A stable high-speed latch circuit, latch, and integrated circuit
By designing a latch circuit consisting of 6 PMOS and 6 NMOS transistors and utilizing a controlled-coupled inverter structure, the problems of signal fluctuation and instability in high-speed latch circuits were solved, achieving stability and low power consumption for high-speed data transmission, reducing circuit area, and meeting the needs of high-speed circuits such as CMOS image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANHUI UNIV
- Filing Date
- 2023-09-21
- Publication Date
- 2026-07-21
AI Technical Summary
Existing high-speed latch circuits suffer from signal fluctuations and instability during high-speed data transmission, making it difficult to meet the requirements of high-speed circuits such as CMOS image sensors.
A latch circuit consisting of 6 PMOS transistors and 6 NMOS transistors is used. Through two controlled-coupled inverter structures, the positive feedback coupling path between the inverters is disconnected during the high level of the clock for sampling and transmission, and the coupling path between the inverters is closed during the low level of the clock for data latching. The operating mode of the latch circuit is controlled by a synchronous inverting signal.
It achieves stable high-speed data transmission and low static power consumption, reduces circuit area and internal resistance, improves integration, and eliminates signal fluctuations during transmission.
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Figure CN117176137B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital logic circuits, specifically relating to a stable high-speed latch circuit, latch, and integrated circuit. Background Technology
[0002] A latch is a level-triggered storage circuit unit. The data storage action is determined by the level of a clock signal. The latch output changes with the input signal only when the latch is enabled; when enabled, the data is stably stored. Based on this special data transmission and retention function, latches are widely used in various integrated circuits, especially in the design of high-speed circuits. Examples include high-speed bus level sampling units, memories, phase-locked loop (PLL) clock dividers, and counters.
[0003] CMOS image sensors include a special signal sampling unit: a column-level single-slope analog-to-digital converter (ADC). This unit typically requires a counter consisting of a one-bit latch and several flip-flops to count the ramp time on both edges. Because ADC circuits have a high conversion bit depth and high conversion rate, a high-speed clock is needed as the base frequency signal to count the counter. Various current applications have a strong demand for high-speed latch circuits.
[0004] Figure 1 This is a circuit diagram of a classic latch. Because the two inverters in this latch are always mutually coupled, when the input data D is opposite to the latched data in the previous state of the inverter node, the pull-down channel formed by NM1, NM3, NM2, and NM4 must have low impedance. This means the NMOS transistor W needs to be relatively large, and there are high requirements for the width (duration) of the CK high-level signal. If the CK high-level signal width is narrow, the pull-down channel will not be sufficient to pull the mutually coupled inverter node low within that time, and the data cannot be latched. This makes the device prone to signal fluctuations during high-speed data transmission, resulting in insufficient stability of high-speed transmission performance.
[0005] Figure 2An improved latch circuit is provided. In this circuit, when the clock is high, NM1 and PM1 are turned on, the transmission gate composed of MN5 and PM5 is turned off, and the inverters composed of MN3, PM3 and NM4, PM4 are decoupled, with the output Q following the input D. When CK is low, NM1 and PM1 are turned off, and the output data D channel is shut off; the transmission gate composed of PM5 and NM5 is closed, and the two inverters couple and latch the data. This circuit adjusts the coupling relationship of the circuit, significantly improving the data transmission rate. However, in this scheme, when CK is high, since the gates of the inverters composed of PM3 and NM3 are connected together, their gate levels are the same, sharing the same charge / discharge channel. When the potential at point K fluctuates, in the initial stage, because the NMOS is still in the on state, the potential of the output node Q is difficult to be pulled high by the PMOS. This will affect the data transmission rate of the device.
[0006] Therefore, how to provide a high-speed latch circuit with faster transmission rate and higher stability has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0007] To address the issue that the transmission rate and data transmission stability of existing latches cannot meet the requirements of high-speed circuits such as CMOS image sensors, this invention provides a stable high-speed latch circuit, latch, and integrated circuit.
[0008] This invention is achieved using the following technical solution:
[0009] A stable high-speed latch circuit is provided, consisting of six PMOS transistors PM1 to PM6 and six NMOS transistors NM1 to NM6. It is used to achieve fast data transmission and stable data retention. The connection relationships of the components in this latch circuit are as follows:
[0010] The drains of PM1 and NM1 are connected to the gates of PM2 and NM2, forming the output node Q; the drains of PM2 and NM2 are connected to the sources of PM2 and NM2, forming the inverting node QB. The output node Q and the inverting node QB have opposite voltage levels.
[0011] The sources of PM4 and PM5 are connected to the drain of PM6, denoted as node N1. The sources of NM4 and NM5 are connected to the drain of NM6, denoted as node M1. The drains of PM4, NM3, and NM5 are connected to the gate of PM1, denoted as node N2. The drains of NM4, PM3, and PM5 are connected to the gate of NM1, denoted as node M2.
[0012] The gates of PM3, NM4, and NM5 are connected and serve as the input of the first clock signal CK; the gates of NM3, PM4, and PM5 are connected and serve as the input of the second time signal CKB. The gates of PM6 and NM6 are connected and serve as the data input D; the sources of PM1, PM2, and PM6 are connected to the power supply VDD; the sources of NM1, NM2, and NM6 are grounded to GND.
[0013] In the stable high-speed latch circuit provided by the present invention, PM1 and NM1 constitute a first inverter, and PM2 and NM2 constitute a second inverter; the coupling state between the first inverter and the second inverter switches according to the state of the first clock signal CK and the second clock signal CKB.
[0014] As a further improvement of the present invention, the first clock signal CK and the second clock signal CKB are a set of synchronous inverted signals, which together serve as the enable signal for the latch circuit.
[0015] As a further improvement of the present invention, when CK in the enable signal is high and CKB is low, the latch circuit is in transmission mode, and the second inverter and the second inverter are decoupled from each other; the output node Q of the first inverter changes synchronously with the input data D.
[0016] As a further improvement of the present invention, when CK in the enable signal is low and CKB is high, the latch circuit is in latch mode, the first inverter and the second inverter are positively fed back together, and data latching is realized.
[0017] In the stable high-speed latching circuit provided by the present invention, PM3 and NM3 serve as a coupling switching pair. The coupling switching pair is used to adjust the coupling state of the first inverter and the second inverter according to the enable signal, so that the first inverter and the second inverter are decoupled in the transmission mode and positively fed back into coupling in the latching mode.
[0018] In the stable high-speed latch circuit provided by this invention, PM4-PM6 and NM4-NM6 serve as the first sampling circuit and the second sampling circuit, respectively; both are used to adjust the isolation state between the input signal and the first inverter. Furthermore, the first sampling circuit is also used to sample the input data D in a low-level state in transmission mode and transmit it to the output node Q. The second sampling circuit is also used to sample the input data D in a high-level state in transmission mode and transmit it to the output node Q.
[0019] The present invention also includes a latch comprising the stable high-speed latch circuit described above, and an inverter. The enable signal of the latch is directly connected to the input of the first clock signal CK, such that the signal is connected to the input of the second clock signal CKB through the inverter.
[0020] As a further improvement of the present invention, the latch ports include: a power supply terminal VDD, a ground terminal GND, an enable terminal EN, an input terminal D, and an output terminal Q. The power supply terminal VDD is connected to the power supply VDD; the ground terminal GND is used for grounding; the enable terminal EN is used as an enable signal to adjust the coupling relationship of the internal circuitry of the latch according to the input, thereby changing the operating mode of the latch. The input terminal D is used to input the data to be transmitted; the output terminal Q is used to output the data input at the input terminal in transmission mode.
[0021] In the latch provided by this invention, when the enable signal is high, the latch is in a transmission state; the output terminal Q transmits the data input to the input terminal D in real time. When the enable signal is low, the latch is in a latching state; the output terminal Q does not change with the input terminal D and retains the data input in the previous clock cycle.
[0022] The present invention also includes an integrated circuit that employs a stable high-speed latch circuit as described above to achieve data transmission or latching.
[0023] The technical solution provided by this invention has the following beneficial effects:
[0024] This circuit utilizes a two-coupled inverter structure to achieve data latching and transmission. During the clock high level, the positive feedback coupling path between the two inverters is broken, and the input signal is sampled and transmitted. During the clock low level, the input signal path is broken, and the positive feedback coupling path between the two inverters is closed, causing the two inverters to be cross-coupled in opposite phases and latching the data. This controllable and adjustable coupling allows the latching circuit to maintain high-speed performance in transmit mode while preserving data in latching mode, keeping most components off and reducing the device's static power consumption.
[0025] The high-speed latch circuit provided by this invention incorporates two sampling circuits to enable separate transmission of high-level and low-level data in transmission mode. This novel circuit design also allows the NMOS and PMOS transistors in the first inverter to be in a separately controlled state, thereby improving the stability of data transmission in the circuit and eliminating signal fluctuation problems during transmission.
[0026] The solution provided by this invention simplifies the circuit topology, reducing static power consumption and effectively saving area while meeting the requirements of high-speed operation. Combined with the optimized circuit layout design, it helps improve device integration. Furthermore, the latch circuit provided in this embodiment uses common-node connections for multiple components, thus saving wire length and reducing device internal resistance in the circuit layout design. This further saves on-chip area and improves integration. Attached Figure Description
[0027] Figure 1 The circuit diagram provided in the background art is a latch circuit with a fixed coupling relationship.
[0028] Figure 2 The circuit diagram is provided in the background section for a latch circuit with controllable coupling.
[0029] Figure 3 This is a circuit diagram of the stable high-speed latch circuit provided in Embodiment 1 of the present invention.
[0030] Figure 4 This is a functional partitioning diagram of the latch circuit provided in Embodiment 1 of the present invention.
[0031] Figure 5 The circuit state diagram for transmitting high-level data in transmission mode of the stable high-speed latch circuit provided in Embodiment 1 of the present invention.
[0032] Figure 6 The circuit state diagram of the stable high-speed latch circuit provided in Embodiment 1 of the present invention for low-level data of ship speed in transmission mode.
[0033] Figure 7 The circuit state diagram for maintaining high-level data in latching mode for the stable high-speed latch circuit provided in Embodiment 1 of the present invention.
[0034] Figure 8 The circuit state diagram for maintaining low-level data in latching mode for the stable high-speed latch circuit provided in Embodiment 1 of the present invention.
[0035] Figure 9 This is a circuit diagram of the latch provided in Embodiment 2 of the present invention.
[0036] Figure 10 The signal waveform diagram obtained during the data transmission-latch cycle test of the stable high-speed latch circuit in Example 1 of the test experiment.
[0037] Figure 11 For testing the experimental example 1 and Figure 1 and Figure 2 The signal waveforms obtained during the performance comparison test of the two comparison circuits are shown.
[0038] Figures 5-8 In a circuit diagram, a component that is hidden in light color indicates that the component is currently off. Detailed Implementation
[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0040] Example 1
[0041] This embodiment provides a stable high-speed latch circuit with two operating modes: a transfer mode and a latch mode. These two modes are used to achieve fast data transfer and stable data storage, respectively. The latch circuit consists of 12 transistors: six PMOS transistors PM1-PM6 and six NMOS transistors NM1-NM6. Figure 3 As shown, the connection relationships of the various components in this high-speed latch circuit are as follows:
[0042] The drains of PM1 and NM1 are connected to the gates of PM2 and NM2, forming the output node Q; the drains of PM2 and NM2 are connected to the sources of PM2 and NM2, forming the inverting node QB. The output node Q and the inverting node QB have opposite voltage levels.
[0043] The sources of PM4 and PM5 are connected to the drain of PM6, denoted as node N1. The sources of NM4 and NM5 are connected to the drain of NM6, denoted as node M1. The drains of PM4, NM3, and NM5 are connected to the gate of PM1, denoted as node N2. The drains of NM4, PM3, and PM5 are connected to the gate of NM1, denoted as node M2.
[0044] The gates of PM3, NM4, and NM5 are connected and serve as the input of the first clock signal CK; the gates of NM3, PM4, and PM5 are connected and serve as the input of the second time signal CKB. The gates of PM6 and NM6 are connected and serve as the data input D; the sources of PM1, PM2, and PM6 are connected to the power supply VDD; the sources of NM1, NM2, and NM6 are grounded to GND.
[0045] The circuit can be divided according to the function of each component, such as... Figure 4 As shown, the latch circuit provided in this embodiment can be divided into an inverter, a coupling switching pair, and a sampling circuit. The inverter includes a first inverter and a second inverter, and the sampling circuit includes a first sampling circuit and a second sampling circuit. The coupling switching pair is used to adjust the coupling relationship between the first inverter and the second inverter according to the clock signal, thereby switching the operating mode of the latch circuit. The first sampling circuit and the second sampling circuit are respectively used to transmit data of different level states from the signal input terminal to the signal output terminal in transmission mode.
[0046] In the stable high-speed latch circuit provided in this embodiment, PM1 and NM1 constitute a first inverter, and PM2 and NM2 constitute a second inverter. The coupling state between the first and second inverters switches according to the states of the first clock signal CK and the second clock signal CKB. The first clock signal CK and the second clock signal CKB together serve as the enable signal for the latch. PM3 and NM3 serve as a coupling switching pair, which is used to adjust the coupling state of the first and second inverters according to the enable signal, so that the first and second inverters are decoupled in transmission mode and positively fed back coupled in latching mode.
[0047] PM4~PM6 and NM4~NM6 serve as the first sampling circuit and the second sampling circuit, respectively. The first sampling circuit is used to sample the input data D in the low-level state in the transmission mode and transmit it to the output node Q. The second sampling circuit is used to sample the input data D in the high-level state in the transmission mode and transmit it to the output node Q.
[0048] In practical application of the latch circuit in this embodiment, the first clock signal CK and the second clock signal CKB are a set of synchronous inverted signals. Because they are inverted, they can generate two signal states. When CK in the enable signal is high and CKB is low, the second inverter and the second inverter are decoupled. At this time, the latch is in transmission mode, and the output node Q of the first inverter changes synchronously with the input data D. When CK in the enable signal is low and CKB is high, the first inverter and the second inverter are positively fed back coupled. At this time, the latch is in latching mode and data latching is achieved.
[0049] The working principle of the latch circuit provided in this embodiment will be explained in detail below, taking different working modes as examples:
[0050] I. Transmission Mode
[0051] When the first clock signal CK is high and the second clock signal CKB is low, the latch circuit is in transmission mode. At this time, PM5 and NM5 are both on, while PM3 and NM3 are both off. The first inverter composed of PM1 and NM1 and the first inverter composed of PM2 and NM2 are decoupled. Therefore, after the input data D is sampled by PM6 or NM6, it will directly drive the first inverter through PM5 and NM5, thereby changing the level state of the output node Q.
[0052] In the latch circuit provided in this embodiment, when the level state of the input data D is different, the signal transmission path that affects the level state of the output node Q in the transmission mode is different.
[0053] Specifically, when the input data D = "1", such as Figure 5 As shown, the gates of NM6 and PM6 are both at a high level. At this time, PM6 is off, while NM6 is on. The input data is sampled and transmitted in the second sampling circuit. In this state, NM6 first pulls node N1 low, and then pulls the levels of nodes N2 and M2 low through NM5 and NM4 respectively. This causes the pull-up transistor PM1 in the first inverter to turn on and NM1 to turn off. At this time, the output node is at a high level, i.e., the output result Q is "1". The latch circuit successfully transmits the data "1" from the data input terminal to the data output terminal in transmission mode.
[0054] When the input data D = "0", such as Figure 6 As shown, the gates of both NM6 and PM6 are at a low level. In this state, NM6 is off, while PM6 is on. The input data is sampled and transmitted in the first sampling circuit. In this state, PM6 first pulls node M1 high, and then pulls the levels of nodes M2 and N2 high through PM5 and PM4 respectively. This causes the pull-down transistor NM1 in the first inverter to conduct and PM1 to turn off. At this time, the output node is at a low level, meaning the output result Q is "0". The latch circuit successfully transmits the data "0" from the data input terminal to the data output terminal in transmission mode.
[0055] Based on the above explanation of the operating principle of the latch circuit in transmission mode, it can be seen that the input signal D in the latch circuit provided in this embodiment only undergoes two stages of transmission delay, and the first inverter and the second inverter are in a decoupled state during this stage. Therefore, the level state of the output node Q can more easily follow the input signal's flip-flops. Consequently, the latch circuit provided in this embodiment has faster data transmission performance in transmission mode.
[0056] II. Latching Mode
[0057] When the first clock signal CK is low and the second clock signal CKB is high, the latch circuit is in transmit mode. At this time, as... Figure 7 and Figure 8 As shown, PM4, NM4, PM5, and NM5 are all in the off state. The first and second inverters to the right of PM6 and NM6 are isolated, meaning the input signal D does not affect the values of the first and second inverters. Meanwhile, PM3 and NM3 are both in the on state. The inverting node QB of the second inverter is connected to the gates of the pull-up transistor PM1 and pull-down transistor NM1 in the first inverter via NM3 and PM3, respectively, thus forming a positive feedback coupling relationship between the first and second inverters. Therefore, the level states of the output node Q and the inverting node QB can be maintained, i.e., stable data latching is achieved.
[0058] Based on the above explanation of the operating principle of the latch circuit in latch mode, it can be seen that in latch mode, the nodes in the first inverter and the second inverter in the latch circuit can achieve reverse cross coupling. Therefore, compared with conventional latches, the latching speed of this embodiment is faster, the data is more stable, and multiple components are in the off state, resulting in lower static power consumption of the device.
[0059] In the latch circuit provided in this embodiment, the switching state of the coupling switch can be adjusted by adjusting the first clock signal CK and the second clock signal CKB, thereby changing the coupling state between the first inverter and the second inverter. Simultaneously, adjusting the clock signals can also change the isolation state between the MOS transistors receiving input data D in the first and second sampling circuits and the first inverter. Therefore, the first clock signal CK and the second clock signal CKB are essentially the enable signals of the latch circuit in this embodiment. The first clock signal CK and the second clock signal CKB in this embodiment can be jointly controlled based on software or hardware. In the hardware implementation, an inverter can be installed before any port. For example, the enable signal can be directly connected to the CK terminal and connected to the CKB terminal via an inverter.
[0060] Example 2
[0061] Based on the scheme in Embodiment 1, this embodiment provides a latch, such as... Figure 9 As shown, it includes a stable high-speed latch circuit as in Embodiment 1, and an inverter. The enable signal of the latch is directly connected to the input of the first clock signal CK, so that the signal is connected to the input of the second clock signal CKB through the inverter.
[0062] Combination Figure 9 As can be seen, the latch provided in this embodiment includes the following ports: power supply terminal VDD, ground terminal GND, enable terminal EN, input terminal D, and output terminal Q. The power supply terminal VDD is used to connect to the power supply VDD; the ground terminal GND is used to ground; the enable terminal EN is used as an enable signal to adjust the coupling relationship of the internal circuitry of the latch according to the input, thereby changing the operating mode of the latch. The input terminal D is used to input the data to be transmitted; the output terminal Q is used to output the data input at the input terminal in transmission mode.
[0063] In the latch provided in this embodiment, when the enable signal is high, the latch is in a transmission state; the output terminal Q transmits the data input to the input terminal D in real time. When the enable signal is low, the latch is in a latching state; the output terminal Q does not change with the input terminal D and retains the data input in the previous clock cycle.
[0064] Example 3
[0065] This embodiment provides an integrated circuit that employs a stable high-speed latch circuit as described in Embodiment 1 to achieve data transmission or latching. This integrated circuit includes, but is not limited to, a high-speed bus level sampling unit, a memory, a phase-locked loop (PLL) clock divider, a counter, and a CMOS image sensor.
[0066] The high-speed latch circuit used in the integrated circuit in this embodiment has advantages such as fast data transmission rate and high data stability, which can fully meet the performance requirements of these high-speed devices for latch circuits.
[0067] Performance testing
[0068] 1. Basic Functionality Test
[0069] To verify the basic performance of the stable high-speed latch circuit designed in Embodiment 1 of the present invention, the circuit in this embodiment is based on 0.18um CMOS technology, the simulation circuit diagram is designed using VIRTUOSO software, and the circuit simulation is performed using ADEL simulation tool.
[0070] During the test, clock signals CK and CKB were both inverted square wave pulse signals. The CK pulse period was 3.7ns, and the high-level pulse width was 150ps. Each time the clock signal CK transitioned to a high level, the latch circuit switched to transmit mode; when the clock signal CK returned to a low level, the latch circuit readjusted to latch mode. The input signal D used a square wave signal with a period of 7.2ns. The waveform of the output signal Q1 during the test is shown below. Figure 10 As shown.
[0071] analyze Figure 10 It can be observed that when the first pulse is generated in the clock signal (2.5ns), the output signal Q1 quickly switches from a low level to a high level, realizing the first transmission of the input data D, which is in a high level state. After the data transmission is completed, the latch circuit is in latch mode. At this time, the output data Q1 remains high, and even when the input data D drops to a low level (4.8ns), the output remains high. When the second pulse is generated in the clock signal (6.2ns), the latch circuit switches back to transmission mode, and the output signal Q1 adjusts to a low level, completing the second data transmission. The output data Q1 then quickly adjusts to a low level following the input data D. This process continues, with the output signal toggling with the input signal in transmission mode and remaining stable in latch mode.
[0072] Combination Figure 10It can be observed that the latch circuit provided in this embodiment can quickly adjust between transmission mode and latching mode when the first clock signal CK and the second clock signal CKB switch to the corresponding level states, accurately realizing data transmission or retention. Furthermore, combined with the waveform diagram of the output signal Q, it can be seen that when the latch circuit of this embodiment is transmitting data, the waveform is approximately a square wave signal with very short falling and rising edge durations. This indicates that the data transmission rate of this device is extremely fast, meeting the requirements for high-speed data transmission.
[0073] 2. Performance Comparison Test
[0074] To further highlight the advantages of the solution in this embodiment, this experiment also used the same testing method to compare and test the two existing latch circuits described in this embodiment and in the background section. The test results are as follows: Figure 11 As shown.
[0075] Figure 11 In the diagram, Q1, Q2, and Q3 represent the circuit, circuit, and circuit of the present invention, respectively. Figure 1 medium circuit and Figure 2 The output signal of the circuit. Analysis. Figure 11 The results show that during the three data transmission processes recorded in the figure, the latching circuit provided in this invention always completed the signal flipping earlier than the two comparative schemes. This demonstrates that the present invention has a higher data transmission speed. At this time, comparing the waveforms of Q1 and Q2, it can be seen that the latching device in the figure has obvious fluctuations in the signal when performing data transmission and latching, while the latching circuit in this invention does not have this problem. This shows that the present invention has higher stability in data transmission and holding states.
[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A stable high-speed latch circuit, characterized in that, It consists of 6 PMOS transistors PM1~PM6 and 6 NMOS transistors NM1~NM6; the circuit connection is as follows: The drains of PM1 and NM1 are connected to the gates of PM2 and NM2, and serve as output nodes Q; the drains of PM2 and NM2 are connected to the sources of PM3 and NM3, and serve as inverting nodes QB; the output nodes Q and inverting nodes QB have opposite voltage levels. The sources of PM4 and PM5 are connected to the drain of PM6, denoted as node M1; the sources of NM4 and NM5 are connected to the drain of NM6, denoted as node N1; the drains of PM4, NM3, and NM5 are connected to the gate of PM1, denoted as node N2; the drains of NM4, PM3, and PM5 are connected to the gate of NM1, denoted as node M2. The gates of PM3, NM4, and NM5 are connected and serve as the input of the first clock signal CK; the gates of NM3, PM4, and PM5 are connected and serve as the input of the second clock signal CKB; the gates of PM6 and NM6 are connected and serve as the data input D; the sources of PM1, PM2, and PM6 are connected to the power supply VDD; the sources of NM1, NM2, and NM6 are grounded to GND.
2. The stable high-speed latch circuit as described in claim 1, characterized in that: PM1 and NM1 constitute the first inverter, and PM2 and NM2 constitute the second inverter; the coupling state between the first inverter and the second inverter switches according to the state of the first clock signal CK and the second clock signal CKB.
3. The stable high-speed latch circuit as described in claim 2, characterized in that: The first clock signal CK and the second clock signal CKB are a set of synchronous inverted signals, which together serve as the enable signal for the latch circuit.
4. The stable high-speed latch circuit as described in claim 3, characterized in that: When the enable signal CK is high and CKB is low, the latch circuit is in transmission mode, and the first inverter and the second inverter are decoupled from each other; the output node Q of the first inverter changes synchronously with the input data D.
5. The stable high-speed latch circuit as described in claim 3, characterized in that: When CK in the enable signal is low and CKB is high, the latch circuit is in latch mode, and the first inverter and the second inverter are positively fed back together to achieve data latching.
6. The stable high-speed latch circuit as described in claim 3, characterized in that: PM3 and NM3 serve as a coupling switching pair; the coupling switching pair is used to adjust the coupling state of the first inverter and the second inverter according to the enable signal, so that the two are decoupled in the transmission mode and positively fed back into coupling in the latching mode.
7. The stable high-speed latch circuit as described in claim 1, characterized in that: PM4~PM6 and NM4~NM6 serve as the first sampling circuit and the second sampling circuit, respectively, and are used to adjust the isolation state between the input signal and the first inverter. The first sampling circuit is also used to sample the input data D in the low-level state in the transmission mode and transmit it to the output node Q. The second sampling circuit is also used to sample the input data D in the high-level state in the transmission mode and transmit it to the output node Q.
8. A latch comprising a stable high-speed latch circuit as described in any one of claims 1-7, and an inverter; wherein an enable signal of the latch is directly connected to the input of a first clock signal CK, and the enable signal is connected to the input of a second clock signal CKB via the inverter.
9. The latch as described in claim 8, characterized in that: The latch's ports include: The power supply terminal VDD is used to connect to the power source. GND, the ground terminal, is used for grounding; The enable terminal EN is used to input an enable signal to adjust the operating mode of the latch; when the enable signal is high, the latch is in the transmission state; when the enable signal is low, the latch is in the latching state. Input terminal D is used to input data for latching or transmission; The output terminal Q is used to output the data input by the input terminal in transmission mode.
10. An integrated circuit, characterized in that, It employs a stable high-speed latching circuit as described in any one of claims 1-7 to achieve data transmission or latching.