Signal receiving apparatus and signal equalization method thereof
By introducing a frequency detector and a speed judgment circuit into the signal receiving device, a speed judgment signal is generated to adjust the equalizer operating parameters, thus solving the problem of signal quality degradation under different signal speeds and achieving efficient signal equalization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NAN YA TECH
- Filing Date
- 2022-07-12
- Publication Date
- 2026-07-21
AI Technical Summary
Existing equalizer-based receivers cannot adjust to different signal speed levels, resulting in a decline in signal quality.
A frequency detector and speed judgment circuit are used to generate a speed judgment signal by detecting the phase and frequency of the clock signal. Based on this signal, the equalizer operation parameters are adjusted to adapt to different signal speeds.
It achieves effective signal equalization based on signal speed level, thereby improving signal quality.
Smart Images
Figure CN117176191B_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to a signal receiving device, and more specifically, to an equalizer-based signal receiving device and its signal equalization method. Background Technology
[0002] In conventional technology, the platform controller needs to receive input signals and perform equalization to improve the quality of the processed signals. For controllers deployed on different platforms, signals with different speed levels need to be processed by the controller; however, these speed levels cannot be distinguished by the controller's equalizer-based receiver. In equalizer-based receivers, the front-end equalizer is easily affected by the speed level of each individual input signal. Therefore, the equalizer-based receiver needs to be adjusted according to the speed level of the corresponding input signal, thus reducing the influence of the controller. Summary of the Invention
[0003] The present invention provides a signal receiving device and a signal equalization method thereof, the method being able to perform equalization operations for applications with different signal speeds.
[0004] The signal receiving device structure includes a frequency detector, a speed determination circuit, and an equalizer-based signal receiver. The frequency detector receives a clock signal and a first reference signal, and detects the phase and frequency of the clock signal based on the first reference signal to generate a detection result. The speed determination circuit is coupled to the frequency detector and generates a speed determination signal based on the detection result. The equalizer-based signal receiver is coupled to the speed determination circuit, receives the speed determination signal, and determines the equalizer operating parameters based on the speed determination signal.
[0005] The present invention provides a signal equalization method, comprising: receiving a clock signal and a first reference signal; detecting the phase and frequency of the clock signal based on the first reference signal to generate a detection result; generating a speed judgment signal based on the detection result; and receiving the speed judgment signal and determining equalizer operating parameters based on the speed judgment signal.
[0006] To make the foregoing more understandable, several embodiments, accompanied by accompanying drawings, are described in detail below. Attached Figure Description
[0007] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
[0008] Figure 1 A schematic diagram of a signal receiving apparatus according to an embodiment of the present disclosure is shown;
[0009] Figure 2A schematic diagram illustrating the relationship between a speed determination signal, a lead flag, a lag flag, and a threshold according to an embodiment of the present disclosure;
[0010] Figure 3 A schematic diagram illustrating the relationship between speed determination signals and speed determination signals according to embodiments of the present disclosure;
[0011] Figure 4 A flowchart illustrating a signal equalization method according to an embodiment of the present disclosure is shown;
[0012] Figure 5 A flowchart of a signal equalization method according to another embodiment of the present disclosure is shown.
[0013] Explanation of icon numbers
[0014] 100: Signal receiving device;
[0015] 110: Frequency detector;
[0016] 120: Speed detection circuit;
[0017] 130: Equalizer-based signal receiver;
[0018] CLK: Clock signal;
[0019] DR: Test results;
[0020] EFT1~EFTN: Candidate feedback time;
[0021] ES1~ESN: Candidate equalizer strengths;
[0022] FR1~FRN: bit;
[0023] JS: Speed detection signal;
[0024] IN1: Input signal;
[0025] OUT: Output signal;
[0026] REF1, REF2: Reference signals;
[0027] S410, S420, S430, S440, S510, S520, S530, S540: Steps. Detailed Implementation
[0028] Reference will now be made to the presently preferred embodiments of the invention in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.
[0029] Please refer to Figure 1This diagram illustrates a signal receiving apparatus according to an embodiment of the present disclosure. The signal receiving apparatus 100 includes a frequency detector 110, a speed determination circuit 120, and an equalizer-based signal receiver 130. The frequency detector 110 receives a clock signal CLK and a reference signal REF1. The frequency detector 110 detects the frequency and phase of the clock signal CLK based on the reference signal REF1 to generate a detection result DR. In this embodiment, both the clock signal CLK and the reference signal REF1 are periodic signals. The frequency detector 110 compares the frequency of the clock signal CLK with the frequency of the reference signal REF1 and compares the phase of the clock signal CLK with the phase of the reference signal REF1 to generate the detection result DR. Specifically, the detection result DR may include a lead flag, a lag flag, and a difference signal. If the frequency of the clock signal CLK is higher than the frequency of the reference signal REF1, the frequency detector 110 may enable the lead flag. If the frequency of the clock signal CLK is lower than the frequency of the reference signal REF1, the frequency detector 110 may enable the lag flag. Furthermore, the frequency detector 110 can generate a difference signal based on the difference in phase and frequency between the clock signal CLK and the reference signal REF1.
[0030] Speed determination circuit 120 is coupled to frequency detector 110. Speed determination circuit 120 receives a detection result DR containing a lead flag, a lag flag, and a difference signal. Speed determination circuit 120 generates a speed determination signal JS based on the detection result DR. Speed determination circuit 120 can generate a multi-bit speed determination signal JS based on the lead flag, lag flag, and difference signal. Specifically, based on enabled lead and lag flags, speed determination circuit 120 compares the difference signal with multiple thresholds to generate multiple bits of the speed determination signal JS.
[0031] In detail, if the lead flag is enabled (and the lag flag is disabled), the speed determination circuit 120 can generate a speed determination signal JS based on the difference signal, wherein the speed determination signal JS is positively correlated with the difference signal. Conversely, if the lag flag is enabled (and the lead flag is disabled), the speed determination circuit 120 can generate a speed determination signal JS based on the difference signal, wherein the speed determination signal JS is negatively correlated with the difference signal.
[0032] For example, the speed determination signal JS can have multiple bits FR1 to FRN, where bit FR1 is the least significant bit (LSB) and bit FRN is the most significant bit (MSB). When the lead flag is enabled and the difference signal is at its maximum, bit FRN can be enabled, and other bits FR1 can be disabled to FRN-1. When the lead flag is enabled and the difference signal is at its minimum, bit FR1 can be enabled, and other bits FR2 can be disabled to FRN. On the other hand, when the lag flag is enabled and the difference signal is at its minimum, bit FRN can be enabled, and other bits FR1 can be disabled to FRN-1; and when the lag flag is enabled and the difference signal is at its maximum, bit FR1 can be enabled, and other bits FR2 can be disabled to FRN.
[0033] Each of the lead and lag flags can be implemented using a single bit of a register. If the lead flag is enabled and the lag flag is disabled, the lead flag can be at a first logic value and the lag flag can be at a second logic value. If the first logic value is logic 1, the second logic value is logic 0. If the first logic value is logic 0, the second logic value is logic 1.
[0034] The equalizer-based signal receiver 130 is coupled to the speed determination circuit 120. The equalizer-based signal receiver 130 receives a speed determination signal JS and determines the equalizer operating parameters based on the speed determination signal JS. In this embodiment, the equalizer-based signal receiver 130 further receives an input signal IN1 and a reference signal REF2. The input signal IN1 and the reference signal REF2 may come from a differential signal pair or a reference voltage. The equalizer-based signal receiver 130 performs a signal equalization operation on the input signal IN1 according to the speed determination signal JS to generate an output signal OUT.
[0035] In detail, the equalizer-based signal receiver 130 can determine equalizer operating parameters, namely equalizer feedback time or equalizer intensity, based on the speed judgment signal JS. In one embodiment, the equalizer-based signal receiver 130 can perform signal equalization operation based on the equalizer feedback time, which is determined according to the speed judgment signal JS. In another embodiment, the equalizer-based signal receiver 130 can perform signal equalization operation based on the equalizer intensity, which is determined according to the speed judgment signal JS.
[0036] Please refer to this together. Figure 1 and Figure 2 ,in Figure 2 A schematic diagram of an equalizer-based signal receiver for determining the equalizer strength for equalization operation, according to an embodiment of the present disclosure, is shown. Figure 2In the speed judgment signal JS, multiple bits FR1 to FRN are included, where each bit corresponds to a candidate equalizer strength ES1 to candidate equalizer strength ESN. The equalizer-based signal receiver 130 receives the speed judgment signal JS containing the bits FR1 to FRN. The equalizer-based signal receiver 130 can determine the equalizer strength used to perform the equalization operation by selecting one of the candidate equalizer strengths ES1 to candidate equalizer strength ESN based on the enabled bits FR1 to FRN. For example, if bit FR1 of the speed judgment signal JS is enabled (logic 1), the equalizer-based signal receiver 130 can determine that the equalizer strength is equal to the candidate equalizer strength ES1. If bit FRN of the speed judgment signal JS is enabled (logic 1), the equalizer-based signal receiver 130 can determine that the equalizer strength is equal to the candidate equalizer strength ESN. In this embodiment, the candidate equalizer strength ES1 can be 0, and if the equalizer strength is set to be equal to the candidate equalizer strength ES1, the equalization operation can be disabled.
[0037] Please refer to this together. Figure 1 and Figure 3 ,in Figure 3 A schematic diagram of an equalizer-based signal receiver for determining the equalizer feedback time for equalization operation, according to another embodiment of the present disclosure, is shown. Specifically, the equalizer-based signal receiver 130 receives bits FR1 to FRN of the speed determination signal JS, and determines the equalizer feedback time for the signal equalization operation based on the enabled bits in bits FR1 to FRN. In this embodiment, bits FR1 to FRN of the speed determination signal JS correspond to multiple candidate feedback times EFTN to candidate feedback time EFT1.
[0038] By reference Figure 3 If bit FR1 is enabled, the equalizer-based signal receiver 130 can determine the equalizer feedback time used for performing signal equalization operations as the highest candidate feedback time EFTN. If bit FR2 is enabled, the equalizer-based signal receiver 130 can determine the equalizer feedback time used for performing signal equalization operations as the candidate feedback time EFTN-1. Furthermore, if bit FRN is enabled, the equalizer-based signal receiver 130 can determine the equalizer feedback time used for performing signal equalization operations as the lowest candidate feedback time EFT1.
[0039] Note here that the equalizer-based signal receiver 130 may include a decision feedback equalizer (DFE) or a linear equalizer for performing signal equalization operations. The decision feedback equalizer or linear equalizer may be implemented using any equalizer circuitry well known to those skilled in the art, and there are no particular limitations herein.
[0040] On the other hand, the frequency detector 110 can be implemented using any phase and frequency detection circuit known in the art. The speed determination circuit 120 can be implemented using multiple comparators and logic circuits. When the difference signal is a digital code, the speed determination circuit 120 can, for example, use an XOR gate to perform a comparison operation to generate a detection result. In some embodiments, the difference signal can be time information, and the speed determination circuit 120 can sample the time information to convert the difference signal into a digital code.
[0041] In this disclosure, the signal receiving device 100 has an adjustable equalizer feedback time for equalization operations corresponding to different input speed levels. That is, the signal receiving device 100 can be applied to circuit operations on different platforms, and equalization operations can be performed well within the signal receiving device.
[0042] Please refer to Figure 4 The diagram illustrates a flowchart of a signal equalization method according to an embodiment of the present disclosure. In step S410, phase and frequency information of a clock signal is acquired using a frequency detector. Next, in step S420, the phase and frequency difference between the clock signal and a reference signal can be detected using the frequency detector. Thus, the input speed level can be detected using the frequency detector.
[0043] In step S430, a speed determination signal may be generated by the speed determination circuit. The speed determination circuit generates the speed determination signal based on the detection result obtained in step S420. The details of obtaining the speed determination signal have been described in the previous embodiments and will not be repeated here.
[0044] In step S440, the equalization operation can be determined by an equalizer-based signal receiver based on multiple bits of the speed judgment signal. Specifically, the equalizer-based signal receiver can determine the equalizer operation parameters for the equalization operation based on the bits of the speed judgment signal obtained in step S430.
[0045] Please refer to Figure 5 The diagram illustrates a flowchart of a signal equalization method according to another embodiment of the present disclosure. In step S510, a clock signal and a first reference signal are received by a frequency detector. In step S520, the phase and frequency of the clock signal can be detected based on the first reference signal to generate a detection result by the frequency detector. In step S530, a speed determination signal can be generated by a speed determination circuit based on the detection result. In step S540, the equalizer feedback time or equalizer strength can be determined by an equalizer-based signal receiver based on the speed determination signal. Then, the equalizer performs an equalization operation on the input signal based on the equalizer feedback time, wherein the equalizer feedback time can be precisely adjusted according to the speed level of the input signal.
[0046] In summary, the signal receiving apparatus of this disclosure provides a frequency detector for detecting the phase and frequency of a clock signal, and a speed determination circuit to convert the phase and frequency of the clock signal into a speed determination signal that can be coded digitally. Thus, the equalizer-based signal receiver can adjust the equalizer feedback time according to the speed determination signal, and can perform equalization operations on input signals with different speed levels.
[0047] It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover such modifications and variations, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.
Claims
1. A signal receiving device, comprising: A frequency detector receives a clock signal and a first reference signal, both of which are periodic signals, and detects the phase and frequency differences between the clock signal and the first reference signal to generate a detection result. A speed determination circuit is coupled to the frequency detector and generates a speed determination signal based on the detection result. as well as The equalizer-based signal receiver is coupled to the speed judgment circuit, receives the speed judgment signal, and determines the equalizer operation parameters based on the speed judgment signal.
2. The signal receiving apparatus according to claim 1, wherein the detection result includes a lead flag, a lag flag, and a difference signal, and the frequency detector enables the lead flag or the lag flag by detecting whether the phase of the clock signal is ahead or behind the phase of the first reference signal, and the frequency detector generates the difference signal based on the difference in phase and frequency between the clock signal and the first reference signal.
3. The signal receiving device according to claim 2, wherein the speed determination circuit generates the speed determination signal having multiple bits based on the lead flag, the lag flag, and the difference signal.
4. The signal receiving device according to claim 3, wherein when the lead flag is enabled, the speed determination signal is positively correlated with the difference signal.
5. The signal receiving device according to claim 3, wherein when the hysteresis flag is enabled, the speed determination signal is negatively correlated with the difference signal.
6. The signal receiving apparatus according to claim 3, wherein the speed determination circuit compares the difference signal with a plurality of thresholds to generate the plurality of bits of the speed determination signal, wherein the plurality of thresholds respectively correspond to the plurality of bits of the speed determination signal.
7. The signal receiving apparatus according to claim 6, wherein the equalizer-based signal receiver further receives an input signal and a second reference signal, and the equalizer-based signal receiver performs a signal equalization operation on the input signal according to the speed judgment signal.
8. The signal receiving apparatus of claim 7, wherein the equalizer-based signal receiver determines the equalizer feedback time or equalizer strength by judging one of the plurality of bits of the signal based on the enabled speed.
9. A signal equalization method, comprising: The receiver receives a clock signal and a first reference signal, both of which are periodic signals. The phase and frequency differences between the clock signal and the first reference signal are detected to generate a detection result; A speed determination signal is generated based on the detection results; as well as The speed judgment signal is received and the equalizer operation parameters are determined based on the speed judgment signal.
10. The signal equalization method according to claim 9, wherein the detection result includes a lead flag, a lag flag, and a difference signal, and the detection of the phase and frequency of the clock signal based on the first reference signal to generate the detection result includes: The lead flag or the lag flag is enabled by detecting whether the phase of the clock signal leads or lags the phase of the first reference signal. as well as The difference signal is generated based on the difference in phase and frequency between the clock signal and the first reference signal.
11. The signal equalization method according to claim 10, wherein the step of generating the speed judgment signal based on the detection result includes: The speed judgment signal with multiple bits is generated based on the leading flag, the lagging flag, and the difference signal.
12. The signal equalization method according to claim 11, wherein when the lead flag is enabled, the speed judgment signal is positively correlated with the difference signal; and when the lag flag is enabled, the speed judgment signal is negatively correlated with the difference signal.
13. The signal equalization method according to claim 11, wherein the step of generating the speed judgment signal based on the detection result further comprises: The difference signal is compared with a plurality of thresholds to generate the plurality of bits of the speed determination signal, wherein the plurality of thresholds respectively correspond to the plurality of bits of the speed determination signal.
14. The signal equalization method according to claim 13, comprising receiving the speed judgment signal and determining the equalizer feedback time or equalizer strength based on the speed judgment signal, including: Receive input signal and second reference signal; as well as The input signal is subjected to signal equalization operation based on the speed determination signal.
15. The signal equalization method according to claim 14, wherein the step of receiving the speed judgment signal and determining the equalizer operating parameters according to the speed judgment signal further comprises: Based on the enabled speed, one of the multiple bits of the signal is used to generate the equalizer feedback time or equalizer strength.