A method for regenerable pseudocode ranging applied to deep space transponders

Abstract

This invention provides a method for regenerated pseudo-code ranging applied to deep space transponders. The method involves converting the uplink pseudo-code ranging signal via a receiving channel to output a second intermediate frequency (IF) pseudo-code ranging signal, which is then processed by a baseband module. The baseband module uses an FPGA as its core processing chip, along with peripheral AD, DA, and RAM circuitry. The baseband module acquires, tracks, and demodulates the uplink pseudo-code ranging signal, then forwards the downlink regenerated pseudo-code ranging signal via a transmitting channel. Within the baseband module, a carrier acquisition and tracking module based on a phase-locked loop (PLL) utilizes gate information from a carrier pre-estimation module to lock onto the residual carrier frequency offset, thereby achieving uplink carrier acquisition and tracking. This invention, while maintaining high-sensitivity pseudo-code demodulation, further reduces software resource consumption, achieving reliable demodulation of -148 dBm, an acquisition time better than 150 seconds, and optimizing pseudo-code module resource usage to approximately 6% of total resources.

Description

Technical Field

[0001] This application relates to the field of satellite telemetry, tracking and command, and in particular to a method for implementing regenerated pseudocode ranging for deep space transponders. Background Technology

[0002] As a crucial component of the telemetry, tracking, and command (TT&C) subsystem, the deep-space transponder provides a bidirectional radio frequency transmission channel between the satellite and the TT&C station, working in conjunction with the TT&C station to perform tasks such as satellite tracking, remote control, and telemetry. Due to the long distance between the satellite and the ground, the uplink signal-to-noise ratio is low. During relay, the noise power will exceed the ranging signal power, and most of the noise will be transmitted to the downlink through the ranging channel, thus reducing the receiver's signal-to-noise ratio.

[0003] Regenerative pseudocode ranging is an emerging technology in deep space ranging systems. In deep space ranging, transparent forwarding ranging suffers from drawbacks such as low ranging accuracy, small unambiguous range, and low acquisition and demodulation sensitivity. Compared to transparent forwarding ranging, regenerative pseudocode ranging offers advantages such as high ranging accuracy and a large unambiguous range.

[0004] In recent years, as deep space exploration missions have gradually developed towards ultra-long-distance communication, and the demand for long-distance ranging has been increasing, it is essential to add pseudo-code ranging functionality to deep space transponders. Summary of the Invention

[0005] To further meet the needs of long-distance ranging in deep space exploration missions, this invention designs a regenerated pseudocode ranging implementation method for deep space transponders. While satisfying the requirements of high-sensitivity pseudocode demodulation, it proposes an implementation method that reduces software resource consumption.

[0006] The present invention adopts the following technical solution:

[0007] A method for regenerated pseudocode ranging applied to deep space transponders is characterized in that the uplink pseudocode ranging signal is frequency-converted by the receiving channel and output as a second intermediate frequency pseudocode ranging signal to the baseband module for processing. The baseband module uses an FPGA as the core processing chip, in conjunction with peripheral AD chips, DA chips, and RAM circuitry. The baseband module is used to acquire, track, and demodulate the uplink pseudocode ranging signal, and then forwards the downlink regenerated pseudocode ranging signal through the transmitting channel. In the baseband module, the carrier acquisition and tracking module is based on a phase-locked loop and uses the gate information from the carrier pre-estimation module to lock the residual carrier frequency offset, thereby achieving the acquisition and tracking of the uplink carrier.

[0008] Furthermore, the digital phase-locked loop is a third-order digital phase-locked loop that automatically adapts and dynamically adjusts its loop parameters based on changes in the normalized carrier-to-noise ratio and the Doppler frequency shift rate.

[0009] Furthermore, in baseband carrier acquisition and tracking, after the received intermediate frequency signal is sampled by AD, one path is orthogonally downconverted with a direct digital frequency synthesizer (DDS), then decimation filtering is performed, and carrier FFT calculation is performed; the other path signal and I / Q signal are phase-locked loop (PLL) detected and filtered, synthesized, and a loop-locked decision is generated.

[0010] Furthermore, the carrier pre-estimation module is an open-loop estimation module based on carrier FFT calculation. Through FFT calculation, the uplink coherent Doppler frequency fd and the current carrier-to-noise ratio estimate C / N can be obtained. The carrier pre-estimation module provides fd and C / N as gate information to the subsequent carrier acquisition and tracking module.

[0011] Furthermore, the baseband module includes a monitoring FPGA, a processing FPGA, and RAM. The RAM chip is used for data buffering. The processing FPGA is used to implement the core functions of carrier acquisition, tracking, regeneration of pseudocode signals, demodulation, and regeneration. The monitoring FPGA is responsible for dynamically refreshing the baseband FPGA configuration area frame by frame and monitoring the baseband FPGA status telemetry. If an abnormality occurs, the baseband FPGA is reset.

[0012] Furthermore, the FFT analysis results from carrier pre-acquisition and the acquired uplink receive channel automatic gain control (AGC) voltage value are used for comprehensive analysis and judgment to obtain a normalized carrier-to-noise ratio (CNR) estimate. This CNR estimate is then used to drive the phase-locked loop (PLL) loop parameter switching logic, thereby driving the PLL to work and complete carrier acquisition and tracking.

[0013] Furthermore, the ±100kHz spectrum range is segmented into multiple spectrum segments. Then, FFT calculations are performed on each spectrum segment in a time-division and alternating manner, ensuring a certain overlap between each spectrum segment to avoid signal loss and distortion that may occur near the edges of the spectrum segments.

[0014] Furthermore, the entire spectrum range is divided into 14 spectrum segments, and an external cache RAM is used to enable high-speed reading directly from the cache without waiting for the 1 second of sample points required for FFT calculation during segment estimation.

[0015] Furthermore, the phase-locked loop noise bandwidth is:

[0016]

[0017] in, k is the loop gain, τ1 and τ2 are the loop bandwidth indicator coefficients, and γ is set to approximately 2 by setting the loop parameters.

[0018] Furthermore, the pseudocode demodulation process employs a combined serial-parallel computational structure for the subcode-related structures.

[0019] The present invention achieves the following beneficial technical effects:

[0020] This design proposes a method for implementing a deep-space transponder with regenerative pseudo-code ranging, which further reduces software resource consumption while meeting high-sensitivity pseudo-code demodulation requirements. Compared to the performance of conventional pseudo-code ranging (around -130dBm), the pseudo-code ranging in this invention can achieve reliable demodulation at -148dBm, with an acquisition time better than 150s, and the pseudo-code module resource consumption can be optimized to about 6% of the total resources. Attached Figure Description

[0021] Figure 1 This is a hardware block diagram of the baseband module;

[0022] Figure 2 This is a block diagram of a baseband carrier acquisition and tracking system.

[0023] Figure 3 Block diagram for the design and implementation of adaptive switching of baseband loop;

[0024] Figure 4 Block diagram of segmented estimation scheme for baseband FPGA+RAM solution;

[0025] Figure 5 This is a flowchart of the calculation related to the pseudocode ranging subcode. Detailed Implementation

[0026] The regenerated pseudocode ranging method for deep space transponders, as described in the accompanying drawings and examples, will be further explained. In this specification, f0 is the receiving intermediate frequency, and fd is the uplink coherent Doppler frequency.

[0027] The baseband module of this invention uses an FPGA as the core processing chip, in conjunction with peripheral AD chips, DA chips, and RAM circuits, to acquire, track, and demodulate the pseudo-code ranging signal before forwarding the downlink regenerated pseudo-code ranging signal. The uplink pseudo-code ranging signal is frequency-converted by the receiving channel to output a dual-IF pseudo-code ranging signal. This signal is then processed by the baseband module to acquire, track, and demodulate the pseudo-code ranging signal, and is then forwarded as a downlink regenerated pseudo-code ranging signal through the transmitting channel.

[0028] The X-band deep space transponder mainly consists of three modules: an RF channel module, a digital baseband module, and a crystal oscillator module. After receiving the uplink RF signal, the receiving channel performs down-conversion processing and sends the signal to the baseband module as an intermediate frequency (IF) signal. After narrowband filtering, the signal is sent to an AD (analog-to-digital converter) chip for processing. The hardware platform used in the digital baseband signal processing circuit is a combination of a monitoring FPGA (A54SX72A) and a processing FPGA (XQR4VSX55). External components such as AD converters, DA converters, and RAM complete the main signal flow. An additional RAM chip is used for data buffering to implement the software algorithm. The processing FPGA implements core functions such as carrier acquisition, tracking, regeneration, pseudocode signal demodulation, and regeneration. The monitoring FPGA is responsible for dynamically refreshing the processing FPGA configuration area frame by frame and monitoring the baseband FPGA status via telemetry. If an anomaly is detected, the baseband FPGA is reset. Figure 1 The baseband module hardware block diagram is shown below. Figure 1 As shown.

[0029] Before demodulating the uplink pseudocode ranging signal, carrier acquisition and tracking are performed first. The carrier acquisition and tracking module is based on a third-order phase-locked loop and uses the gate information from the carrier pre-estimation module to lock onto the residual carrier frequency offset, thereby achieving uplink carrier acquisition and tracking.

[0030] The internal implementation of the carrier module can be divided into two parts: the carrier pre-estimation module and the carrier acquisition and tracking module. Figure 2 Here is a block diagram of a baseband carrier acquisition and tracking system, such as Figure 2 As shown, after the received intermediate frequency (IF) signal is sampled by an AD converter, one path undergoes quadrature down-conversion with a DDS (Direct Digital Synthesizer), followed by decimation filtering and carrier FFT calculation. The other path signal, along with the I / Q signal, undergoes phase detection and filtering via a digital phase-locked loop (PLL), and is then synthesized to generate a loop-locked decision. The carrier pre-estimation module is an open-loop estimation module based on carrier FFT calculation. Through FFT calculation, the uplink coherent Doppler frequency fd and the current estimated carrier-to-noise ratio (C / N) can be obtained. The carrier pre-estimation module provides fd and C / N as gate information to the subsequent carrier acquisition and tracking module.

[0031] The carrier acquisition and tracking module is based on a third-order phase-locked loop (PLL). It utilizes the gate information from the carrier pre-estimation module to lock onto the residual carrier frequency offset, thereby achieving uplink carrier acquisition and tracking. Carrier acquisition and tracking needs to adapt to different normalized carrier-to-noise ratios (CNRs) and different Doppler shift rates. However, based on extensive simulation analysis, the stable parameters of the third-order loop are not consistent under different CNRs and Doppler shift rates.

[0032] To ensure the reliable operation of the deep-space transponder under various mission scenarios, this invention designs a loop adaptive switching mechanism based on signal-to-noise ratio (SNR). The third-order digital phase-locked loop (PLL) for carrier acquisition and tracking needs to automatically adapt and dynamically adjust the loop parameters according to changes in the normalized carrier-to-noise ratio (CNR) and the Doppler frequency shift rate.

[0033] The primary basis for adaptive switching of loop parameters is the normalized carrier-to-noise ratio (CNR). A relatively accurate CNR estimate needs to be obtained before the carrier-locked loop (PLL) is stably locked in. In other words, adaptive loop switching requires high accuracy, stability, and timeliness in CNR estimation.

[0034] Figure 3 This is a block diagram illustrating the design and implementation of adaptive switching for the baseband loop. (See diagram below.) Figure 3 As shown, in the adaptive switching design of the baseband loop parameters of this invention, after performing FFT analysis on the carrier baseband signal, the signal-to-noise ratio (SNR) is estimated using the FFT analysis results during carrier pre-acquisition. This result is then compared with the acquired uplink receiving channel AGC voltage value to estimate the carrier-to-noise ratio (CNR). In other words, a comprehensive analysis and judgment is performed using the FFT analysis results during carrier pre-acquisition and the acquired uplink receiving channel AGC (Automatic Gain Control) voltage value, thereby obtaining a more accurate, stable, and real-time normalized CNR estimation result. This CNR estimation result drives the phase-locked loop (PLL) loop parameter switching logic, which in turn drives the PLL to operate and complete carrier acquisition and tracking.

[0035] In the intermediate frequency (IF) processing unit, the received IF signal is converted by an analog-to-digital converter (ADC) and then processed by the digital processing module. Ignoring signal amplitude information and noise, the received low-IF signal can be represented as:

[0036] s(t)=cos[2πf0t+βC(t)+φ]

[0037] Where f0 is the intermediate frequency carrier frequency, φ is the initial phase of the intermediate frequency carrier, β is the ranging modulation, and C(t) is the ranging pseudocode sequence.

[0038] Assuming the AD sampling rate is 4f0, after AD sampling:

[0039]

[0040] After the carrier is fully synchronized, the local carrier frequency and phase are the same as the frequency and phase of the received signal. After quadrature downconversion, the data of the I / Q (in-phase and quadrature) paths are as follows:

[0041]

[0042]

[0043] Since β takes a small value, cos[βC(t)] is approximately a constant value of 1, and Q(k)≈βC(k), that is, Q-channel data can be used to demodulate ranging information.

[0044] In deep space telemetry and communication, since PM (phase modulation) modulation is used, the system first obtains carrier synchronization during demodulation, so the frequency deviation of the carrier is not considered during pseudocode synchronization, and the main focus is on code space search and synchronization.

[0045] The pseudo-code ranging system takes the received uplink PN (pseudo-random) baseband signal as input and outputs the regenerated PN code and lock indicator. The system mainly consists of two parts: a pseudo-code tracking CTL (chip timing tracking loop) loop and local sub-code regeneration. The former extracts the PN code clock and code clock phase, while the latter determines the correct phase of the PN and generates the regenerated PN output. The pseudo-code ranging system module comprises the pseudo-code tracking CTL loop and the local sub-code regeneration. The pseudo-code tracking CTL loop is crucial for ensuring the ranging accuracy of the system in forwarding mode.

[0046] The key to designing a pseudocode tracking CTL loop lies in the selection of loop parameters. The known loop noise bandwidth is:

[0047]

[0048] in, k is the loop gain, and τ1 and τ2 are the loop bandwidth indication coefficients. Because B L Since it cannot be infinite, γ must be greater than 1 / 2. By setting the loop parameters and taking γ around 2, the CTL loop can be stably locked under low signal-to-noise ratio conditions and have a small jitter variance.

[0049] To reduce system resource consumption, an FPGA+RAM scheme is designed to assist in FFT carrier estimation. The implementation method of carrier pre-estimation FFT calculation is equivalently transformed using RAM chips, which can further reduce software resource consumption without sacrificing carrier acquisition time. Figure 4 The block diagram for the segmented estimation scheme of the baseband FPGA+RAM solution is shown below. The software implementation process is described in [link to software implementation details]. Figure 4 As shown, the intermediate frequency signal f0+fd and the local signal f0 are orthogonally downconverted to obtain the uplink Doppler fd. The filtered and downsampled data is stored in the RAM chip. The spectrum segmentation control multiplies the segmented bandwidth signal Δf with fd and shifts the signal to near the 0 frequency. At the same time, the signal is filtered and sampled and then the spectrum peak is searched.

[0050] To simultaneously guarantee the ±100kHz capture range and SNR (signal-to-noise ratio) performance requirements, a "speed for area" design principle is adopted. The ±100kHz spectrum range is divided into 14 sub-segments. Then, FFT calculations are performed on each sub-segment in a time-division, alternating manner. A certain overlap is maintained between the sub-segments to avoid potential signal loss and distortion near their edges.

[0051] To avoid performance loss, the FPGA+RAM solution continues to be designed with a 1Hz FFT resolution, dividing the entire frequency band into 14 segments. The RAM chip is used to store the data for FFT calculations. The introduction of the RAM chip eliminates the need to wait for the 1-second sampling points required for FFT calculations during segment estimation. Instead, the data is read directly from the RAM chip at high speed, reducing the time required for uplink Doppler fd estimation. This further reduces the waiting time for carrier acquisition even with the increased number of spectrum segments.

[0052] To further reduce system resource consumption, an external cache RAM is used, which eliminates the need to wait for the 1-second sample point required for FFT calculation during segment estimation. The data can be read directly from the cache at high speed, reducing the time required for fd (uplink coherent Doppler frequency) estimation. This ensures that the overall carrier acquisition time meets the performance requirements even with an increase in the number of spectrum segments.

[0053] To further reduce system resource consumption, a combined serial-parallel computational structure was adopted for the subcode-related structures during pseudocode demodulation. Figure 5 This is a flowchart of the correlation calculation for the pseudocode ranging subcode. Figure 5 As shown, the serialization degree is designed to be 3, meaning that one correlation calculation unit serially calculates 3 correlation results, reducing the parallelism to 1 / 3 of the fully parallel structure. Taking subcode 6 as an example, with a length of 23, the fully parallel structure has 23 subcode correlation calculation units, which consumes a lot of software resources; the resource-reducing structure with a serialization degree of 3 only requires 8 correlation calculation units, consuming fewer software resources, thus reducing software resource consumption.

[0054] It should be noted that the above description is merely illustrative and explanatory of the present invention. Those skilled in the art should understand that any modifications and substitutions to the present invention fall within the scope of protection of the present invention.

Claims

1. A regenerative pseudo-code ranging implementation method applied to a deep space transponder, characterized in that, The system converts the uplink pseudo-code ranging signal through the receiving channel and outputs a second intermediate frequency pseudo-code ranging signal to the baseband module for processing. The baseband module uses an FPGA as the core processing chip, along with peripheral AD chips, DA chips, and RAM circuitry. The baseband module is used to capture, track, and demodulate the uplink pseudo-code ranging signal. Then, it forwards the downlink regenerated pseudo-code ranging signal through the transmitting channel. In the baseband module, the carrier acquisition and tracking module is based on a digital phase-locked loop and uses the gate information from the carrier pre-estimation module to lock the residual carrier frequency offset, thereby achieving the acquisition and tracking of the uplink carrier. In baseband carrier acquisition and tracking, the received intermediate frequency signal is sampled by AD, and one path is orthogonally downconverted by a direct digital frequency synthesizer (DDS), then decimation filtering is performed, and carrier FFT calculation is performed; the other path signal and I / Q signal are phase-locked loop (PLL) detected and filtered, synthesized, and a loop-locked decision is generated. The carrier pre-estimation module is an open-loop estimation module based on carrier FFT calculation. Through FFT calculation, the uplink coherent Doppler frequency fd and the current carrier-to-noise ratio estimate C / N can be obtained. The carrier pre-estimation module provides fd and C / N as gate information to the subsequent carrier acquisition and tracking module.

2. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 1, characterized in that, The digital phase-locked loop is a third-order digital phase-locked loop that automatically adapts and dynamically adjusts its loop parameters based on changes in the normalized carrier-to-noise ratio and the Doppler frequency shift rate.

3. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 1, characterized in that, The baseband module includes a monitoring FPGA, a processing FPGA, and RAM. The RAM chip is used for data buffering. The processing FPGA is used to implement the core functions of carrier acquisition, tracking, regeneration of pseudocode signals, demodulation, and regeneration. The monitoring FPGA is responsible for dynamically refreshing the baseband FPGA configuration area frame by frame and monitoring the baseband FPGA status telemetry. If an abnormality occurs, the baseband FPGA is reset.

4. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 1, characterized in that, The FFT analysis results from carrier pre-estimation and the collected uplink receiver channel automatic gain control (AGC) voltage value are used for comprehensive analysis and judgment to obtain a normalized carrier-to-noise ratio (CNR) estimate. This CNR estimate drives the phase-locked loop (PLL) loop parameter switching logic, which in turn drives the PLL to work and complete carrier acquisition and tracking.

5. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 1, characterized in that, The ±100kHz spectrum range is segmented into multiple spectrum segments. Then, FFT calculations are performed on each spectrum segment in a time-division and alternating manner. A certain overlap area is ensured between each spectrum segment to avoid signal loss and distortion near the edges of the spectrum segments.

6. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 5, characterized in that, The entire spectrum range is divided into 14 spectrum segments, and an external cache RAM is used so that segment estimation does not need to wait for the 1 second of sample points required for FFT calculation, but can directly read from the cache at high speed.

7. The regenerative pseudo-code ranging implementation method for deep space transponders according to claim 1, characterized in that, During the demodulation of the pseudocode, a combined serial-parallel computational structure is used for the subcode-related structures.

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