System and method for implementing optimized tsn frame preemption ip core based on FPGA

Abstract

The application discloses a system for realizing optimized TSN frame preemption IP core based on FPGA, which comprises a credit flow shaping IP core, a frame preemption scheduling module, etc. The credit flow shaping IP core is used for receiving flow data and putting the flow data into different priority queues based on the priority of the flow data. The frame preemption scheduling module receives the flow data sent by the credit flow shaping IP core and sends a scheduling strategy switching feedback signal to the credit flow shaping IP core. In the case that the frame preemption condition is not met, the CBS algorithm is used to set fixed credit value parameters for each flow transmission queue, so as to reduce the problem of high-speed frame delay caused by long standard Ethernet frames or super-large pre-emptible frames, and the co-network transmission of high-speed frames and pre-emptible frames. The application realizes the logical function of the frame preemption MAC merge sublayer based on FPGA, and realizes stable and reliable data transmission on a hardware circuit. When the frame preemption condition is met, the frame preemption flow scheduling function can be normally executed, and then the flexible switching of the frame preemption function and the credit value flow shaping function is achieved.

Description

Technical Field

[0001] This invention belongs to the field of industrial internet technology, and in particular relates to a system and method for optimizing TSN frame preemption IP cores based on FPGA. Background Technology

[0002] With the development of network technology, the Internet has been widely used in industrial control. The Industrial Internet requires lower latency, less jitter, and lower packet loss and error rates during data transmission. Time-Sensitive Networking (TSN) provides crucial Quality of Service (QoS) guarantees for the real-time reliable transmission of the Industrial Internet. In TSN, traffic scheduling plays a vital role. Specifically, the frame preemption techniques defined by the IEEE Std 802.1Qbu and IEEE 802.3br protocols ensure that eMAC frames can interrupt the transmission of standard Ethernet frames or very large frames, preventing significant congestion caused by very large frame transmissions.

[0003] However, the problem of high-speed frame latency caused by longer standard Ethernet frames or oversized preemptible frames when frame preemption conditions are not met needs further resolution. Summary of the Invention

[0004] To address the aforementioned issues, the present invention provides a system and method for optimizing TSN frame preemption IP cores based on FPGA. The core of this system is the implementation of a TSN frame preemption IP core based on FPGA. When the communication node does not meet the frame preemption conditions, a fixed credit value parameter (i.e., fixed bandwidth allocation) is set for each traffic transmission queue (which has priorities) using the CBS algorithm (Credit Based Shaper). This ensures deterministic transmission of high-speed frames under preemption conditions and allows for shared network transmission of both high-speed and preemptible frames. Simultaneously, when the frame preemption conditions are met, the frame preemption traffic scheduling function defined by IEEE 802.1Qbu and IEEE 802.1br can be executed normally, thus achieving flexible switching between frame preemption and credit value traffic shaping functions.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: a system for optimizing TSN frame preemption IP cores based on FPGA, built on a field-programmable gate array (FPGA), comprising: a credit traffic shaping IP core, used to receive traffic data and place traffic data into queues of different priorities based on the priority of the traffic data, wherein traffic data passing through the credit traffic shaping IP core is allocated a fixed transmission bandwidth; a frame preemption scheduling module, which receives traffic data sent by the credit traffic shaping IP core and sends a scheduling strategy switching feedback signal to the credit traffic shaping IP core; the frame preemption scheduling module includes a MAC merging sublayer, wherein the MAC merging sublayer determines whether the node supports frame preemption function, and after the credit traffic shaping IP core, time-sensitive data frames and non-time-sensitive data frames are mapped to eMA. C-frames and pMAC frames are transmitted via the eMAC channel and pMAC channel, respectively. The traffic data includes time-sensitive data frames and non-time-sensitive data frames, with time-sensitive data frames having a higher priority than non-time-sensitive data frames. If the node supports frame preemption, when the network needs to transmit eMAC frames and the frame preemption policy is enabled, the transmission of the pMAC channel is paused and switched to the eMAC channel to transmit the eMAC frames, thus achieving normal frame preemption scheduling. If the frame preemption policy is not enabled or the frame preemption conditions are not met, the credit traffic shaping IP core is activated, and the eMAC frames and pMAC frames are allocated to different priority queues. Each queue is assigned a corresponding credit value to achieve deterministic transmission of eMAC frames and reduce the transmission delay of eMAC frames caused by pMAC frame blocking.

[0006] Preferably, the MAC merging sublayer further includes a traffic identification module, a traffic reception control module, a traffic scheduling strategy switching module, and a traffic transmission control module. The traffic identification module identifies the frame header of the traffic data. When SMD-E is identified, the traffic data is transmitted to the eMAC channel through the reception control module; otherwise, it is transmitted to the pMAC channel through the reception control module. The traffic reception control module is used to restore pMAC slice frames, transmit pMAC frames and eMAC frames, and transmit frame preemption verification frames. The traffic scheduling strategy switching module receives the frame preemption verification frame from the traffic reception control module and feeds back the verification result to the traffic transmission control module through the frame preemption enable signal Frame_Prp_en to enable the frame preemption scheduling strategy, and sends the enable signal Frame_Prp_en to the credit traffic shaping IP core. The traffic transmission control module is used to control the transmission of pMAC frame slices, pMAC frames, and eMAC frames.

[0007] Preferably, the frame preemption scheduling module includes an eMAC channel and a pMAC channel. The eMAC channel sends a request signal Tx_eMAC_Request to the pMAC channel to request frame preemption. If the eMAC receives a request response signal Tx_eMAC_Response from the pMAC, it suspends the current pMAC transmission and transmits fast frames via the eMAC. The pMAC channel slices the pMAC frame into a first frame, a middle frame, and a last frame. According to the three frame type formats, after slicing, the first frame will have an mCRC checksum generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx. The middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then a modulo-4 fragment count Frame_cnt will be added. The last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then a modulo-4 fragment count Frame_cnt will be added. The checksum at the end of the last frame is the checksum (FCS) of the original pMAC frame type.

[0008] Preferably, the traffic receiving control module uses a two-level frame check method to check the received data frames: when traffic data is received, a CRC check is first performed directly, and the CRC_CHK_ERR signal is set to indicate the correctness of the frame check. If the frame check is incorrect, the signal is set to a high level, otherwise it is set to a low level; the mCRC_CHK_ERR signal is set to check the correctness of the pMAC slice frame. If the frame check is incorrect, the signal is set to a high level, otherwise it is set to a low level.

[0009] Preferably, the traffic receiving control module determines the frame type of the received traffic data based on SMD-E, SMD-Sx, and SMD-Cx. If it is a complete data frame, it is directly passed through to the eMAC channel, pMAC channel, or traffic scheduling strategy switching module; otherwise, a frame reassembly and restoration operation is performed. The frame reassembly and restoration process is as follows: mPacket frames with continuous frame delimiters and continuous fragment counts are combined into a complete pMAC frame and transmitted. If the mPacket frames are not continuous, the part of the mPacket frames is discarded.

[0010] Preferably, the traffic scheduling strategy switching module receives a pre-preemption enable signal Pre_Frame_Prp_en from the traffic transmission control module to determine whether a frame meets the preemption condition. If the signal is high, preemption occurs; otherwise, the preemption condition is not met. If either the frame preemption enable signal Frame_Prp_en or the pre-preemption enable signal Pre_Frame_Prp_en is low, the traffic scheduling strategy switching module will generate a scheduling strategy switching signal Mode_Switch and feed it back to the credit traffic shaping IP core to enable the credit value traffic scheduling strategy.

[0011] Preferably, the traffic transmission control module receives a frame preemption enable signal Frame_Prp_en from the traffic scheduling strategy switching module. If the signal is high, it indicates that the frame preemption scheduling strategy can be enabled; otherwise, it is low and the frame preemption scheduling strategy cannot be enabled.

[0012] Preferably, the traffic identification module encapsulates the highest priority traffic data into an eMAC frame through the eMAC layer defined in the IEEE 802.1br protocol standard, and encapsulates the traffic data other than the highest priority into a pMAC frame through the pMAC layer. The specific encapsulation method is as follows: the 8th byte of the header of the highest priority traffic data is replaced with SMD-E, and the 8th byte of the header of the traffic data other than the highest priority is replaced with SMD-Sx to form a pMAC frame. The SMD-E value and the SFD value of the eMAC frame are the same, both being 0xd5.

[0013] Based on the same concept, this invention also provides a method for optimizing TSN frame preemption IP cores based on FPGA, applicable to any of the systems described above, comprising the following steps: receiving traffic data, determining whether the current node supports frame preemption function and the current scheduling policy, and sending a scheduling policy switching feedback signal to the credit traffic shaping IP core; when the current scheduling policy is a frame preemption traffic scheduling policy, encapsulating the highest priority traffic data into eMAC frames through the eMAC layer defined in the IEEE 802.1br protocol standard, and encapsulating traffic data other than the highest priority into pMAC frames through the pMAC layer; and enabling the eMAC channel to transmit eMAC frames and the pMAC channel to transmit pMAC frames based on a preset program.

[0014] Preferably, the transmission of eMAC frames by the eMAC channel and the transmission of pMAC frames by the pMAC channel based on a preset program further includes: the eMAC channel sending a request signal Tx_eMAC_Request to the pMAC channel request frame preemption; if the eMAC receives a request response signal Tx_eMAC_Response from the pMAC, the current pMAC transmission is paused, and only the transmission of eMAC frames by the eMAC channel is retained; the pMAC channel slices the pMAC frame into a first frame, a middle frame, and a last frame. According to the three frame type formats, after the pMAC frame is sliced, the first frame will have an mCRC checksum generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then the modulo-4 fragment count Frame_cnt will be added; the last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then the modulo-4 fragment count Frame_cnt will be added, and the checksum at the end of the last frame will be the checksum (FCS) of the original pMAC frame type.

[0015] Based on the same concept, the present invention also provides an electronic device, comprising: a memory for storing a processing program; and a processor, wherein the processor, when executing the processing program, implements the method for optimizing TSN frame preemption IP cores based on FPGA as described above.

[0016] Based on the same concept, the present invention also provides a readable storage medium storing a processing program, which, when executed by a processor, implements the method for optimizing TSN frame preemption IP cores based on FPGA as described above.

[0017] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art:

[0018] 1. Through this invention, when the frame preemption condition is not met, a fixed credit value parameter (i.e., fixed bandwidth allocation) can be set for each traffic transmission queue (which has priority) using the CBS algorithm (Credit Based Shaper). This reduces the high-speed frame latency caused by long standard Ethernet frames or very large preemptible frames, and also enables the shared transmission of high-speed frames and preemptible frames.

[0019] 2. The MAC merging sublayer in the technical solution of this invention identifies the frame type of traffic data, determines whether preemption is supported, encapsulates eMAC and pMAC frames, and slices pMAC frames into first, middle, and last frames. According to the three frame type formats, after slicing, the first frame of the pMAC frame will have an mCRC check value generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added; the last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added. The check value at the end of the last frame is the checksum (FCS) of the original pMAC frame type, thereby efficiently and automatically realizing the frame preemption function, and automatically resuming the transmission of pMAC frames after the preemption transmission of eMAC frames is completed. Attached Figure Description

[0020] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, wherein:

[0021] Figure 1 This is a block diagram of the system for implementing an optimized TSN frame preemption IP core based on FPGA according to the present invention;

[0022] Figure 2 This is a block diagram of the MAC merging sublayer based on FPGA in this invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0024] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0025] First Embodiment

[0026] like Figure 1The diagram illustrates a block diagram of a system for optimizing TSN frame preemption IP cores based on an FPGA. Built on a Field-Programmable Gate Array (FPGA), the system includes: a credit traffic shaping IP core, used to receive traffic data and place it into queues of different priorities based on the data's priority; traffic data passing through the credit traffic shaping IP core is allocated a fixed transmission bandwidth; a frame preemption scheduling module, which receives traffic data sent by the credit traffic shaping IP core and sends a scheduling policy switching feedback signal to it; the frame preemption scheduling module includes a MAC merging sublayer, which determines whether the node supports frame preemption functionality. After the credit traffic shaping IP core, time-sensitive and non-time-sensitive data frames are mapped to eMAC frames and pMA frames. C-frames are transmitted via both the eMAC and pMAC channels. The traffic data includes time-sensitive and non-time-sensitive data frames, with time-sensitive data frames having higher priority than non-time-sensitive data frames. If the node supports frame preemption, when the network needs to transmit an eMAC frame and frame preemption is enabled, the transmission of the pMAC channel is paused and switched to the eMAC channel to transmit the eMAC frame, thus achieving normal frame preemption scheduling. If frame preemption is not enabled or the frame preemption conditions are not met, the credit traffic shaping IP core is activated, allocating eMAC and pMAC frames to different priority queues and assigning corresponding credit values ​​to each queue, thus achieving deterministic transmission of eMAC frames and reducing the transmission delay of eMAC frames caused by pMAC frame blocking.

[0027] See Figure 2 The diagram shows a block diagram of a MAC merging sublayer based on FPGA. The MAC merging sublayer also includes a traffic identification module, a traffic receiving control module, a traffic scheduling strategy switching module, and a traffic sending control module.

[0028] The traffic identification module identifies the frame header of the traffic data. When SMD-E is identified, the traffic data is transmitted to the eMAC channel through the receiving control module; otherwise, it is transmitted to the pMAC channel through the receiving control module.

[0029] The traffic reception control module is used to restore pMAC slice frames, transmit pMAC frames, eMAC frames, and transmit frame preemption verification frames.

[0030] The traffic scheduling strategy switching module receives a frame preemption verification frame from the traffic receiving control module, and feeds back the verification result to the traffic sending control module through the frame preemption enable signal Frame_Prp_en to enable the frame preemption scheduling strategy, and sends the enable signal Frame_Prp_en to the credit traffic shaping IP core.

[0031] The traffic transmission control module is used to control the transmission of pMAC frame slices, pMAC frames, and eMAC frames.

[0032] Traffic first passes through a credit-based traffic shaping IP core. Within the IP core, traffic is placed into queues of different priorities based on its priority type, with priorities decreasing from 7 to 0. The specific functions and implementation methods of this IP core can be found in the patent "A Credit-Based Traffic Scheduling System and Method in a Time-Sensitive Network" (Application No.: CN202310146107.6). Traffic passing through the IP core will be allocated a fixed transmission bandwidth, thus determining the transmission delay for this type of traffic. After processing by the IP core, the traffic enters frame preemption scheduling. It should be noted that the frame preemption scheduling function of this invention is also entirely implemented based on FPGA. The frame preemption verification module in the MAC merging sublayer determines whether the node supports frame preemption. The condition for this determination is that each transmitted data frame must meet the minimum frame length, i.e., 64 bytes (including the checksum field), including sliced ​​data frames. Once this condition is met, the frame preemption strategy can be enabled. After enabling the frame preemption policy, time-sensitive data frames will be mapped to eMAC frames and pMAC frames, which are transmitted by the eMAC layer and pMAC layer respectively. The eMAC layer transmits fast frames (eMAC frames), and the pMAC layer transmits preemptible frames (pMAC frames). When the network needs to transmit fast frames and the frame preemption policy is enabled, the transmission on the pMAC channel will be paused and switched to the eMAC channel to transmit fast frames, achieving normal frame preemption scheduling. If the frame preemption policy is not enabled or the frame preemption conditions are not met, the credit value traffic scheduling policy will be activated, allocating fast frames and preemptible frames to different priority queues and assigning corresponding credit values ​​(bandwidth) to each queue, achieving deterministic transmission of fast frames and reducing the transmission latency of high-speed frames caused by low-speed frame congestion. The specific technical steps are as follows:

[0033] Step 1: Upon receiving the Mode_Switch scheduling policy switching signal from the traffic scheduling policy switching module, the credit-based traffic shaping algorithm IP core is enabled. Different traffic flows are allocated to corresponding queues based on their priority, and a credit value parameter is configured for each queue, i.e., bandwidth is allocated. The specific steps are as follows:

[0034] (1) Calculate the credit value parameter for each queue based on the data frame sending period and size.

[0035] (2) Calculate the credit values ​​hiCredit and loCredit of the upper and lower bounds of the constrained queue based on the maximum interference frame length in the queue and the maximum frame length transmitted.

[0036] These parameters can be configured by the user in advance according to the corresponding application scenario, and can be enabled when the frame preemption conditions are not met.

[0037] Specifically, the formula for calculating credit score is:

[0038]

[0039] In the formula, CMI is the data frame transmission period, i.e., the measurement interval, and reservedBytes is the number of bits in the transmitted data frame;

[0040] After calculating the idleSlope for each queue, the calculation process for the sendSlope, a consumption parameter representing the rate at which credit consumption decreases for each queue, is as follows:

[0041] sendSlope N =idleSlope N -portTransmitRate

[0042] In the formula, portTransmitRate is the port transmission rate.

[0043] Configure the highest credit value (hiCredit) and lowest credit value (loCredit) for each queue. These settings constrain the maximum number of data frames a queue can carry and the maximum frame length it can transmit. The highest credit value (hiCredit) is determined by the maximum length of interfering frames in the queue, and the loCredit is determined by the maximum frame length transmitted in the queue. Specifically:

[0044]

[0045]

[0046] Where maxInterference is the maximum interference frame length of the queue, and maxFrameSize is the maximum frame length transmitted in the queue.

[0047] The frame preemption scheduling strategy will not be satisfied in two situations: first, the link does not support frame preemption after passing the frame preemption verification frame; second, the preemptible frame does not meet the minimum frame length of 64 bytes for preemption. In both cases, high-speed frames will only begin transmission after low-speed frames have finished transmitting, making the transmission of high-speed frames uncertain. Therefore, enabling this IP core in these situations allows for the allocation of fixed bandwidth to both high-speed and low-speed frames, and a strict priority algorithm ensures that higher-priority frames are transmitted first.

[0048] This invention enables the reduction of high-speed frame latency caused by long standard Ethernet frames or oversized preemptible frames, as well as the co-transmission of high-speed frames and preemptible frames, by setting fixed credit value parameters (i.e. fixed bandwidth allocation) for each traffic transmission queue (which has priority) using the CBS algorithm (Credit Based Shaper) when frame preemption conditions are not met.

[0049] Step 2: Encapsulate the highest priority frame into a fast frame through the eMAC layer defined in the IEEE 802.1br protocol standard, and encapsulate the frames other than the highest priority frame into preemptible frames through the pMAC layer. The specific encapsulation method is as follows: replacing the 8th byte of the frame header with SMD-E (SMD: Start mPacket Delimiter) results in a fast frame, and replacing the 8th byte of the frame header with SMD-Sx results in a preemptible frame. The SMD-E value and SFD value of the fast frame are the same, both being 0xd5.

[0050] Step 3: The traffic scheduling strategy switching module in the MAC merging sublayer completes the scheduling mode switch. This module has two functions: first, it verifies whether the link supports frame preemption; second, based on the above judgment, it sets the corresponding enable signal to select which scheduling strategy to enable. If frame preemption is satisfied, it proceeds to Step 4 to enter frame preemption traffic scheduling; otherwise, it switches to Step 1 to execute the credit value traffic scheduling strategy.

[0051] Step 4: Implement MAC merging sublayer frame preemption scheduling function based on FPGA. For example... Figure 2 The diagram shows a block diagram of a MAC merging sublayer design based on FPGA. The MAC merging sublayer IP core mainly includes the following sub-modules: traffic transmission control module, traffic reception control module, traffic scheduling strategy switching module, traffic identification module, as well as eMAC interface and pMAC interface.

[0052] The traffic identification module filters eMAC and pMAC frames using SMD-E and SMD-Sx in the frame header. If SMD-E is detected, the fast frame is passed to the eMAC; otherwise, it is passed to the traffic reception control module for processing.

[0053] The flow reception control module is responsible for restoring pMAC slice frames, transmitting pMAC frames and eMAC frames, and transmitting frame preemption verification frames. The specific steps are as follows:

[0054] (1) A two-level frame check method is used to check the received data frames. When a data frame is received, a CRC check is performed directly first, and the CRC_CHK_ERR signal is set to indicate the correctness of the frame check. If the frame check is incorrect, the signal is set to a high level; otherwise, it is set to a low level. At the same time, the mCRC_CHK_ERR signal is set to check the correctness of the slice frame check. If the frame check is incorrect, the signal is set to a high level; otherwise, it is set to a low level.

[0055] (2) Determine the frame type of the received data frame based on SMD-E, SMD-Sx, and SMD-Cx. If it is a complete data frame, it will be directly passed through to the eMAC, pMAC, or traffic scheduling strategy switching module. Otherwise, a frame reassembly and restoration operation will be performed.

[0056] (3) Frame reassembly and restoration process. mPacket frames with consecutive frame delimiters and consecutive fragment counts are assembled into a complete preemptible frame and transmitted. If they are not consecutive, it indicates that the mPacket frames that make up the preemptible packet are lost, the framing is incorrect, and that part of the mPacket frame is discarded.

[0057] The traffic transmission control module is responsible for the transmission of pMAC frame slices, pMAC frames, and eMAC frames. The specific steps are as follows:

[0058] (1) Receive the frame preemption enable signal Frame_Prp_en from the traffic scheduling strategy switching module. If the signal is high, it means that the frame preemption scheduling strategy can be enabled; otherwise, it is low and the frame preemption scheduling strategy cannot be enabled.

[0059] (2) Fast frame transmission. The eMAC sends a request signal Tx_eMAC_Request to the pMAC to request a frame preemption. If the eMAC receives a request response signal Tx_eMAC_Response from the pMAC, it suspends the current pMAC transmission and the eMAC transmits the fast frame.

[0060] (3) Preemptible frame slicing and transmission. Preemptible frames are sliced ​​into first frame, middle frame and last frame. According to the three frame type formats, after the preemptible frame is sliced, the first frame will have an mCRC check value generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have the frame start delimiter in the header replaced with SMD-Cx, and the frame modulo 4 fragment count Frame_cnt will be added after that; the last frame will be operated in the same way as the middle frame, the only difference being that the check value at its end is the checksum of the original frame type FCS. Before preemptible frame slicing, (2) must be executed to determine whether the pMAC frame has the conditions for preemption (i.e., whether the length of the data already sent is greater than 64 bytes, and whether the data of the remaining preemptible packets is greater than 64 bytes).

[0061] The traffic scheduling policy switching module is responsible for verifying whether the link supports frame preemption and setting the corresponding enable signal to select which scheduling policy to enable. This module receives frame preemption verification frames from the traffic reception control module and feeds back the verification result to the traffic transmission control module via the frame preemption enable signal Frame_Prp_en to enable the frame preemption scheduling policy. Simultaneously, it receives the pre-preemption enable signal Pre_Frame_Prp_en from the traffic transmission control module to determine if a frame meets the preemption conditions. If this signal is high, preemption occurs; otherwise, the preemption conditions are not met. If either the frame preemption enable signal Frame_Prp_en or the pre-preemption enable signal Pre_Frame_Prp_en is low, the traffic scheduling policy switching module will generate a scheduling policy switching signal Mode_Switch and feed it back to the credit traffic shaping IP core to enable the credit-based traffic scheduling policy.

[0062] The eMAC interface side and the pMAC interface side transmit fast frames and preemptible frames respectively. Considering the application scenarios with high traffic, in order to avoid traffic overflow and packet loss, a dual-port RAM is used in the FPGA to buffer the fast frames and preemptible frames received and sent respectively.

[0063] This invention implements the logic function of the frame preemption MAC merging sublayer based on FPGA, and achieves stable and reliable data transmission on the hardware circuit.

[0064] In addition, through this invention, when the frame preemption conditions are met, the frame preemption traffic scheduling function defined by IEEE 802.1Qbu and IEEE 802.1br can be executed normally, thereby achieving flexible switching between the frame preemption function and the credit value traffic shaping function.

[0065] Second Embodiment

[0066] Based on the same concept, this invention also provides a method for optimizing TSN frame preemption IP cores based on FPGA, applicable to any of the systems described above, comprising the following steps: receiving traffic data, determining whether the current node supports frame preemption function and the current scheduling policy, and sending a scheduling policy switching feedback signal to the credit traffic shaping IP core; when the current scheduling policy is a frame preemption traffic scheduling policy, encapsulating the highest priority traffic data into eMAC frames through the eMAC layer defined in the IEEE 802.1br protocol standard, and encapsulating traffic data other than the highest priority into pMAC frames through the pMAC layer; and enabling the eMAC channel to transmit eMAC frames and the pMAC channel to transmit pMAC frames based on a preset program.

[0067] Preferably, the transmission of eMAC frames by the eMAC channel and the transmission of pMAC frames by the pMAC channel based on a preset program further includes: the eMAC channel sending a request signal Tx_eMAC_Request to the pMAC channel request frame preemption; if the eMAC receives a request response signal Tx_eMAC_Response from the pMAC, the current pMAC transmission is paused, and only the transmission of eMAC frames by the eMAC channel is retained; the pMAC channel slices the pMAC frame into a first frame, a middle frame, and a last frame. According to the three frame type formats, after the pMAC frame is sliced, the first frame will have an mCRC checksum generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then the modulo-4 fragment count Frame_cnt will be added; the last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then the modulo-4 fragment count Frame_cnt will be added, and the checksum at the end of the last frame will be the checksum (FCS) of the original pMAC frame type.

[0068] Third Embodiment

[0069] Based on the same concept, the present invention also provides an electronic device, characterized in that it includes: a memory for storing a processing program; and a processor, wherein the processor, when executing the processing program, implements the method for optimizing TSN frame preemption IP core based on FPGA as described above.

[0070] Based on the same concept, the present invention also provides a readable storage medium, characterized in that the readable storage medium stores a processing program, which, when executed by a processor, implements the method for optimizing TSN frame preemption IP cores based on FPGA as described above.

[0071] If the method for optimizing TSN frame preemption IP cores based on FPGA is implemented as program instructions and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in software. This computer software is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific identification content executed by the system and device described above can be referred to the corresponding process in the foregoing method embodiments.

[0073] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A system for implementing an optimized TSN frame preemption IP core based on FPGA, characterized in that, include: The credit traffic shaping IP core is used to receive traffic data and place the traffic data into queues of different priorities based on the priority of the traffic data. The traffic data passing through the credit traffic shaping IP core is allocated a fixed transmission bandwidth. The frame preemption scheduling module receives traffic data sent by the credit traffic shaping IP core and sends a scheduling strategy switching feedback signal to the credit traffic shaping IP core; The frame preemption scheduling module includes a MAC merging sublayer. The MAC merging sublayer determines whether a node supports the frame preemption function. After the credit traffic is shaped into IP cores, time-sensitive data frames and non-time-sensitive data frames are mapped into eMAC frames and pMAC frames, which are transmitted by the eMAC channel and pMAC channel, respectively. The traffic data includes time-sensitive data frames and non-time-sensitive data frames, and the priority of the time-sensitive data frames is higher than that of the non-time-sensitive data frames. If the node supports frame preemption, when the network needs to transmit eMAC frames and the frame preemption policy is enabled, the transmission of the pMAC channel is paused and the transmission of eMAC frames is switched to the eMAC channel to achieve normal frame preemption scheduling. If the frame preemption policy is not enabled or the frame preemption conditions are not met, the credit traffic shaping IP core is activated to allocate eMAC frames and pMAC frames to different priority queues and assign corresponding credit values ​​to each queue, thereby achieving deterministic transmission of eMAC frames and reducing the transmission delay of eMAC frames caused by pMAC frame blocking. The MAC merging sublayer also includes a traffic identification module, a traffic receiving control module, a traffic scheduling strategy switching module, and a traffic sending control module; The traffic identification module identifies the frame header of the traffic data. When SMD-E is identified, the traffic data is transmitted to the eMAC channel through the receiving control module; otherwise, it is transmitted to the pMAC channel through the receiving control module. The traffic reception control module is used to restore pMAC slice frames, transmit pMAC frames, eMAC frames, and transmit frame preemption verification frames. The traffic scheduling strategy switching module receives a frame preemption verification frame from the traffic receiving control module, and feeds back the verification result to the traffic sending control module through the frame preemption enable signal Frame_Prp_en to enable the frame preemption scheduling strategy, and sends the enable signal Frame_Prp_en to the credit traffic shaping IP core. The traffic transmission control module is used to control the transmission of pMAC frame slices, pMAC frames, and eMAC frames. The traffic scheduling strategy switching module receives a pre-preemption enable signal Pre_Frame_Prp_en from the traffic transmission control module to determine whether a frame meets the preemption condition. If the signal is high, preemption occurs; otherwise, the preemption condition is not met. If either the frame preemption enable signal Frame_Prp_en or the pre-preemption enable signal Pre_Frame_Prp_en is low, the traffic scheduling strategy switching module will generate a scheduling strategy switching signal Mode_Switch and feed it back to the credit traffic shaping IP core to enable the credit value traffic scheduling strategy.

2. The system for implementing optimized TSN frame preemption IP core based on FPGA according to claim 1, characterized in that, The frame preemption scheduling module includes an eMAC channel and a pMAC channel. The eMAC channel sends a request signal Tx_eMAC_Request to the pMAC channel to request frame preemption. If the eMAC receives a request response signal Tx_eMAC_Response from the pMAC, it suspends the current pMAC transmission and the eMAC transmits fast frames. The pMAC channel slices the pMAC frame into a first frame, middle frames, and a last frame. According to the three frame type formats, after the pMAC frame is sliced, the first frame will have an mCRC check value generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added; the last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added. The check value at the end of the last frame is the checksum (FCS) of the original pMAC frame type.

3. The system for implementing optimized TSN frame preemption IP core based on FPGA according to claim 1, characterized in that, The flow receiving control module uses a two-level frame check method to check the received data frames: When traffic data is received, a CRC check is performed first, and the CRC_CHK_ERR signal is set to indicate the correctness of the frame check. If the frame check is incorrect, the signal is set to a high level; otherwise, it is set to a low level. The mCRC_CHK_ERR signal is set to verify the correctness of pMAC slice frames. If the frame verification is incorrect, the signal is set to high level; otherwise, it is set to low level.

4. The system for implementing optimized TSN frame preemption IP core based on FPGA according to claim 3, characterized in that, The traffic receiving control module determines the frame type of the received traffic data based on SMD-E, SMD-Sx, and SMD-Cx. If it is a complete data frame, it is directly passed through to the eMAC channel, pMAC channel, or traffic scheduling strategy switching module; otherwise, a frame reassembly and restoration operation is performed. The frame reassembly and restoration process is as follows: mPacket frames with consecutive frame delimiters and consecutive fragment counts are combined into a complete pMAC frame and transmitted; if the mPacket frames are not consecutive, the part of the mPacket frame is discarded.

5. The system for implementing optimized TSN frame preemption IP core based on FPGA according to claim 1, characterized in that, The traffic transmission control module receives the frame preemption enable signal Frame_Prp_en from the traffic scheduling strategy switching module. If the signal is high, it indicates that the frame preemption scheduling strategy can be enabled; otherwise, it is low and the frame preemption scheduling strategy cannot be enabled.

6. The system for implementing optimized TSN frame preemption IP core based on FPGA according to claim 1, characterized in that, The traffic identification module encapsulates the highest-priority traffic data into eMAC frames using the eMAC layer defined in the IEEE 802.1br protocol standard, and encapsulates traffic data other than the highest priority traffic data into pMAC frames using the pMAC layer. The specific encapsulation method is as follows: The 8th byte of the header of the highest priority traffic data is replaced with SMD-E, and the 8th byte of the header of traffic data other than the highest priority is replaced with SMD-Sx for pMAC frames. The SMD-E value and SFD value of the eMAC frame are the same, both being 0xd5.

7. A method for optimizing TSN frame preemption IP cores based on FPGA, applied to the system described in any one of claims 1-6, characterized in that, Includes the following steps: Receive traffic data, determine whether the current node supports frame preemption and the current scheduling policy, and send a scheduling policy switching feedback signal to the credit traffic shaping IP core; When the current scheduling strategy is a frame preemption traffic scheduling strategy, the traffic data with the highest priority is encapsulated into an eMAC frame through the eMAC layer defined in the IEEE 802.1 br protocol standard, and the traffic data other than the highest priority is encapsulated into a pMAC frame through the pMAC layer. The preset program enables the eMAC channel to transmit eMAC frames and the pMAC channel to transmit pMAC frames.

8. The method for optimizing TSN frame preemption IP cores based on FPGA according to claim 7, characterized in that, The transmission of eMAC frames by the eMAC channel and the transmission of pMAC frames by the pMAC channel based on the preset procedure further includes: the eMAC channel sending a request signal Tx_eMAC_Request to the pMAC channel request frame preemption; if the eMAC receives the request response signal Tx_eMAC_Response from the pMAC, the current pMAC transmission is paused, and only the transmission of eMAC frames by the eMAC channel is retained. The pMAC channel slices the pMAC frame into a first frame, middle frames, and a last frame. According to the three frame type formats, after the pMAC frame is sliced, the first frame will have an mCRC check value generated by the mCRC generator added to its end, and the frame start delimiter in the header will be replaced with SMD-Sx; the middle frame will have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added; the last frame will first have its frame start delimiter in the header replaced with SMD-Cx, and then the frame modulo 4 fragment count Frame_cnt will be added. The check value at the end of the last frame is the checksum (FCS) of the original pMAC frame type.

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