Switching chip and control method

Abstract

The embodiment of the application discloses a switching chip and a control method. The switching chip comprises a serializer, a mapping circuit and a protocol controller group. The protocol controller group comprises at least two protocol controllers. The serializer is used for sending mapping parameters to the mapping circuit. The mapping circuit is used for determining a mapping relationship between the serializer and a target protocol controller based on the mapping parameters. The target protocol controller is a protocol controller in the at least two protocol controllers and is determined based on the mapping parameters. The target protocol controller is used for communicating with the serializer. The mapping relationship between the serializer and the target protocol controller is determined through the mapping circuit, the mapping between the serializer and the target protocol controller can be realized, that is, based on different mapping parameters, the mapping between the serializer and the multiple protocol controllers can be switched through the mapping circuit, and the chip cost is reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a switching chip and a control method thereof. Background Technology

[0002] Currently, switching chips can be implemented with different functions through software definition for application in different scenarios. Different functions require different communication protocols, such as the packet-switched interconnect protocol RapidIO, Ethernet protocol, and so on.

[0003] In related technologies, the mapping and communication between serializers and single-protocol controllers are generally achieved through a single-protocol switching chip. However, when multiple different functions need to be implemented, i.e., multiple communication protocols are required, multiple switching chips are needed, which increases the chip cost. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a switching chip and a control method to reduce chip costs.

[0005] The embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a switching chip, the chip comprising: a serializer, a mapping circuit, and a protocol controller group; wherein, a first terminal and a second terminal of the mapping circuit are respectively connected to the mapping circuit and the protocol controller group; the protocol controller group comprises at least two protocol controllers;

[0007] The serializer is used to send the mapping parameters to the mapping circuit;

[0008] The mapping circuit is used to determine the mapping relationship between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is one of the at least two protocol controllers; the target protocol controller is determined based on the mapping parameters.

[0009] The target protocol controller is used to communicate with the serializer based on the mapping relationship.

[0010] Optionally, the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit; wherein, the first terminal and the second terminal of the first-level mapping circuit are respectively connected to the serializer and the second-level mapping circuit; the first terminal and the second terminal of the second-level mapping circuit are respectively connected to the first-level mapping circuit and the protocol controller group; the mapping parameters include protocol configuration parameters and channel mode parameters;

[0011] The first-level mapping circuit is used to receive the mapping parameters and to determine the target protocol controller from the protocol controller group according to the protocol configuration parameters in the mapping parameters.

[0012] The secondary mapping circuit is used to determine the mapping relationship between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters.

[0013] Optionally, the first-level mapping circuit is specifically used to parse the protocol configuration parameters in the mapping parameters to obtain a first-level parsing result; and to determine the target protocol controller based on the first-level parsing result.

[0014] Optionally, the secondary mapping circuit is specifically used to parse the channel mode parameters in the mapping parameters to obtain a secondary parsing result; and to determine the mapping relationship between the data transmission channel of the serializer and the port of the target protocol controller based on the secondary parsing result.

[0015] Optionally, when the protocol controller group includes a Fibre Channel FC protocol controller, and the mapping parameters indicate parameters of the FC protocol controller; the mapping circuit includes a first-level mapping circuit;

[0016] The first-level mapping circuit is used to parse the mapping parameters to obtain the first-level parsing result; and to determine the interface of the FC protocol controller based on the first-level parsing result.

[0017] Optionally, when the protocol controller group includes a high-speed serial computer expansion bus standard PCIe protocol controller, and the mapping parameters indicate parameters of the PCIe protocol controller; the mapping parameters include protocol configuration parameters and channel mode parameters; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit;

[0018] The first-level mapping circuit is used to receive the mapping parameters, parse the protocol configuration parameters in the mapping parameters to obtain the first-level parsing result, and determine the PCIE interface based on the first-level parsing result; the PCIE interface is the interface of the PCIE controller.

[0019] The secondary mapping circuit is used to parse the channel configuration parameters in the mapping parameters to obtain the secondary mapping result; and to determine the mapping relationship between the PCIe interface and the port of the PCIe controller based on the secondary mapping result.

[0020] Secondly, embodiments of this application provide a switching chip, the chip comprising: n serializers, n mapping circuits, n protocol controller groups, and n-1 high-speed serial computer expansion bus standard PCIe protocol controllers; wherein n is an integer greater than or equal to 2; and the protocol controller group includes at least one protocol controller;

[0021] Among them, the n serializers correspond to the n mapping circuits; each of the n serializers is connected to a corresponding mapping circuit; the n mapping circuits correspond to the n protocol controller groups; each of the n mapping circuits is connected to a corresponding protocol controller group; and the n-1 PCIe protocol controllers are connected to two adjacent mapping circuits.

[0022] The serializer is used to send the mapping parameters to the mapping circuit;

[0023] The mapping circuit is used to determine the mapping relationship between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is a protocol controller among the at least two protocol controllers or the PCIe protocol controller; the target protocol controller is determined based on the mapping parameters.

[0024] The target protocol controller is used to communicate with the serializer based on the mapping relationship.

[0025] Thirdly, embodiments of this application provide a control method for a switching chip, the switching chip including a serializer, a mapping circuit, and a protocol controller group; wherein, a first terminal and a second terminal of the mapping circuit are respectively connected to the mapping circuit and the protocol controller group; the protocol controller group includes at least two protocol controllers;

[0026] The control method includes:

[0027] Receive mapping parameters; the mapping parameters are obtained through the serializer;

[0028] The mapping relationship between the serializer and the target protocol controller is determined based on the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers.

[0029] Fourthly, embodiments of this application provide a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, it implements the control method for the switching chip as described in the third aspect.

[0030] Fifthly, embodiments of this application provide a computer-readable storage medium storing instructions that, when executed on a terminal device, cause the terminal device to perform the control method for the switching chip as described in the third aspect.

[0031] Compared with the prior art, this application has the following beneficial effects:

[0032] The switching chip provided in this application includes a serializer, a mapping circuit, and a protocol controller group. The protocol controller group includes at least two protocol controllers. The serializer sends mapping parameters to the mapping circuit. The mapping circuit determines the mapping relationship between the serializer and a target protocol controller based on the mapping parameters. The target protocol controller is one of the at least two protocol controllers, determined based on the mapping parameters. The target protocol controller communicates with the serializer. By determining the mapping relationship between the serializer and the target protocol controller through the mapping circuit, mapping from the serializer to the target protocol controller can be achieved. That is, based on different mapping parameters, the mapping circuit can achieve switching between the serializer and multiple protocol controllers, reducing chip cost. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of the structure of a switching chip provided in an embodiment of this application;

[0035] Figure 2 A schematic diagram of another switching chip provided in an embodiment of this application;

[0036] Figure 3 A schematic diagram of a switching chip provided in an embodiment of this application;

[0037] Figure 4 A schematic diagram illustrating a mapping relationship based on the Ethernet protocol, provided for an embodiment of this application;

[0038] Figure 5 A schematic diagram illustrating a mapping relationship based on the SRIO protocol provided in an embodiment of this application;

[0039] Figure 6 A schematic diagram illustrating a mapping relationship based on the PCIE protocol, provided for an embodiment of this application;

[0040] Figure 7 A flowchart illustrating the control method for the switching chip provided in this application embodiment. Detailed Implementation

[0041] As described earlier, research on switching chips has revealed that they can currently be implemented with different functions through software definition for various applications. These different functions utilize different communication protocols, such as the packet-switched interconnect protocol RapidIO, Ethernet, and so on.

[0042] In related technologies, the mapping and communication between serializers and single-protocol controllers are generally achieved through a single-protocol switching chip. However, when multiple different functions need to be implemented, i.e., multiple communication protocols are required, multiple switching chips are needed, which increases the chip cost.

[0043] To address the aforementioned problems, this application provides a switching chip and a control method. The switching chip includes a serializer, a mapping circuit, and a protocol controller group; wherein the protocol controller group includes at least two protocol controllers; the serializer is used to send mapping parameters to the mapping circuit; the mapping circuit is used to determine the mapping relationship between the serializer and a target protocol controller based on the mapping parameters, the target protocol controller being one of the at least two protocol controllers, and the target protocol controller is determined based on the mapping parameters; the target protocol controller is used to communicate with the serializer.

[0044] Thus, by determining the mapping relationship between the serializer and the target protocol controller through the mapping circuit, the mapping between the serializer and the target protocol controller can be realized. That is, based on different mapping parameters, the switching between the serializer and multiple protocol controllers can be realized through the mapping circuit, reducing chip cost.

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0046] See Figure 1 The figure is a schematic diagram of the structure of a switching chip provided in an embodiment of this application.

[0047] Combination Figure 1 As shown, the switching chip 100 provided in this embodiment may include:

[0048] The system includes a serializer 101, a mapping circuit 102, and a protocol controller group 103; wherein, the first and second terminals of the mapping circuit 102 are respectively connected to the mapping circuit 102 and the protocol controller group 103; the protocol controller group 103 includes at least two protocol controllers.

[0049] A protocol controller group refers to a collection of at least two protocol controllers. A protocol controller group may include at least two of the following: Fibre Channel FC protocol controller, PCIe protocol controller, Ethernet protocol controller, and SRIO serial communication protocol controller, including but not limited to the aforementioned four protocols, without specific limitations.

[0050] FC (Fibre Channel) protocol is a suite of standard Fibre Channel protocols. FC protocol networks feature high bandwidth, low latency, low fault rate, and flexible topology.

[0051] PCI-Express (Peripheral Component Interconnect Express), or PCIE for short, is a high-speed serial computer expansion bus standard, primarily used to expand the data throughput of computer system buses and improve device communication speed.

[0052] Ethernet protocol is used to implement data transmission and address encapsulation (MAC) at the link layer.

[0053] SRIO (Serial RapidIO) is a protocol for high-speed serial communication designed to connect chips such as digital signal processors (DSPs), network processors, and FPGAs, as well as the interconnects between them. SRIO features low latency, high bandwidth (supporting data transfer rates from 1.25Gbps to 25Gbps), and high reliability.

[0054] The serializer 101 is used to send the mapping parameters to the mapping circuit 102.

[0055] A serializer (serDes) is a physical device that converts parallel data into serial data for transmission and converts received serial data into parallel data.

[0056] Mapping parameters refer to parameters of the protocol controller that communicates with the serializer. As one possible implementation, mapping parameters can be obtained based on the data to be transmitted, and no specific limitation is made here.

[0057] The mapping circuit 102 is used to determine the mapping relationship between the serializer 101 and the target protocol controller based on the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers; the target protocol controller is determined based on the mapping parameters.

[0058] A mapping circuit refers to a circuit used to determine the target protocol controller that communicates with the serializer and to determine the mapping relationship between the serializer and the target protocol controller. The mapping relationship refers to the relationship between the serializer's data channels and the ports of the target protocol controller. As an example, assuming the serializer's data channels are a1 to a8 and the target protocol controller's ports are b1 and b2, then the mapping relationship between the serializer's data channels and the target protocol controller's ports is a1 to a4 corresponding to b1, and a5 to a8 corresponding to b2.

[0059] It should be understood that the mapping parameters include parameters related to the target protocol controller. The mapping circuit uses these mapping parameters to determine the target protocol controller from at least two protocol controllers in the protocol controller group, and uses the mapping parameters to determine the mapping relationship between the serializer and the target protocol controller, which facilitates subsequent communication.

[0060] The target protocol controller is used to communicate with the serializer 101 based on the mapping relationship.

[0061] It should be understood that once the mapping circuit determines the target protocol controller and the mapping relationship between the serializer and the target protocol controller, the target protocol controller can perform operations such as communication and data interaction with the serializer 101 based on the mapping relationship.

[0062] In this embodiment, the mapping relationship between the serializer and the target protocol controller is determined by the mapping circuit, which can realize the mapping between the serializer and the target protocol controller. That is, based on different mapping parameters, the mapping circuit can realize the switching between the serializer and multiple protocol controllers, reducing chip cost.

[0063] Based on the switching chip provided in the above embodiments, in order to further explain the mapping circuit 102, in some possible implementations, the mapping circuit 102 may include: a first-level mapping circuit and a second-level mapping circuit.

[0064] The first and second terminals of the primary mapping circuit are respectively connected to the serializer 101 and the secondary mapping circuit; the first and second terminals of the secondary mapping circuit are respectively connected to the primary mapping circuit and the protocol controller group 103; the mapping parameters include protocol configuration parameters and channel mode parameters.

[0065] Protocol configuration parameters refer to the protocol-related configuration parameters of the protocol controller that communicates with the serializer; channel mode parameters refer to the mode between the serializer's data channel and the corresponding protocol controller port.

[0066] It should be understood that in the embodiments of this application, it is necessary to determine the target controller and the mapping relationship between the serializer and the target controller. Therefore, it can be divided into two mappings. The first mapping can determine the target controller from multiple protocol controllers. That is, the target protocol controller is determined from the protocol controller group 103 according to the protocol configuration parameters through the first-level mapping circuit. The second mapping determines the mapping relationship between the serializer and the protocol controller. That is, the mapping relationship between the serializer 101 and the target protocol controller is determined according to the channel mode parameters through the second-level mapping circuit.

[0067] In some possible implementations, the first-level mapping circuit is specifically used to parse the protocol configuration parameters in the mapping parameters to obtain a first-level parsing result; and to determine the target protocol controller based on the first-level parsing result.

[0068] It should be understood that the target protocol controller is determined based on the first-level parsing result, and the target interface of the target protocol controller can also be determined so that the serializer can establish a connection with the target interface of the target protocol controller.

[0069] Here, "interface" refers to the connection component between the protocol controller and the serializer, serving as a relay station for information exchange between the protocol controller's CPU and the outside world; "port" refers to the register in the interface, used for data exchange with other software.

[0070] It should be noted that the protocol configuration parameters include protocol-related parameters of the protocol controller to which the serializer is to communicate. Therefore, by parsing the protocol configuration parameters, a first-level mapping result can be obtained, and the path switching between the serializer and the protocol controller in the protocol controller group can be configured based on this mapping relationship to determine the target protocol controller.

[0071] As an example, suppose the protocol controller group includes three protocol controllers A, B, and C. It can be pre-set that the serializer has not established a path with protocol controllers A, B, and C. The first-level mapping result can include a=0, b=1, and c=0. Then the first-level mapping result can indicate that the serializer has established a path with protocol controller B. Based on the first-level mapping result, protocol controller B is determined as the target protocol controller.

[0072] In some possible implementations, the secondary mapping circuit is specifically used to parse the channel mode parameters in the mapping parameters to obtain a secondary parsing result; and to determine the mapping relationship between the data transmission channel of the serializer 101 and the port of the target protocol controller based on the secondary parsing result.

[0073] It should be understood that the channel mode parameter includes the channel mode corresponding to the target protocol controller. Since the serializer may include multiple data transmission channels and the protocol controller also includes multiple ports, in order to ensure normal communication between the serializer 101 and the target protocol controller, it is necessary to determine the mapping relationship between the data channels of the serializer 101 and the ports of the target protocol controller. That is, the channel mode corresponding to the target controller is determined through the channel mode parameter, and the mapping relationship between the multiple data channels of the serializer and the ports of the target protocol controller is determined based on the channel mode.

[0074] Based on the switching chip provided in the above embodiments, since different protocol controllers have different functions or configurations, in one possible implementation, when the protocol controller group 103 includes a Fibre Channel FC protocol controller, and the mapping parameters indicate the parameters of the FC protocol controller; the mapping circuit includes a first-level mapping circuit.

[0075] The first-level mapping circuit is used to parse the mapping parameters to obtain the first-level parsing result; and to determine the interface of the FC protocol controller based on the first-level parsing result.

[0076] It should be noted that since there is no mapping relationship between the serializer and the port of the protocol controller, it is only necessary to determine that the target protocol controller is the FC protocol controller through a first-level mapping circuit, so that the serializer and the FC protocol controller can be connected and communicated.

[0077] Based on the switching chip provided in the above embodiments, in one possible implementation, when the protocol controller group 103 includes a high-speed serial computer expansion bus standard PCIe protocol controller, and the mapping parameters indicate parameters of the PCIe protocol controller; the mapping parameters include protocol configuration parameters and channel mode parameters; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit;

[0078] The first-level mapping circuit is used to receive the mapping parameters, parse the protocol configuration parameters in the mapping parameters to obtain the first-level parsing result, and determine the PCIE interface based on the first-level parsing result; the PCIE interface is the interface of the PCIE controller.

[0079] The secondary mapping circuit is used to parse the channel configuration parameters in the mapping parameters to obtain the secondary mapping result; and to determine the mapping relationship between the PCIe interface and the port of the PCIe controller based on the secondary mapping result.

[0080] It should be noted that there is a one-to-one correspondence between the serializer's data channels and the PCIe protocol controller's interface. Therefore, the PCIe interface of the PCIe protocol controller can be determined through a first-level mapping circuit. However, there is not a one-to-one correspondence between the PCIe interface and the PCIe protocol controller's port. Therefore, a second-level mapping circuit is needed to determine the mapping relationship between the PCIe interface and the PCIe protocol controller's port in order to enable communication between the serializer and the PCIe protocol controller.

[0081] See Figure 2 This figure is a schematic diagram of another switching chip provided in an embodiment of this application.

[0082] Since the PCIe protocol controller supports the bonding of 16 data channels, when designing a switch chip, two serializers can be bonded to one PCIe protocol controller. That is, two adjacent serializers share one PCIe protocol controller, but the communication between the two serializers and the PCIe protocol controller does not affect each other.

[0083] Combination Figure 2 As shown, the switching chip 200 provided in this application embodiment may include: n serializers 101, n mapping circuits 102, n protocol controller groups 201, and n-1 high-speed serial computer expansion bus standard PCIe protocol controllers 202; where n is an integer greater than or equal to 2; the protocol controller group 103 includes at least one protocol controller;

[0084] Specifically, the n serializers 101 correspond to the n mapping circuits 102; each of the n serializers 101 is connected to a corresponding mapping circuit 102; the n mapping circuits 102 correspond to the n protocol controller groups 201; each of the n mapping circuits 102 is connected to a corresponding protocol controller group 201; and the n-1 PCIe protocol controllers 202 are connected to two adjacent mapping circuits 102.

[0085] It should be noted that the same modules or devices in the switching chip 200 provided in this application embodiment are the same as those in the switching chip 100 provided in the above embodiment, and the reference numerals in the drawing of the switching chip 100 provided in the above embodiment are used.

[0086] It should be noted that the protocol controller group 201 provided in this application embodiment may be the same as or different from the protocol controller group 103 provided in the above embodiment, and therefore different reference numerals are used. As an example, assuming that the protocol controllers included in the protocol controller group 201 are the same as those included in the protocol controller group 103, then the protocol controller group 201 and the protocol controller group 103 are the same; otherwise, they are different.

[0087] The serializer 101 is used to send the mapping parameters to the mapping circuit 102.

[0088] The mapping circuit 102 is used to determine the mapping relationship between the serializer 101 and the target protocol controller based on the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers or the PCIE protocol controller 202; the target protocol controller is determined based on the mapping parameters.

[0089] The target protocol controller is used to communicate with the serializer based on the mapping relationship.

[0090] In the embodiments of this application, in the design of the switching chip, by sharing a PCIe protocol controller between two adjacent serializers, the chip cost can be reduced and the utilization rate of the PCIe protocol controller can be improved.

[0091] See Figure 3 The figure is a schematic diagram of a switching chip provided in an embodiment of this application.

[0092] Combination Figure 3 As shown, the switching chip provided in this application embodiment may include 6 groups, each group corresponding to one serializer, wherein each serializer may include 8 data channels, namely lane0 to lane7; one primary mapping circuit; one MPPG (multi-protocol port group), wherein the MPPG includes an Ethernet protocol controller and a corresponding secondary Ethernet mapping circuit, an FC protocol controller, an SRIO protocol controller and a corresponding secondary SRIO mapping circuit; every two groups correspond to two serializers and one PPG (PCIE port group), wherein the PPG includes a PCIE interface, a secondary PCIE mapping circuit and a PCIE controller.

[0093] It should be noted that the appendices in the embodiments of this application... Figure 3 Only the connections between any two adjacent groups out of the six groups are shown; the connections between other groups and their appendices are not displayed. Figure 3 The structures and connections shown are the same or similar, and will not be repeated here.

[0094] It should be noted that the mapping parameters include protocol configuration parameters and channel mode parameters. Protocol configuration parameters can be represented by BCFG[1:0], and channel mode parameters can be represented by path_mode[3:0].

[0095] Combination Figure 3 As shown, the first-level mapping circuit is located in the first level of the mapping circuit. It mainly realizes the clock reset, data and control signal and status signal path switching between the serializer and the four protocol controllers according to the protocol configuration parameters. The switching is based on BCFG[1:0].

[0096] In some possible implementations, the processing of the protocol configuration parameter BCFG[1:0] by the first-level mapping circuit may include the following four cases:

[0097] In the first case, in the serializer's transmit direction, when BCFG[1:0]==00, the clock reset, data, control signal, and status signal output by the serializer are connected to the interface of the Ethernet protocol controller; otherwise, the clock is gated, and the clock reset, data, control signal, and status signal are connected to 0.

[0098] Clock gating is a technique used in digital IC design to turn off the clock when certain parts of the design are not needed.

[0099] In the second case, in the serializer transmission direction, when BCFG[1:0]==01, the clock reset, data, control signal and status signal output by the serializer are connected to the interface of the SRIO protocol controller; otherwise, the clock is gated and the clock reset, data, control signal and status signal are connected to 0.

[0100] In the third case, in the serializer transmission direction, when BCFG[1:0]==10, the clock reset, data, control signal and status signal output by the serializer are connected to the interface of the FC protocol controller; otherwise, the clock is gated and the clock reset, data, control signal and status signal are connected to 0.

[0101] In the first case, in the serializer transmit direction, when BCFG[1:0]==11, the clock reset, data, control signal and status signal output by the serializer are connected to the interface of the PCIE protocol controller; otherwise, the clock is gated and the clock reset, data, control signal and status signal are connected to 0.

[0102] It should be understood that when the clock reset, data, control signals, and status signals are connected to the interface of the target protocol controller according to the protocol configuration parameters, clock gating is performed on other protocol controllers, and the clock reset, data, control signals, and status signals are connected to 0, so as to realize the switching and selection of the target protocol controller.

[0103] It should be noted that, in the serializer transmission direction, when the clock signal switches, the data selection unit in the first-level mapping circuit needs to be replaced with a gating unit for control.

[0104] In some possible implementations, the mapping relationship between the serializer's data channel and the target protocol controller's port can include the following:

[0105] It should be noted that the secondary Ethernet mapping circuit is located in the second level of the mapping circuit. It mainly switches the paths for clock reset, data, control, and status signals between the Ethernet interface of the primary mapping circuit and the port of the Ethernet protocol controller based on the configuration of the channel mode parameters. The switching is based on path_mode[3:0]. See [link to relevant documentation]. Figure 4 This figure is a schematic diagram of a mapping relationship based on the Ethernet protocol provided in an embodiment of this application.

[0106] Combination Figure 4 As shown, the serializer can have 8 data channels, namely Lane 0 to Lane 7; the Ethernet protocol controller can have 9 ports; there are a total of twelve mapping relationships based on the Ethernet protocol. When path_mode[3:0] has different values, it represents a different mapping relationship between the serializer's data channels and the Ethernet protocol controller's ports. As an example, assuming path_mode[3:0] = 0000, then the serializer's data channels Lane 0 to Lane 4 correspond to the Ethernet protocol controller's port 2000GAUI-4PCS, and the serializer's data channels Lane 5 to Lane 7 correspond to the Ethernet protocol controller's port 1000GAUI-4PCS.

[0107] The second-level SRIO mapping circuit is located in the second stage of the mapping circuit. It is used to switch the paths for clock reset, data, control, and status signals between the SRIO interface of the first-level mapping circuit and the port of the SRIO protocol controller according to the configuration of the channel mode parameters. The switching is based on path_mode[3:0]. See [link to relevant documentation]. Figure 5 This figure is a schematic diagram of a mapping relationship based on the SRIO protocol provided in an embodiment of this application.

[0108] Combination Figure 5As shown, the serializer's data channels can include eight, namely Lane 0 to Lane 7; the SRIO protocol controller's ports include two sets of SRIO_ and SRIO_1, each set including two ports; the mapping relationship based on the SRIO protocol can include four types. When path_mode[3:0] has different values, it represents a different mapping relationship between the serializer's data channels and the SRIO protocol controller's ports. As an example, assuming path_mode[3:0] = 0011, then the serializer's data channels Lane 0 and Lane 1 correspond to the SRIO protocol controller's port 0; the serializer's data channels Lane 2 and Lane 3 correspond to the SRIO protocol controller's port 12; the serializer's data channels Lane 4 and Lane 5 correspond to the SRIO protocol controller's port 6; and the serializer's data channels Lane 6 and Lane 7 correspond to the SRIO protocol controller's port 18.

[0109] The secondary PCIe mapping circuit, located at the second level of the mapping circuit, is used to switch the data and control signal paths between the PCIe interface and the PCIe protocol controller ports. The signals involved in the switching, besides receiving and transmitting data, are mostly control or status signals, and there is no timing handshake relationship between the control flow and the data flow. The secondary PCIe mapping circuit is located between the PCIe interface and the PCIe protocol controller ports, and mainly implements the switching of clock reset, data, control, and status signal paths between the PIPE interface and the PCIe protocol controller ports based on the channel mode parameter configuration. The switching is based on path_mode[3:0]. See also... Figure 6 This figure is a schematic diagram of a mapping relationship based on the PCIE protocol provided in an embodiment of this application.

[0110] Combination Figure 6 As shown, the PCIe interface can have 16 data channels, which can be divided into two groups. Each group includes data channels Lane0 to Lane7, and each group corresponds to two adjacent serializers. The PCIe protocol controller ports can also be divided into two groups, each containing four ports, and each group corresponds to two serializers. The mapping relationship based on the PCIe protocol can include six types. As an example, assuming path_mode[3:0] = 0000, then the data channels Lane0 to Lane7 corresponding to each of the two serializers are all associated with port X16 PCIe Controller.

[0111] Based on the switching chip provided in the above embodiments, see [link / reference]. Figure 7 This figure is a flowchart of a control method for a switching chip provided in an embodiment of this application. (In conjunction with...) Figure 7As shown, the switching chip provided in this application embodiment may include a serializer, a mapping circuit, and a protocol controller group; wherein, the first terminal and the second terminal of the mapping circuit are respectively connected to the mapping circuit and the protocol controller group; the protocol controller group includes at least two protocol controllers.

[0112] The control method may include:

[0113] S701: Receive mapping parameters; the mapping parameters are obtained through the serializer.

[0114] S702: Determine the mapping relationship between the serializer and the target protocol controller based on the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers.

[0115] As an example, the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit; wherein, the first terminal and the second terminal of the first-level mapping circuit are respectively connected to the serializer and the second-level mapping circuit; the first terminal and the second terminal of the second-level mapping circuit are respectively connected to the first-level mapping circuit and the protocol controller group; the mapping parameters include protocol configuration parameters and channel mode parameters;

[0116] Step S702 includes:

[0117] A1: Determine the target protocol controller from the protocol controller group based on the protocol configuration parameters in the mapping parameters.

[0118] A2: Determine the mapping relationship between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters.

[0119] As an example, A1 specifically includes:

[0120] The protocol configuration parameters in the mapping parameters are parsed to obtain the first-level parsing result;

[0121] The target protocol controller is determined based on the first-level parsing results.

[0122] As an example, A2 specifically includes:

[0123] The channel mode parameters in the mapping parameters are parsed to obtain the secondary parsing result;

[0124] Based on the secondary parsing results, the mapping relationship between the data transmission channel of the serializer and the port of the target protocol controller is determined.

[0125] As an example, when the protocol controller group includes a Fibre Channel FC protocol controller, and the mapping parameters indicate parameters of the FC protocol controller; the mapping circuit includes a first-level mapping circuit;

[0126] Step S702 includes:

[0127] The mapping parameters are parsed to obtain a first-level parsing result, which is then used to determine the interface of the FC protocol controller based on the first-level parsing result.

[0128] As an example, when the protocol controller group includes a high-speed serial computer expansion bus standard PCIe protocol controller, and the mapping parameters indicate parameters of the PCIe protocol controller; the mapping parameters include protocol configuration parameters and channel mode parameters; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit;

[0129] Step S702 includes:

[0130] The protocol configuration parameters in the mapping parameters are parsed to obtain the first-level parsing result;

[0131] The PCIe interface is determined based on the first-level parsing result; the PCIe interface is the interface of the PCIe controller;

[0132] The channel configuration parameters in the mapping parameters are parsed to obtain the secondary mapping result;

[0133] The mapping relationship between the PCIe interface and the port of the PCIe controller is determined based on the secondary mapping result.

[0134] The control method for the switching chip provided in this application has the same beneficial effects as the switching chip provided in the above embodiments, and therefore will not be described again.

[0135] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.

[0136] The device includes a memory and a processor. The memory stores instructions or code, and the processor executes the instructions or code to enable the device to perform the control method for the switching chip described in any embodiment of this application.

[0137] The computer storage medium stores code, and when the code is executed, the device running the code implements the control method of the switching chip described in any embodiment of this application.

[0138] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the embodiments can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0139] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0140] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0141] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A switching chip, characterized in that, The chip includes: a serializer, a mapping circuit, and a protocol controller group; wherein, a first terminal and a second terminal of the mapping circuit are respectively connected to the serializer and the protocol controller group; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit; a first terminal and a second terminal of the first-level mapping circuit are respectively connected to the serializer and the second-level mapping circuit; and a first terminal and a second terminal of the second-level mapping circuit are respectively connected to the first-level mapping circuit and the protocol controller group; the protocol controller group includes at least two protocol controllers. The serializer is used to send mapping parameters to the first-level mapping circuit; the mapping parameters include protocol configuration parameters and channel mode parameters, the channel mode parameters representing the mode between the serializer's data channel and the corresponding protocol controller port; The first-level mapping circuit is used to receive the mapping parameters and determine the target protocol controller from the protocol controller group according to the protocol configuration parameters in the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers; The secondary mapping circuit is used to determine the mapping relationship between the serializer and the target protocol controller based on the channel mode parameter in the mapping parameters; The target protocol controller is used to communicate with the serializer based on the mapping relationship.

2. The switching chip according to claim 1, characterized in that, The first-level mapping circuit is specifically used to parse the protocol configuration parameters in the mapping parameters to obtain the first-level parsing result; and to determine the target protocol controller based on the first-level parsing result.

3. The switching chip according to claim 1, characterized in that, The secondary mapping circuit is specifically used to parse the channel mode parameters in the mapping parameters to obtain secondary parsing results; and to determine the mapping relationship between the data transmission channel of the serializer and the port of the target protocol controller based on the secondary parsing results.

4. The switching chip according to claim 1, characterized in that, When the protocol controller group includes a Fibre Channel FC protocol controller, and the mapping parameters indicate parameters of the FC protocol controller; the mapping circuit includes a first-level mapping circuit; The first-level mapping circuit is used to parse the mapping parameters to obtain the first-level parsing result; And it is used to determine the interface of the FC protocol controller based on the first-level parsing result.

5. The switching chip according to claim 1, characterized in that, When the protocol controller group includes a high-speed serial computer expansion bus standard PCIe protocol controller, and the mapping parameters indicate parameters of the PCIe protocol controller; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit; The first-level mapping circuit is used to receive the mapping parameters and parse the protocol configuration parameters in the mapping parameters to obtain the first-level parsing result; And used to determine the PCIe interface based on the first-level parsing result; The PCIe interface is the interface of the PCIe controller; The secondary mapping circuit is used to parse the channel configuration parameters in the mapping parameters to obtain the secondary mapping result; It is used to determine the mapping relationship between the PCIe interface and the port of the PCIe controller based on the secondary mapping result.

6. A switching chip, characterized in that, The chip includes: n serializers, n mapping circuits, n protocol controller groups, and n-1 high-speed serial computer expansion bus standard PCIe protocol controllers; where n is an integer greater than or equal to 2; the protocol controller group includes at least one protocol controller; Specifically, the n serializers correspond to the n mapping circuits; each of the n serializers is connected to a corresponding mapping circuit; the n mapping circuits correspond to the n protocol controller groups; each of the n mapping circuits is connected to a corresponding protocol controller group; the n-1 PCIe protocol controllers are connected to two adjacent mapping circuits; each of the n mapping circuits includes a first-level mapping circuit and a second-level mapping circuit. The serializer is used to send mapping parameters to the corresponding first-level mapping circuit; the mapping parameters include protocol configuration parameters and channel mode parameters, and the channel mode parameters characterize the mode between the data channel of the serializer and the port of the corresponding protocol controller. The first-level mapping circuit is used to receive the mapping parameters sent by the corresponding serializer; and to determine the target protocol controller from the protocol controller group according to the protocol configuration parameters in the mapping parameters; the target protocol controller is the protocol controller among the at least two protocol controllers or the PCIE protocol controller; The secondary mapping circuit is used to determine the mapping relationship between the corresponding serializer and the target protocol controller based on the channel mode parameter in the mapping parameters; The target protocol controller is used to communicate with the corresponding serializer based on the mapping relationship.

7. A control method for a switching chip, characterized in that, The switching chip includes a serializer, a mapping circuit, and a protocol controller group; wherein, a first terminal and a second terminal of the mapping circuit are respectively connected to the serializer and the protocol controller group; the mapping circuit includes a first-level mapping circuit and a second-level mapping circuit; a first terminal and a second terminal of the first-level mapping circuit are respectively connected to the serializer and the second-level mapping circuit; and a first terminal and a second terminal of the second-level mapping circuit are respectively connected to the first-level mapping circuit and the protocol controller group; the protocol controller group includes at least two protocol controllers. The control method includes: Receive mapping parameters; the mapping parameters are obtained through the serializer, and the mapping parameters include protocol configuration parameters and channel mode parameters, wherein the channel mode parameters characterize the mode between the data channel of the serializer and the port of the corresponding protocol controller; The target protocol controller is determined from the protocol controller group based on the protocol configuration parameters in the mapping parameters; the target protocol controller is one of the at least two protocol controllers. The mapping relationship between the serializer and the target protocol controller is determined based on the channel mode parameter in the mapping parameters; Based on the mapping relationship, the target protocol controller communicates with the serializer.

8. A computer device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the control method for the switching chip as described in claim 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a terminal device, cause the terminal device to perform the control method for the switching chip as described in claim 7.

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