Circuit board plating method and circuit board

Abstract

The application discloses a circuit board electroplating method and a circuit board. The circuit board comprises a surface metal layer and at least one internal circuit layer, and an insulating layer is arranged between adjacent internal circuit layers. An insulating layer is arranged between the surface metal layer and the internal circuit layer. A hole dense area is formed on the surface of the circuit board. The hole dense area comprises at least one hole. The method comprises the following steps: removing part of layers of a target edge of the circuit board to expose a target internal circuit layer; placing the circuit board in an electroplating solution; applying an electroplating current to the exposed target internal circuit layer at the target edge; electroplating; forming a metal layer with uniform thickness on the surface metal layer; and forming a metal layer connecting the surface metal layer and the target internal circuit layer on the inner wall of the hole. During the electroplating process, the current on the surface metal layer flows outward from the hole, the current density of the hole dense area is increased, the quality of the circuit board is improved, and the scrap rate is reduced.

Description

Technical Field

[0001] This invention relates to electroplating technology, and more particularly to an electroplating method for circuit boards and a circuit board. Background Technology

[0002] In the process of manufacturing multilayer circuit boards, it is usually necessary to drill holes in the circuit board and electroplate a metal layer on the inner wall of the holes so that the circuits of the internal circuit layer are electrically connected to the metal layer on the surface of the circuit board. Then, the metal layer on the surface of the circuit board is processed to form a surface circuit layer, thus realizing the electrical connection between the internal circuit layer and the surface circuit layer.

[0003] During electroplating, the entire circuit board needs to be immersed in the plating solution. While a metal layer forms on the inner walls of the holes, a metal layer also forms on the surface of the circuit board. In the densely populated hole areas on the circuit board surface, due to the higher specific surface area compared to other areas, the current density is lower. This results in a thinner metal layer in these areas and a thicker metal layer in other areas, leading to poor plating uniformity. A large difference between these two areas severely affects subsequent processing, and in severe cases, may even prevent the etching of surface circuitry, rendering the circuit board unusable. Summary of the Invention

[0004] This invention provides a circuit board electroplating method and circuit board, which can increase the current density in the densely packed hole area, thereby offsetting the effect of the reduced current density caused by the high specific surface area of ​​the densely packed hole area. In this way, the metal layer formed on the surface metal layer has a uniform thickness, which improves the quality of the circuit board and reduces the scrap rate.

[0005] In a first aspect, the present invention provides a circuit board electroplating method, the circuit board comprising a surface metal layer and at least one internal circuit layer, an insulating layer being disposed between adjacent internal circuit layers, an insulating layer being disposed between the surface metal layer and the internal circuit layer, and a densely packed area of ​​holes being formed on the surface of the circuit board, the densely packed area of ​​holes including at least one hole, the circuit board electroplating method comprising:

[0006] Remove a portion of the layer at the target edge of the circuit board to expose the internal circuit layer, wherein the target edge is one edge of the circuit board;

[0007] The circuit board is placed in an electroplating solution, and an electroplating current is applied to the exposed internal circuit layer at the edge of the target to perform electroplating, forming a metal layer of uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the internal circuit layer of the target on the inner wall of the hole.

[0008] Optionally, before removing a portion of the layer at the target edge of the circuit board to expose the target internal circuit layer, the process further includes:

[0009] The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole using a chemical deposition method.

[0010] Optionally, after removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layers, the method further includes:

[0011] A groove parallel to the target edge is formed on the surface metal layer, the bottom of the groove exposing the target insulating layer located below the surface metal layer, the groove dividing the surface metal layer into a first part close to the target edge and a second part away from the target edge, the width of the first part being smaller than the width of the second part;

[0012] The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole, the surface of the exposed target insulating layer, and the surface metal layer using a chemical deposition method.

[0013] Remove the first portion and the metal layer on the first portion to form an insulating barrier between the exposed internal circuitry layer of the target and the surface metal layer.

[0014] Optionally, a groove parallel to the target edge is formed on the surface metal layer, including:

[0015] A groove is formed on the surface metal layer using a slotting method, parallel to the edge of the target, with the bottom of the groove exposing the target insulating layer located beneath the surface metal layer.

[0016] Optionally, after removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layers, the method further includes:

[0017] Remove the surface metal layer near the edge of the target to expose the target insulating layer beneath the surface metal layer;

[0018] Apply insulating tape to the exposed target insulation layer;

[0019] The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole, the surface of the insulating tape, and the surface metal layer using a chemical deposition method.

[0020] Peel off the insulating tape to form an insulating barrier between the exposed internal wiring layer and the surface metal layer.

[0021] Optionally, removing a portion of the layers at the target edge of the circuit board to expose the target internal circuit layers includes:

[0022] A blind soldering method is used to remove part of the target edge layer of the circuit board to expose the internal circuit layer. The width of the blind soldering is 5mm-12mm and the length of the blind soldering is the length of the target edge.

[0023] Optionally, a surface metal layer is provided on one side of the circuit board, and an insulating layer is provided on the opposite side. Removing a portion of the layer at the target edge of the circuit board exposes the target internal circuit layer, including:

[0024] Remove a portion of the target edge layer on the side of the circuit board where the surface metal layer is located to expose the internal circuit layer.

[0025] Optionally, a surface metal layer is provided on both opposite sides of the circuit board, and a portion of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer, including:

[0026] Remove a portion of the target edge layer from one side of the target surface metal layer of the circuit board to expose the target internal circuit layer;

[0027] Remove the non-target surface metal layer from one side of the target edge of the non-target surface metal layer of the circuit board to expose the target insulating layer located beneath the non-target surface metal.

[0028] Optionally, the circuit board is placed in an electroplating solution, and an electroplating current is applied to the exposed internal circuit layer at the target edge to perform electroplating, including:

[0029] The target edge of the circuit board is held by electroplating clips, and a plurality of electroplating clips are evenly spaced along the target edge. The electroplating clips are electrically connected to the exposed internal circuit layer of the target at the target edge.

[0030] The circuit board is placed in an electroplating solution;

[0031] Electroplating is performed by applying an electroplating current to the exposed internal circuit layer at the edge of the target using the electroplating clamp.

[0032] Optionally, the metal layer is a copper layer.

[0033] Secondly, embodiments of the present invention also provide a circuit board prepared using the circuit board electroplating method provided in the first aspect of the present invention.

[0034] The present invention provides a circuit board electroplating method. The circuit board includes a surface metal layer and at least one internal circuit layer. An insulating layer is disposed between adjacent internal circuit layers and between the surface metal layer and the internal circuit layer. A densely packed hole region is formed on the surface of the circuit board, the densely packed hole region including at least one hole. A portion of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer. The target edge is one edge of the circuit board. The circuit board is placed in an electroplating solution, and an electroplating current is applied to the exposed target internal circuit layer at the target edge for electroplating. A metal layer of uniform thickness is formed on the surface metal layer, and a metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of the hole. During the electroplating process, the current on the surface metal layer is changed to flow diverging from the hole to the surrounding area, increasing the current density in the densely packed hole region, thereby offsetting the effect of the reduced current density due to the high specific surface area of ​​the densely packed hole region. In this way, the metal layer formed on the surface metal layer has a uniform thickness, improving the quality of the circuit board and reducing the scrap rate. Attached Figure Description

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a schematic diagram of a circuit board structure;

[0037] Figure 2 This is a schematic diagram of the current flow direction in an existing electroplating method.

[0038] Figure 3 This is a schematic flowchart of a circuit board electroplating method provided in an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a deposited metal layer provided by the present invention;

[0040] Figure 5 A front view of the circuit board with the target edge partially removed;

[0041] Figure 6 for Figure 5 A sectional view along section line AA;

[0042] Figure 7 This is a schematic diagram of electroplating on a circuit board according to an embodiment of the present invention;

[0043] Figure 8 This is a cross-sectional view of a circuit board after electroplating, along section line AA.

[0044] Figure 9 A schematic flowchart of another circuit board electroplating method provided in an embodiment of the present invention;

[0045] Figure 10A front view of a circuit board with a portion of the layer removed from the target edge;

[0046] Figure 11 for Figure 10 A sectional view along section line AA;

[0047] Figure 12 A front view of the circuit board after the surface metal layer of the target edge has been removed;

[0048] Figure 13 for Figure 12 A sectional view along section line AA;

[0049] Figure 14 This is a schematic diagram of the structure after a metal layer has been deposited.

[0050] Figure 15 A schematic diagram of the structure of the metal layer deposited on the surface to remove the exposed target insulation layer;

[0051] Figure 16 This is a schematic diagram of another electroplating process for a circuit board provided in an embodiment of the present invention;

[0052] Figure 17 This is a cross-sectional view of another circuit board after electroplating, along section line AA.

[0053] Figure 18 A schematic flowchart of another circuit board electroplating method provided in this embodiment of the invention;

[0054] Figure 19 A schematic diagram of the structure after removing the surface metal layer near the edge of the target;

[0055] Figure 20 A schematic diagram of a structure for attaching insulating tape to an exposed target insulation layer;

[0056] Figure 21 This is a schematic diagram of the structure after another metal layer has been deposited.

[0057] Figure 22 This is a schematic diagram of the structure after the insulating tape has been peeled off;

[0058] Figure 23 This is a cross-sectional view of another circuit board after electroplating, along section line AA. Detailed Implementation

[0059] To make the technical problems solved by the present invention, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0060] In the description of this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0061] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature. Moreover, the terms "first" and "second" are used merely for descriptive distinction and have no specific meaning.

[0062] Figure 1 This is a schematic diagram of a circuit board structure. Figure 2 This is a schematic diagram of the current flow direction in an existing electroplating method, such as... Figure 1 As shown, the circuit board includes a surface metal layer 10 and an internal circuit layer 20. An insulating layer 30 is disposed between the surface metal layer 10 and the internal circuit layer 20. The internal circuit layer 20 is formed on the insulating layer 30. The metal layer 10 is not etched to form circuits, while the internal circuit layer 20 is etched to form circuits. A dense via region 40 is formed on the surface of the circuit board. The dense via region 40 includes at least one via 41, which is used for electrical connection between the metal layer 10 and the internal circuit layer 20. Figure 1As shown, a very thin metal layer 50 is deposited on the hole 41. Because the metal layer 50 is very thin, its resistance is very high. To reduce the resistance of the metal layer 50 and improve the connection stability between the metal layer 10 and the internal circuit layer 20, electroplating is usually required on the circuit board to form a thicker metal layer on the metal layer 10 and the metal layer 50 on the inner wall of the hole 41. In the prior art, such as... Figure 2 As shown, the circuit board is typically placed vertically in an electroplating bath containing electroplating solution, and an electroplating current is applied to the metal layer 10 at the upper edge of the circuit board. Through an electrochemical reaction, a relatively thick metal layer is formed on the metal layer 10 and the metal layer 50 on the inner wall of the hole 41. Figure 2 As shown, during the electroplating process, the current flows from the upper edge to the lower edge of the circuit board. When it flows through the hole-dense area 40, the current density decreases due to the high specific surface area of ​​the hole-dense area 40. This results in the metal layer formed in the hole-dense area 40 of the metal layer 10 being thinner after electroplating, while the metal layer formed in other areas of the metal layer 10 is thicker. The electroplating uniformity deteriorates, and when the difference between the two is large, it seriously affects subsequent processing. In severe cases, it may even prevent the surface circuitry from being etched, leading to the scrapping of the circuit board.

[0063] To address the above problems, this invention provides a circuit board electroplating method. Figure 3 This is a schematic flowchart of a circuit board electroplating method provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the circuit board electroplating method includes the following steps:

[0064] S101. Immerse the circuit board in the deposition solution and deposit a metal layer on the inner wall of the hole using chemical deposition.

[0065] Figure 4 This is a flowchart illustrating the deposition of a metal layer on the inner wall of a hole using chemical deposition, as described in an embodiment of the present invention. Figure 4 As shown, before deposition, the circuit board includes a surface metal layer 110 and at least one internal circuit layer. This embodiment is illustrated by an example including two internal circuit layers 121 and 122. An insulating layer 131 is provided between adjacent internal circuit layers, and an insulating layer 132 is provided between the surface metal layer 110 and the adjacent internal circuit layer 121. A hole-dense region 140 is formed on the surface of the circuit board, and the hole-dense region 140 includes at least one hole 141.

[0066] For example, in some embodiments of the present invention, a very thin metal layer 151 is formed on the inner wall of the hole 141 by chemical deposition. The metal layer 151 connects the surface metal layer 110 and the internal circuit layer 121. For example, after the hole 141 is formed on the circuit board, the circuit board is immersed in a deposition solution, and the metal layer 151 is deposited on the inner wall of the hole 141 by chemical deposition. The metal layer 151 formed by chemical deposition is very thin, has high resistance, and the connection is unstable. At the same time, a very thin metal layer 153 is also formed on the surface of the surface metal layer 110.

[0067] S102. Remove part of the layer at the target edge of the circuit board to expose the internal circuit layer of the target.

[0068] Figure 5 A front view of a circuit board to show the partial layers at the target edge. Figure 6 for Figure 5 A sectional view along section line AA, as shown below. Figure 5 and Figure 6 As shown, in this embodiment of the invention, one edge of the circuit board is taken as the target edge, and the target edge is processed to remove part of the layer of the target edge of the circuit board, exposing the target internal circuit layer 121. In this embodiment of the invention, the internal circuit layer 121 connected to the surface metal layer 110 is referred to as the target internal circuit layer.

[0069] For example, in an embodiment of the present invention, a router is used to remove a portion of the layer at the target edge of the circuit board using a blind router method. Figure 6 The surface metal layer 110 and insulating layer 132 are exposed, revealing the internal circuit layer 121 of the target. For example, the width D of the blind gong ranges from 5mm to 12mm, and the length L of the blind gong is the length of the target edge.

[0070] In this embodiment, the circuit board has a surface metal layer 110 on only one side and an insulating layer 133 on the other side. Therefore, when removing part of the target edge layer of the circuit board, it is only necessary to remove part of the target edge layer on the side of the circuit board with the surface metal layer 110 to expose the target internal circuit layer 121. The other side does not need to be processed.

[0071] In this embodiment, surface metal layers are provided on both opposite sides of the circuit board. When removing a portion of the target edge layer of the circuit board, a portion of the target edge layer on one side of the target surface metal layer of the circuit board is removed to expose the target internal circuit layer. At the same time, the non-target surface metal layer on one side of the target edge of the non-target surface metal layer (i.e., the surface metal layer on the opposite side) of the circuit board is removed to expose the target insulating layer located below the non-target surface metal layer, which facilitates clamping with electroplating clamps during subsequent electroplating processes.

[0072] S103. Place the circuit board in the electroplating solution and apply electroplating current to the exposed internal circuit layer at the edge of the target to perform electroplating, forming a metal layer of uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the internal circuit layer of the target on the inner wall of the hole.

[0073] Figure 7 This is a schematic diagram of electroplating on a circuit board provided in an embodiment of the present invention, as shown below. Figure 7 As shown, in this embodiment of the invention, the circuit board is placed vertically in an electrolytic tank containing electrolyte, with the target edge facing upwards, and an electroplating current is applied to the exposed internal circuit layer 121 at the target edge to perform electroplating. Figure 8 This is a cross-sectional view of a circuit board after electroplating, along section line AA, as shown below. Figure 8 As shown, a metal layer 161 of uniform thickness is formed on the surface metal layer 110 (on the metal layer 153), and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the inner wall of the hole 141 (the surface of the metal layer 151). The metal layer 162 makes the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121 thicker, reducing the resistance and improving the connection stability.

[0074] For example, in embodiments of the present invention, such as Figure 7 As shown, a plating clamp 170 is used to hold the target edge of the circuit board. Multiple plating clamps 170 are evenly spaced along the target edge, and the plating clamps 170 are electrically connected to the exposed internal circuit layer 121 at the target edge. After the circuit board is placed in the plating solution, multiple plating clamps 170 are simultaneously energized. The plating clamps 170 apply plating current to the exposed internal circuit layer 121 at the target edge to perform plating, thereby improving the current uniformity.

[0075] like Figure 7 As shown, during the electroplating process, current flows from the inner wall of the hole 141 through the inner wall of the target internal circuit layer 121 to the surface metal layer 110. On the surface metal layer 110, the current diffuses outward from the hole 141, increasing the current density in the hole-dense area 140. This offsets the effect of the reduced current density caused by the high specific surface area of ​​the hole-dense area 140. As a result, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, improving the quality of the circuit board and reducing the scrap rate.

[0076] The metal layer described in the above embodiments can be made of conductive metals such as copper, and this embodiment of the present invention does not limit the material.

[0077] The circuit board electroplating method provided in this invention includes a circuit board comprising a surface metal layer and at least one internal circuit layer. An insulating layer is disposed between adjacent internal circuit layers and between the surface metal layer and the internal circuit layer. A densely packed hole region is formed on the surface of the circuit board, the densely packed hole region including at least one hole. A portion of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer. The target edge is one edge of the circuit board. The circuit board is placed in an electroplating solution, and an electroplating current is applied to the exposed target internal circuit layer at the target edge for electroplating. A metal layer of uniform thickness is formed on the surface metal layer, and a metal layer connecting the surface metal layer and the target internal circuit layer is formed on the inner wall of the hole. During the electroplating process, the current on the surface metal layer is changed to flow diverging from the hole to the surrounding area, increasing the current density in the densely packed hole region, thereby offsetting the effect of the reduced current density due to the high specific surface area of ​​the densely packed hole region. Thus, the metal layer formed on the surface metal layer has a uniform thickness, improving the quality of the circuit board and reducing the scrap rate.

[0078] In the above embodiments, a thin metal layer is first formed by depositing metal onto the inner wall of the hole, then a portion of the layer at the target edge of the circuit board is removed to expose the internal circuit layer, and finally electroplating is performed. Because the process of removing the portion of the layer at the target edge of the circuit board to expose the internal circuit layer is time-consuming, the metal layer deposited on the inner wall of the hole is easily oxidized, which may prevent the formation of a metal layer on the inner wall of the hole during subsequent electroplating, resulting in low-quality circuit boards or even scrap. To address this problem, the present invention provides another circuit board electroplating method. Figure 9 This is a schematic flowchart of another circuit board electroplating method provided in an embodiment of the present invention, as shown below. Figure 9 As shown, the circuit board electroplating method includes the following steps:

[0079] S201. Remove part of the layer at the target edge of the circuit board to expose the internal circuit layer of the target.

[0080] Figure 10 A front view of a circuit board to show the partial layers at the target edge. Figure 11 for Figure 10 A sectional view along section line AA, as shown below. Figure 10 and Figure 11 As shown, the circuit board includes a surface metal layer 110 and at least one internal circuit layer. This embodiment is illustrated by an example including two internal circuit layers 121 and 122. An insulating layer 131 is provided between adjacent internal circuit layers, and an insulating layer 132 is provided between the surface metal layer 110 and the adjacent internal circuit layer 121. A hole-dense region 140 is formed on the surface of the circuit board, and the hole-dense region 140 includes at least one hole 141.

[0081] One edge of the circuit board is selected as the target edge, and this target edge is processed, such as... Figure 11 As shown, a portion of the layer at the target edge of the circuit board is removed to expose the target internal circuit layer 121. In this embodiment of the invention, the internal circuit layer 121 connected to the surface metal layer 110 is referred to as the target internal circuit layer.

[0082] For example, in an embodiment of the present invention, a blind router method is used to remove a portion of the layer at the target edge of the circuit board. Figure 11 The surface metal layer 110 and insulating layer 132 are exposed, revealing the internal circuit layer 121 of the target. For example, the width D of the blind gong ranges from 5mm to 12mm, and the length L of the blind gong is the length of the target edge.

[0083] In this embodiment, the circuit board has a surface metal layer 110 on only one side and an insulating layer 133 on the other side. Therefore, when removing part of the target edge layer of the circuit board, it is only necessary to remove part of the target edge layer on the side of the circuit board with the surface metal layer 110 to expose the target internal circuit layer 121. The other side does not need to be processed.

[0084] In this embodiment, surface metal layers are provided on both opposite sides of the circuit board. When removing a portion of the target edge layer of the circuit board, a portion of the target edge layer on one side of the target surface metal layer of the circuit board is removed to expose the target internal circuit layer. At the same time, the non-target surface metal layer on one side of the target edge of the non-target surface metal layer (i.e., the surface metal layer on the opposite side) of the circuit board is removed to expose the target insulating layer located below the non-target surface metal layer, which facilitates clamping with electroplating clamps during subsequent electroplating processes.

[0085] S202. A groove parallel to the target edge is formed on the surface metal layer. The bottom of the groove exposes the target insulating layer located under the surface metal layer. The groove divides the surface metal layer into a first part close to the target edge and a second part far from the target edge. The width of the first part is smaller than the width of the second part.

[0086] Figure 12 A front view of the circuit board after removing the surface metal layer at the target edge. Figure 13 for Figure 12 A sectional view along section line AA, as shown below. Figure 12 and Figure 13 As shown, a groove 111 parallel to the target edge is formed on the surface metal layer 120. The bottom of the groove 111 exposes the target insulating layer 132 located beneath the surface metal layer 110. The groove 111 divides the surface metal layer 110 into a first portion 112 near the target edge and a second portion 113 away from the target edge. The width of the first portion 112 is smaller than the width of the second portion 113. For example, the width of the first portion 112 is much smaller than the width of the second portion 113; the width of the first portion 112 is very small, approximately a few millimeters.

[0087] For example, in some embodiments of the present invention, a groove 111 parallel to the target edge is formed on the surface metal layer 110 by means of a groove, and the bottom of the groove 111 exposes the target insulating layer 132 located below the surface metal layer 110.

[0088] S203. Immerse the circuit board in the deposition solution and deposit a metal layer on the inner wall of the hole and the surface of the exposed target insulating layer using chemical deposition.

[0089] Figure 14 This is a schematic diagram of the structure after a metal layer has been deposited, such as... Figure 14 As shown, after the circuit board is processed in step S202, it is immersed in the deposition solution. A thin metal layer 151 is deposited on the inner wall of the hole 141 by chemical deposition, a thin metal layer 152 is deposited on the surface of the exposed target insulating layer 132, and a thin metal layer 153 is deposited on the surface of the surface metal layer 110 (including the surface of the first part 112 and the surface of the second part 113).

[0090] S204. Remove the first part and the metal layer on the first part to form an insulating isolation strip between the exposed internal circuit layer and the surface metal layer of the target.

[0091] Figure 15 A schematic diagram of the structure after removing the first part and the metal layer on the first part is shown below. Figure 15 As shown, the first portion 112 and the metal layer 152 on the first portion 112 are removed, forming an insulating barrier 114 between the exposed internal circuit layer 121 and the surface metal layer 110. In this embodiment of the invention, since the first portion 112 is very narrow, the first portion 112 and the metal layer 152 on the first portion 112 can be removed by directly tearing it off, which is a simple and time-saving process.

[0092] S205. Place the circuit board in the electroplating solution and apply electroplating current to the exposed internal circuit layer at the edge of the target to perform electroplating, forming a metal layer of uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the internal circuit layer of the target on the inner wall of the hole.

[0093] Figure 16 This is another schematic diagram of circuit board electroplating provided by an embodiment of the present invention, as shown below. Figure 16As shown, in this embodiment of the invention, the circuit board processed in step S204 is vertically placed in an electrolytic tank containing electrolyte, with the target edge facing upwards. Electroplating current is applied to the exposed internal circuit layer 121 at the target edge for electroplating. Since step S204 can be directly peeled off to remove the first portion 112 and the metal layer 152 on it, forming an insulating barrier 114 between the exposed internal circuit layer 121 and the surface metal layer 110, the process is simple and time-efficient. Therefore, oxidation of the metal layer 151 deposited on the inner wall of the hole can be avoided, improving the quality of the metal layer formed on the inner wall of the hole during electroplating, thereby improving the quality of the circuit board. Furthermore, the presence of the insulating barrier 114 prevents the electroplating current from flowing directly from the exposed internal circuit layer 121 to the surface metal layer 110.

[0094] For example, in embodiments of the present invention, such as Figure 16 As shown, a plating clamp 170 is used to hold the target edge of the circuit board. Multiple plating clamps 170 are evenly spaced along the target edge, and the plating clamps 170 are electrically connected to the exposed internal circuit layer 121 at the target edge. After the circuit board is placed in the plating solution, multiple plating clamps 170 are simultaneously energized. The plating clamps 170 apply plating current to the exposed internal circuit layer 121 at the target edge to perform plating, thereby improving the current uniformity.

[0095] like Figure 16 As shown, during the electroplating process, current flows from the inner wall of the hole 141 through the inner wall of the target internal circuit layer 121 to the surface metal layer 110. On the surface metal layer 110, the current diffuses outward from the hole 141, increasing the current density in the hole-dense area 140. This offsets the effect of the reduced current density caused by the high specific surface area of ​​the hole-dense area 140. As a result, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, improving the quality of the circuit board and reducing the scrap rate.

[0096] Figure 17 This is a cross-sectional view of another type of circuit board after electroplating, along section line AA, as shown below. Figure 17 As shown, a metal layer 161 of uniform thickness is formed on the surface metal layer 110 (the surface of the metal layer 153), and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the inner wall of the hole 141 (the surface of the metal layer 151). The metal layer 162 makes the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121 thicker, reduces the resistance, and improves the connection stability.

[0097] Figure 18 A schematic flowchart of another circuit board electroplating method provided in this embodiment of the invention is shown below. Figure 18As shown, the circuit board electroplating method includes the following steps:

[0098] S301. Remove part of the layer at the target edge of the circuit board to expose the internal circuit layer of the target.

[0099] refer to Figure 10 and Figure 11 One edge of the circuit board is selected as the target edge, and this target edge is processed to remove a portion of the layer at the target edge of the circuit board, exposing the target internal circuit layer 121. In this embodiment of the invention, the internal circuit layer 121 connected to the surface metal layer 110 is referred to as the target internal circuit layer. Specifically, the structure of the circuit board has been described in detail in the foregoing embodiments, and will not be repeated here.

[0100] S302. Remove the surface metal layer near the edge of the target to expose the target insulation layer beneath the surface metal layer.

[0101] Figure 19 A schematic diagram of the structure after removing the surface metal layer near the target edge, as shown below. Figure 19 As shown, a portion of the surface metal layer 110 near the edge of the target is removed, exposing the target insulating layer 132 beneath the surface metal layer 110.

[0102] S303. Apply insulating tape to the exposed target insulation layer.

[0103] Figure 20 A schematic diagram of the structure for attaching insulating tape to the exposed target insulation layer, as shown below. Figure 20 As shown, insulating tape 180 is applied to the surface of the exposed target insulation layer 132. The thickness of the insulating tape 180 is not limited here; for example, such as... Figure 20 As shown, the thickness of the insulating tape 180 is the same as the thickness of the surface metal layer 110, that is, the surface of the insulating tape 180 is flush with the surface of the surface metal layer 110.

[0104] S304. Immerse the circuit board in the deposition solution and deposit a metal layer on the inner wall of the hole, the surface of the insulating tape and the surface metal layer using chemical deposition.

[0105] Figure 21 This is a schematic diagram of the structure after another metal layer is deposited, as shown below. Figure 21 As shown, the circuit board processed in step S303 is immersed in the deposition solution, and a thin metal layer 151 is deposited on the inner wall of the hole 141, a thin metal layer 153 is deposited on the surface of the insulating tape 180 and the surface metal layer 110 using chemical deposition.

[0106] S305. Peel off the insulating tape to form an insulating barrier between the exposed internal wiring layer and the surface metal layer of the target.

[0107] Figure 22 This is a schematic diagram of the structure after the insulating tape has been peeled off, as shown below. Figure 22 As shown, the insulating tape 180 is peeled off, and at the same time, the metal layer on the surface of the insulating tape 180 is removed, forming an insulating isolation strip 114 between the exposed internal circuit layer and the surface metal layer. In this embodiment of the invention, the insulating tape 180 is easy to peel off, the process is simple, and the time consumption is short.

[0108] S306. Place the circuit board in the electroplating solution and apply electroplating current to the exposed internal circuit layer at the edge of the target to perform electroplating, forming a metal layer of uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the internal circuit layer of the target on the inner wall of the hole.

[0109] The circuit board processed in step S305 is placed vertically in an electrolytic tank containing electrolyte, with the target edge facing upwards. Electroplating current is applied to the exposed internal circuit layer 121 at the target edge for electroplating. Since step S305 directly peels off the insulating tape 180 and removes the metal layer on its surface, forming an insulating barrier 114 between the exposed internal circuit layer and the surface metal layer, the process is simple and time-efficient. Therefore, oxidation of the metal layer 151 deposited on the inner wall of the hole can be avoided, improving the quality of the metal layer formed on the inner wall of the hole during electroplating, and thus improving the quality of the circuit board. Furthermore, the presence of the insulating barrier 114 prevents the electroplating current from flowing directly from the exposed internal circuit layer 121 to the surface metal layer 110.

[0110] During the electroplating process, current flows from the inner wall of the hole 141 through the inner wall of the target internal circuit layer 121 to the surface metal layer 110. On the surface metal layer 110, the current diffuses outward from the hole 141, increasing the current density in the hole-dense area 140. This offsets the effect of the reduced current density caused by the high specific surface area of ​​the hole-dense area 140. As a result, the metal layer 161 formed on the surface metal layer 110 has a uniform thickness, improving the quality of the circuit board and reducing the scrap rate.

[0111] Figure 23 This is a cross-sectional view of another type of circuit board after electroplating, along section line AA, as shown below. Figure 23As shown, a metal layer 161 of uniform thickness is formed on the surface metal layer 110 (the surface of the metal layer 153), and a metal layer 162 connecting the surface metal layer 110 and the target internal circuit layer 121 is formed on the inner wall of the hole 141 (the surface of the metal layer 151). The metal layer 162 makes the metal layer connecting the surface metal layer 110 and the target internal circuit layer 121 thicker, reduces the resistance, and improves the connection stability.

[0112] This invention also provides a circuit board prepared using the circuit board electroplating method provided in any of the foregoing embodiments of this invention, which has the corresponding effects.

[0113] In the description herein, it should be understood that the terms "upper," "lower," "left," "right," etc., are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of description and simplification of operation, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0114] In the description of this specification, references to terms such as "an embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0115] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0116] The technical principles of the present invention have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of the invention and should not be construed as limiting the scope of protection of the invention in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of the invention without inventive effort, and these embodiments will all fall within the scope of protection of the present invention.

Claims

1. A circuit board electroplating method, characterized in that, The circuit board includes a surface metal layer and at least one internal circuit layer, with an insulating layer between adjacent internal circuit layers, and an insulating layer between the surface metal layer and the internal circuit layer. A densely packed area of ​​vias is formed on the surface of the circuit board, each densely packed area including at least one via. The circuit board electroplating method includes: Remove a portion of the layer at the target edge of the circuit board to expose the internal circuit layer, wherein the target edge is one edge of the circuit board; The circuit board is placed in an electroplating solution, and an electroplating current is applied to the exposed internal circuit layer at the edge of the target to perform electroplating, forming a metal layer of uniform thickness on the surface metal layer, and forming a metal layer connecting the surface metal layer and the internal circuit layer of the target on the inner wall of the hole. After removing a portion of the layer at the target edge of the circuit board to expose the target internal circuit layer, the process further includes: A groove parallel to the target edge is formed on the surface metal layer, the bottom of the groove exposing the target insulating layer located below the surface metal layer, the groove dividing the surface metal layer into a first part close to the target edge and a second part away from the target edge, the width of the first part being smaller than the width of the second part; The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole, the surface of the exposed target insulating layer, and the surface metal layer using a chemical deposition method. Remove the first portion and the metal layer on the first portion to form an insulating barrier between the exposed internal circuitry layer of the target and the surface metal layer.

2. The circuit board electroplating method according to claim 1, characterized in that, Before removing a portion of the layer at the target edge of the circuit board to expose the target internal circuit layer, the process further includes: The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole using a chemical deposition method.

3. The circuit board electroplating method according to claim 1, characterized in that, A groove parallel to the edge of the target is formed on the surface metal layer, including: A groove is formed on the surface metal layer using a slotting method, parallel to the edge of the target, with the bottom of the groove exposing the target insulating layer located beneath the surface metal layer.

4. The circuit board electroplating method according to claim 1, characterized in that, After removing a portion of the layer at the target edge of the circuit board to expose the target internal circuit layer, the process further includes: Remove the surface metal layer near the edge of the target to expose the target insulating layer beneath the surface metal layer; Apply insulating tape to the exposed target insulation layer; The circuit board is immersed in a deposition solution, and a metal layer is deposited on the inner wall of the hole, the surface of the insulating tape, and the surface metal layer using a chemical deposition method. Peel off the insulating tape to form an insulating barrier between the exposed internal wiring layer and the surface metal layer.

5. The circuit board electroplating method according to any one of claims 1-4, characterized in that, Removing a portion of the layer at the target edge of the circuit board to expose the target internal circuit layer includes: A blind soldering method is used to remove part of the target edge layer of the circuit board to expose the internal circuit layer. The width of the blind soldering is 5mm-12mm and the length of the blind soldering is the length of the target edge.

6. The circuit board electroplating method according to any one of claims 1-4, characterized in that, One side of the circuit board has a surface metal layer, and the opposite side has an insulating layer. Removing a portion of the layer at the target edge of the circuit board exposes the internal circuitry layer, including: Remove a portion of the target edge layer on the side of the circuit board where the surface metal layer is located to expose the internal circuit layer.

7. The circuit board electroplating method according to any one of claims 1-4, characterized in that, The circuit board has surface metal layers on both opposite sides. Removing a portion of the layer at the target edge of the circuit board exposes the internal circuitry layer, including: Remove a portion of the target edge layer from one side of the target surface metal layer of the circuit board to expose the target internal circuit layer; Remove the non-target surface metal layer from one side of the target edge of the non-target surface metal layer of the circuit board to expose the target insulating layer located beneath the non-target surface metal.

8. The circuit board electroplating method according to any one of claims 1-4, characterized in that, Placing the circuit board in an electroplating solution and applying an electroplating current to the exposed internal circuit layer at the target edge to perform electroplating includes: The target edge of the circuit board is held by electroplating clips, and a plurality of electroplating clips are evenly spaced along the target edge. The electroplating clips are electrically connected to the exposed internal circuit layer of the target at the target edge. The circuit board is placed in an electroplating solution; Electroplating is performed by applying an electroplating current to the exposed internal circuit layer at the edge of the target using the electroplating clamp.

9. A circuit board, characterized in that, The circuit board is prepared using the electroplating method described in any one of claims 1-8.

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