Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and a method for fabricating the same. The fabrication method includes: providing a substrate; sequentially forming a bit line contact structure and a bit line on the substrate; the bit line including a connection layer connected to the bit line contact structure; etching back the sidewalls of the bit line contact structure and the connection layer; forming a first silicide layer covering the sidewalls of the bit line contact structure and a second silicide layer covering the sidewalls of the connection layer. This disclosure can reduce the contact resistance between the bit line contact structure and the bit line, and the parasitic capacitance between the bit line contact structure and adjacent conductive structures, thereby improving the electrical performance of the semiconductor structure and increasing its reliability and yield.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to the word line. The source region of the transistor forms the bit line contact region to electrically connect to the bit line through a bit line contact structure. The drain region of the transistor forms the memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0003] However, with the development of semiconductor technology, the feature size of devices in integrated circuits is becoming smaller and smaller. After semiconductor processes entered the deep submicron stage, the size of DRAM became smaller and smaller, and the size of bit line contact structures and bit lines also decreased accordingly. This easily leads to large contact resistance between bit line contact structures and bit lines, and large parasitic capacitance between bit line contact structures and adjacent conductive structures, thus adversely affecting the electrical performance of semiconductor devices. Summary of the Invention

[0004] Based on this, the present disclosure provides a semiconductor structure and its fabrication method, which can reduce the contact resistance between bit line contact structures and bit lines, as well as the parasitic capacitance between bit line contact structures and adjacent conductive structures, thereby improving the electrical performance of the semiconductor structure and increasing the reliability and yield of the semiconductor structure.

[0005] To achieve the above objectives, in one aspect, some embodiments of this disclosure provide a method for preparing a semiconductor structure, including the following steps.

[0006] A substrate is provided, on which bit line contact structures and bit lines are sequentially formed; the bit lines include a connection layer connected to the bit line contact structures.

[0007] The bit line contact structure and the sidewall of the connecting layer are etched back.

[0008] A first silicide layer is formed covering the sidewalls of the bit line contact structure, and a second silicide layer is formed covering the sidewalls of the connection layer.

[0009] In some embodiments, the bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthogonal projections of the first silicide layer and the second silicide layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

[0010] In some embodiments, the thickness of the first silicide layer is greater than the thickness of the second silicide layer.

[0011] In some embodiments, the etch-back thickness of the bit line contact structure and the sidewall of the connection layer ranges from 2 nm to 10 nm.

[0012] In some embodiments, the height of the interconnect layer is 35% to 65% of the bit line height.

[0013] In some embodiments, forming a first silicide layer covering the sidewalls of the bit line contact structure and a second silicide layer covering the sidewalls of the interconnect layer includes the following steps.

[0014] A metal material layer is deposited on the sidewalls of the bit line contact structure and the connecting layer after they have been etched back.

[0015] The resulting structure is annealed to obtain the first silicide layer and the second silicide layer.

[0016] In some embodiments, after annealing the obtained structure to obtain the first silicide layer and the second silicide layer, the preparation method further includes: removing the residual metal material layer.

[0017] In some embodiments, the annealing temperature for annealing the obtained structure is 300°C to 700°C.

[0018] In some embodiments, depositing a metal material layer on the sidewalls of the bit line contact structure and the connection layer after being etched back includes: depositing a first metal material layer on the sidewalls of the bit line contact structure after being etched back; and depositing a second metal material layer on the sidewalls of the connection layer after being etched back; wherein the first metal material layer or the second metal material layer comprises a single metal material layer or a stack of multiple metal material layers.

[0019] In some embodiments, after forming a first silicide layer covering the sidewalls of the bit line contact structure and a second silicide layer covering the sidewalls of the interconnect layer, the fabrication method further includes: forming an isolation structure on the sidewalls of the first silicide layer; and forming sidewalls on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second silicide layer.

[0020] In some embodiments, after forming sidewalls on the sidewalls of the second silicide layer and the sidewalls of the bit lines not covered by the second silicide layer, the fabrication method further includes: forming a memory node contact structure; the memory node contact structure is insulated from the first silicide layer through the isolation structure, and the memory node contact structure is insulated from the second silicide layer through the sidewalls.

[0021] On the other hand, some embodiments of this disclosure provide a semiconductor structure prepared using the fabrication methods described in the above embodiments. The semiconductor structure includes: a substrate, a bit line contact structure, a first silicide layer, a bit line, and a second silicide layer. The substrate has a bit line contact hole. The bit line contact structure is disposed within the bit line contact hole. The first silicide layer is disposed on the sidewall of the bit line contact structure. The bit line includes a connection layer connected to the bit line contact structure. The second silicide layer is disposed on the sidewall of the connection layer.

[0022] In some embodiments, the bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthogonal projections of the first silicide layer and the second silicide layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

[0023] In some embodiments, the orthographic projection of the second silicide layer on the substrate lies within the orthographic projection of the conductive layer on the substrate, and there is a gap between the boundary of the orthographic projection of the second silicide layer on the substrate and the boundary of the orthographic projection of the conductive layer on the substrate.

[0024] In some embodiments, the thickness of the first silicide layer is greater than the thickness of the second silicide layer.

[0025] In some embodiments, the height of the interconnect layer is 35% to 65% of the bit line height.

[0026] In some embodiments, the semiconductor structure further includes an isolation structure and sidewalls. The isolation structure is disposed on the sidewall of the first silicide layer. The sidewalls are disposed on the sidewall of the second silicide layer and on the sidewall of the bit line not covered by the second silicide layer.

[0027] In some embodiments, the semiconductor structure further includes: a memory node contact structure; the memory node contact structure is insulated from the first silicide layer through the isolation structure, and the memory node contact structure is insulated from the second silicide layer through the sidewall.

[0028] In this embodiment, by etching back the sidewalls of the bitline contact structure and the sidewalls of the bitline interconnect layer, a first silicide layer can be formed on the sidewalls of the bitline contact structure after the thickness has been reduced, and a second silicide layer can be formed on the sidewalls of the bitline interconnect layer after the thickness has been reduced. In this way, while ensuring that the design dimensions of the bitline and bitline contact holes remain unchanged, the first and second silicide layers can effectively reduce the contact resistance between the bitline contact structure and the bitline itself. This improves the electrical performance of the semiconductor structure, thereby increasing its reliability and yield.

[0029] Furthermore, in this embodiment, by setting the thickness of the first silicide layer and the second silicide layer, for example, by setting the orthogonal projection of the first silicide layer and the second silicide layer on the substrate to be at least within the orthogonal projection range of the conductive layer on the substrate in the bit line, and particularly by setting the orthogonal projection of the second silicide layer on the substrate to be within the orthogonal projection of the conductive layer on the substrate, and by having a gap between the boundary of the orthogonal projection of the second silicide layer on the substrate and the boundary of the orthogonal projection of the conductive layer on the substrate, it is possible to reduce the contact resistance between the bit line contact structure and the bit lines themselves while ensuring that the design dimensions of the bit lines and bit line contact holes remain unchanged, and to increase the distance between the bit line contact structure and the bit lines and adjacent conductive structures, thereby effectively reducing parasitic capacitance. This can further improve the electrical performance of the semiconductor structure, thereby further improving the reliability and yield of the semiconductor structure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0032] Figure 2 This is a schematic cross-sectional view of the bit line contact structure and the structure obtained after forming the bit line, provided in one embodiment.

[0033] Figure 3 This is a cross-sectional schematic diagram of the structure obtained after the back-etching bit line contact structure and the connecting layer sidewall provided in one embodiment;

[0034] Figure 4 This is a schematic cross-sectional view of the structure obtained after forming a first silicide layer and a second silicide layer in one embodiment.

[0035] Figure 5This is a schematic cross-sectional view of the structure obtained after forming the first silicide layer and the second silicide layer in another embodiment;

[0036] Figure 6 This is a flowchart illustrating step S300 provided in one embodiment;

[0037] Figure 7 This is a schematic cross-sectional view of the structure obtained after forming a metal material layer in one embodiment;

[0038] Figure 8 This is a schematic cross-sectional view of the structure obtained after annealing a metal material layer, as provided in one embodiment.

[0039] Figure 9 This is a schematic flowchart of a method for fabricating another semiconductor structure provided in one embodiment;

[0040] Figure 10 This is a schematic cross-sectional view of the structure obtained after forming the storage node contact structure in one embodiment; and... Figure 10 This is also a schematic diagram of a semiconductor structure provided in one embodiment.

[0041] Explanation of reference numerals in the attached figures:

[0042] 1-Substrate, 10-Shallow trench isolation structure, 11-Bit line contact hole, 12-Dielectric layer,

[0043] 2-Bit line contact structure, 3-Bit line, 31-Connection layer, 32-First barrier layer, 33-Conductive layer

[0044] 34 - Top isolation layer, 4 - First silicide layer, 5 - Second silicide layer

[0045] 41-Metallic material layer, 42-Residual metallic material layer, 6-Isolation structure, 7-Side wall,

[0046] 8-Storage node contact structure, 81-First conductive layer, 82-Conductive transition layer, 83-Second barrier layer.

[0047] 84 - Second conductive layer, 9 - Insulating layer, H - Height of bit line

[0048] H1 - Height of the connecting layer, H2 - Height of the first barrier layer

[0049] H3 - Height of the conductive layer, H4 - Height of the top insulating layer 34

[0050] T1 - Etching back thickness of the bit line contact structure sidewall; T2 - Etching back thickness of the connector layer sidewall.

[0051] D1 - thickness of the first silicide layer, D2 - thickness of the second silicide layer. Detailed Implementation

[0052] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0054] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0055] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0056] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0057] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the anticipation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0058] Please see Figure 1 This disclosure provides a method for fabricating a semiconductor structure, comprising the following steps.

[0059] S100, a substrate is provided, on which bit line contact structures and bit lines are sequentially formed. The bit lines include a connection layer connected to the bit line contact structures.

[0060] S200, the sidewall of the back-etching line contact structure and the connecting layer.

[0061] S300, a first silicide layer covering the sidewall of the bit line contact structure and a second silicide layer covering the sidewall of the connection layer are formed.

[0062] In this embodiment, by etching back the sidewalls of the bitline contact structure and the sidewalls of the interconnect layer in the bitline, a first silicide layer can be formed on the sidewalls of the bitline contact structure after the thickness has been reduced, and a second silicide layer can be formed on the sidewalls of the bitline interconnect layer after the thickness has been reduced. In this way, while ensuring that the design dimensions of the bitline and bitline contact structure remain unchanged, the first and second silicide layers can effectively reduce the contact resistance between the bitline contact structure and the bitline itself. This improves the electrical performance of the semiconductor structure, thereby increasing its reliability and yield.

[0063] In step S100, please refer to Figure 1 S100 and Figure 2 A substrate 1 is provided, on which bit line contact structures 2 and bit lines 3 are sequentially formed. The bit line 3 includes a connection layer 31 connected to the bit line contact structure 2.

[0064] In some embodiments, substrate 1 may be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 may be a single-layer structure or a multi-layer structure. For example, substrate 1 may be a silicon (Si) substrate, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 may be a layered substrate comprising, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0065] In one example, substrate 1 includes, but is not limited to, a silicon substrate or a silicon-based substrate. Substrate 1 has a shallow trench isolation structure 10, which isolates active regions within substrate 1. Optionally, the shallow trench isolation structure 10 is a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure 10 can isolate multiple active regions arranged in an array within substrate 1.

[0066] It is understood that in some embodiments, please refer to [the documentation / reference]. Figure 2 Bit line contact (BLC) holes 11 are disposed in the active region on the substrate 1, and bit line contact structures 2 fill the corresponding bit line contact holes 11. The bit line contact holes 11 can be round holes, square holes, or irregularly shaped holes. The embodiments of this disclosure do not limit the shape and size of the bit line contact holes 11.

[0067] In some embodiments, the connection layer 31 of the bit line 3 can be formed using a conductive material such as doped polysilicon or germanium-silicon. The material of the bit line contact structure 2 can be the same as or different from the material of the connection layer 31 in the bit line 3. Alternatively, the material of the bit line contact structure 2 can be the same as the material of the connection layer 31 in the bit line 3, but the doping concentrations of the two can be different, the etching rates during their formation can be different, and the etching rates when their sidewalls are etched back can also be different. The specific settings can be selected according to actual needs. This disclosure does not limit these aspects, nor does it limit the shape of the bit line contact structure 2 and the connection layer 31 after etching.

[0068] In one example, please refer to [link / reference]. Figure 2 The portion of bit line 3 outside the connection between the connecting layer 31 and the bit line contact structure 2 is insulated from the substrate 1 by the dielectric layer 12. Optionally, the dielectric layer 12 can be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer 12 can be selected and set according to actual needs.

[0069] In one example, the connection layer 31 in bit line 3 and the bit line contact structure 2 are both doped polysilicon layers, and their doping concentrations can be the same.

[0070] It is understood that in some embodiments, please refer to [the documentation / reference]. Figure 2 The bit line 3 also includes a first barrier layer 32, a conductive layer 33 and a top isolation layer 34, which are sequentially disposed on one side of the connection layer 31 along the direction away from the substrate 1.

[0071] Optionally, the first barrier layer 32 may include, but is not limited to, a titanium nitride layer. For example, the first barrier layer 32 may also be a titanium layer.

[0072] Optionally, the conductive layer 33 may include, but is not limited to, a tungsten metal layer. For example, the conductive layer 33 may also be a copper metal layer or a gold metal layer.

[0073] Optionally, the top isolation layer 34 may include, but is not limited to, a silicon nitride layer. For example, the top isolation layer 34 may also be a silicon oxynitride layer.

[0074] The first barrier layer 32, the conductive layer 33, and the top isolation layer 34 can all be obtained by patterning each material layer after deposition using a patterning process. Optionally, the top isolation layer 34 can be formed using a hard mask material to serve as a hard mask during the formation of the conductive layer 33, the first barrier layer 32, and the connecting layer 31.

[0075] Here, the deposition process includes, but is not limited to, low-pressure chemical vapor deposition (LPCVD), high-density plasma chemical vapor deposition (HDPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer chemical vapor deposition (ALCVD). The patterning process includes, but is not limited to, wet etching or dry etching, wherein dry etching includes at least one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).

[0076] In some embodiments, the height of the connection layer 31 is 35% to 65% of the height of the bit line 3. For example, the height of the connection layer 31 is 35%, 40%, 45%, 50%, 55%, 60%, or 65% of the height of the bit line 3.

[0077] Please see here. Figure 2 In the example where bit line 3 adopts the aforementioned structure, the height H of bit line 3 refers to the sum of the heights of the connecting layer 31, the first barrier layer 32, the conductive layer 33, and the top isolation layer 34; that is, H = H1 + H2 + H3 + H4, where H1 is the height of the connecting layer 31, H2 is the height of the first barrier layer 32, H3 is the height of the conductive layer 33, and H4 is the height of the top isolation layer 34.

[0078] In step S200, please refer to Figure 1 S200 and Figure 3The sidewalls of the back-etched position line contact structure 2 and the connecting layer 31.

[0079] Here, based on the materials used to form the bit line contact structure 2 and the connecting layer 31, an appropriate etching process can be selected for the etch-back process. The etching process includes, but is not limited to, wet etching or dry etching. Among them, dry etching can include at least any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-concentration plasma etching (HDP).

[0080] Furthermore, the etching thickness of the sidewalls of both the bit line contact structure 2 and the connecting layer 31 can be selected according to actual needs. Also, the etching thickness of the sidewalls of both the bit line contact structure 2 and the connecting layer 31 can be the same or different.

[0081] Optionally, the etch-back thickness of the sidewalls of the bit line contact structure 2 and the connecting layer 31 ranges from 2 nm to 10 nm. For example, please refer to... Figure 3 The etch-back thickness T1 of the sidewall of bit line contact structure 2 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm. For example, the etch-back thickness T2 of the sidewall of interconnect layer 31 is 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, or 10nm.

[0082] In addition, please combine Figure 3 It is understood that the bit line contact structure 2 is formed within the bit line contact hole 11, and the etching of the sidewall of the bit line contact structure 2 can be performed by forming a trench G on its side, which is used, for example, to fill the isolation material to form an isolation structure corresponding to the bit line contact structure 2.

[0083] In step S300, please refer to Figure 1 S300 and Figure 4 A first silicide layer 4 is formed covering the sidewall of the bit line contact structure 2, and a second silicide layer 5 is formed covering the sidewall of the connection layer 31.

[0084] The first silicide layer 4 and the second silicide layer 5 can be the same silicide layer or different silicide layers. Accordingly, the first silicide layer 4 and the second silicide layer 5 can be formed simultaneously or in stages. This disclosure does not limit this.

[0085] In some embodiments, please combine Figure 4 and Figure 5Understandably, bit line 3 also includes a conductive layer 33 located on the side of the interconnect layer 31 facing away from the substrate 1. A first silicide layer 4 is formed on the sidewall of the bit line contact structure 2 after it has been etched back, and a second silicide layer 5 is formed on the sidewall of the interconnect layer 31 after it has been etched back. The orthogonal projections of the first silicide layer 4 and the second silicide layer 5 onto the substrate 1 are at least within the orthogonal projection range of the conductive layer 33 onto the substrate 1.

[0086] Here, the orthographic projections of the first silicide layer 4 and the second silicide layer 5 on the substrate 1 are at least within the orthographic projection range of the conductive layer 33 on the substrate 1, including: both the first silicide layer 4 and the second silicide layer 5 include portions located directly below (i.e., vertically below) the conductive layer 33, or, in addition to the portions located directly below (i.e., vertically below) the conductive layer 33, the first silicide layer 4 and / or the second silicide layer 5 also include portions whose orthographic projections are located outside the orthographic projection of the conductive layer 33 on the substrate 1.

[0087] In one example, such as Figure 5 As shown, the orthographic projection of the second silicide layer 5 on the substrate 1 is located within the orthographic projection of the conductive layer 33 on the substrate 1, and there is a gap W between the boundary of the orthographic projection of the second silicide layer 5 on the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 on the substrate 1.

[0088] From the above, we can combine Figure 4 and Figure 5 It is understood that the thickness D1 of the first silicide layer 4 and the thickness D2 of the second silicide layer 5 can be the same or different.

[0089] In one example, see Figure 4 The thickness D1 of the first silicide layer 4 is equal to the thickness D2 of the second silicide layer 5.

[0090] In one example, see Figure 5 The thickness D1 of the first silicide layer 4 is greater than the thickness D2 of the second silicide layer 5.

[0091] In this embodiment, by adjusting the thickness of the first silicide layer 4 and the second silicide layer 5, the contact resistance between the bit line 3 and the bit line contact structure 2 can be reduced while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged. Furthermore, the distance between the bit line contact structure 2 and the bit line 3 and adjacent conductive structures can be increased, effectively reducing parasitic capacitance. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0092] It is worth mentioning that the first silicide layer 4 and the second silicide layer 5 can be formed simultaneously or in stages. Furthermore, the first silicide layer 4 and the second silicide layer 5 can be deposited directly or obtained by performing a metallization process on polycrystalline silicon. In addition, the first silicide layer 4 and the second silicide layer 5 can be a single-layer structure or a multi-layer structure, which can be selected according to actual needs.

[0093] For ease of description, the following embodiments use a doped polysilicon layer as an example to illustrate bit line contact structure 2 and connection layer 31, and describe in detail the preparation process of the first silicide layer 4 and the second silicide layer 5.

[0094] Please see Figure 6 In some embodiments, step S300, which involves forming a first silicide layer covering the sidewalls of the bit line contact structure and a second silicide layer covering the sidewalls of the interconnect layer, includes the following steps.

[0095] S310, a metal material layer is deposited on the sidewall after the bit line contact structure and the connecting layer have been etched back.

[0096] S320, the obtained structure is annealed to obtain a first silicide layer and a second silicide layer.

[0097] Please continue reading. Figure 6 In some embodiments, after annealing the obtained structure in step S320 to obtain the first silicide layer and the second silicide layer, the preparation method further includes: S330, removing the residual metal material layer.

[0098] In step S310, please refer to Figure 6 S310 and Figure 7 A metal material layer 41 is deposited on the sidewall of the bit line contact structure 2 and the connecting layer 31 after being etched back.

[0099] Here, the metal material layer 41 is, for example, a single metal layer or a metal compound layer. Alternatively, the metal material layer 41 may be a single material layer or multiple material layers. Optionally, the metal material layer 41 may be a tantalum (Ta) metal layer, a stack of tantalum (Ta) and tantalum titanate (TaTi), a tungsten nitride (WN) material layer, or a cobalt (Co) metal layer, etc.

[0100] In step S320, please refer to Figure 6 S320 and Figure 8 ,right Figure 7 The structure shown is subjected to annealing to obtain a first silicide layer 4 and a second silicide layer 5.

[0101] Here, it can be understood that, in relation to Figure 7After the structure shown is annealed, the portion of the metal material layer 41 located on the sidewall of the bit line contact structure 2 and the sidewall of the connecting layer 31 can be converted into a silicide layer.

[0102] Optionally, the annealing temperature for annealing the obtained structure is 300℃ to 700℃. For example, the annealing temperature can be 300℃, 400℃, 500℃, 600℃ or 700℃.

[0103] In step S330, please refer to Figure 6 S330 and Figure 8 Remove the residual metal material layer 42.

[0104] Here, the residual metal material layer 42 refers to the portion of the metal material layer 41 that is transformed to form the first silicide layer 4 and the second silicide layer 5.

[0105] It is worth mentioning that, in some embodiments, the first silicide layer 4 and the second silicide layer 5 can be made of different materials and formed in steps. Based on this, the deposition of a metal material layer 41 on the sidewalls of the bit line contact structure 2 and the connecting layer 31 after being etched back in step S310 can include: depositing a first metal material layer on the sidewalls of the bit line contact structure 2 after being etched back; and depositing a second metal material layer on the sidewalls of the connecting layer 31 after being etched back; wherein the first metal material layer or the second metal material layer includes: a single metal material layer or a stack of multiple metal material layers. Correspondingly, after forming the first metal material layer and the second metal material layer, steps S320 and S330 in the aforementioned embodiments can be referred to to prepare the first silicide layer 4 and the second silicide layer 5. This disclosure will not elaborate further on these aspects.

[0106] Please see Figure 9 In some embodiments, after forming the first silicide layer 4 covering the sidewall of the bit line contact structure 2 and the second silicide layer 5 covering the sidewall of the connection layer 31 in step S300, the preparation method further includes the following steps.

[0107] S400, an isolation structure is formed on the sidewall of the first silicide layer.

[0108] S500, sidewalls are formed on the sidewalls of the second silicide layer and on the sidewalls of the bit lines that are not covered by the second silicide layer.

[0109] It should be understood here that there is no strict order restriction for the execution of steps S400 and S500; these steps can be executed simultaneously or in other orders. Furthermore, in this embodiment of the invention, at least a portion of each step in the preparation method may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0110] In step S400, please refer to Figure 9 An isolation structure 6 is formed on the sidewall of the first silicide layer 4.

[0111] The aforementioned isolation structure 6 can be formed using a dielectric material with a high dielectric constant. For example, the isolation structure 6 can be a single dielectric layer or a stack of multiple dielectric layers. The isolation structure 6 can be formed by filling the trench G in the aforementioned example. The isolation structure 6 is used to insulate the corresponding bit line contact structure 2, and the isolation structure 6 covers the sidewalls of the first silicide layer 4; that is, the first silicide layer 4 can be a component of the equivalent bit line contact structure to ensure that the dimensions of the equivalent bit line contact structure meet the design requirements. (The equivalent bit line contact structure can be formed by the bit line contact structure 2 and the first silicide layer 4 together).

[0112] In step S500, please refer to Figure 9 Sidewalls 7 are formed on the sidewalls of the second silicide layer 5 and on the sidewalls of the bit line 3 that are not covered by the second silicide layer 5.

[0113] The sidewall 7 can be formed of a dielectric material with a low dielectric constant, for example, as a single dielectric layer or a stack of multiple dielectric layers. The sidewall 7 is used to insulate the corresponding bit line 3, and it covers the second silicide layer 5 and the sidewall of the bit line 3; that is, the second silicide layer 5 can be a component of the equivalent bit line to ensure that the dimensions of the equivalent bit line meet design requirements. Furthermore, the thickness of the sidewall 7 can be selected according to actual needs.

[0114] Optionally, the isolation structure 6 and the sidewall 7 are respectively constructed by stacking a first silicon nitride layer, a silicon oxide layer, and a second silicon nitride layer. The isolation structure 6 and the sidewall 7 can be formed simultaneously.

[0115] In this embodiment, the formation of the first silicide layer 4 and the second silicide layer 5 is arranged before the formation of the isolation structure 6 corresponding to the bit line contact structure 2 and the sidewall 7 corresponding to the bit line 3. This simplifies the semiconductor structure fabrication process and reduces the difficulty of semiconductor structure fabrication, thereby improving the production efficiency and yield of semiconductor structures.

[0116] Please continue reading. Figure 9 and Figure 10 In some embodiments, the fabrication method further includes: S600, forming a storage node contact structure 8. The storage node contact structure 8 is insulated from the first silicide layer 4 through the isolation structure 6, and the storage node contact structure 8 is insulated from the second silicide layer 5 through the sidewall 7.

[0117] It is understood that the storage node contact structure 8 is typically formed within the corresponding storage node contact hole. For example, storage node contact holes can be formed on the resulting structure after the isolation structure 6 and sidewall 7 are formed, so as to form storage node contact structures 8 within the storage node contact holes, and to form an insulating layer 9 between adjacent storage node contact structures 8, so as to effectively insulate adjacent storage node contact structures 8 using the insulating layer 9.

[0118] Optionally, the storage node contact structure 8 includes a first conductive layer 81, a conductive transition layer 82, a second barrier layer 83, and a second conductive layer 84 sequentially stacked along a direction away from the substrate 1. However, it is not limited to this. The first conductive layer 81 is, for example, a doped polysilicon layer. The conductive transition layer 82 is, for example, a cobalt silicide layer. The second barrier layer 83 is, for example, a titanium nitride layer. The second conductive layer 84 is, for example, a tungsten metal layer.

[0119] Optionally, the insulating layer 9 can be a silicon nitride layer, such as one or more silicon nitride layers. Furthermore, the insulating layer 9 can be formed in one step or gradually stacked during the fabrication of other layer structures. That is, the insulating layer 9 here refers to the entire insulating portion located between adjacent memory node contact structures 8.

[0120] This disclosure provides a semiconductor structure prepared using the methods described in the above embodiments. The semiconductor structure also possesses all the technical advantages achievable by the above preparation methods, and will not be detailed here.

[0121] Please see Figure 10 The semiconductor structure includes: a substrate 1, a bit line contact structure 2, a bit line 3, a first silicide layer 4, and a second silicide layer 5. The substrate 1 has a bit line contact hole 11. The bit line contact structure 2 is disposed within the bit line contact hole 11. The first silicide layer 4 is disposed on the sidewall of the bit line contact structure 2. The bit line 3 includes a connection layer 31 connected to the bit line contact structure 2. The second silicide layer 5 is disposed on the sidewall of the connection layer 31.

[0122] Optionally, the substrate 1 is a silicon substrate or a silicon-based substrate, and the substrate 1 has a shallow trench isolation structure 10, which isolates active regions within the substrate 1. The shallow trench isolation structure 10 is, for example, a silicon oxide (SiO2) isolation structure. The shallow trench isolation structure 10 can isolate multiple active regions arranged in an array within the substrate 1. Bit line contact holes 11 are disposed within the active regions of the substrate 1.

[0123] Optionally, the bit line 3 includes a connection layer 31, a first barrier layer 32, a conductive layer 33 and a top isolation layer 34 disposed sequentially along a direction away from the substrate 1.

[0124] In some embodiments, the connection layer 31 of the bit line 3 may be a doped polysilicon layer or a germanium-silicon layer with conductive properties. The bit line contact structure 2 may be the same as or different from the structure of the connection layer 31 in the bit line 3.

[0125] In one example, the connection layer 31 in bit line 3 and the bit line contact structure 2 are both doped polysilicon layers, and their doping concentrations can be the same.

[0126] In one example, the first barrier layer 32 is a titanium nitride layer or a titanium layer.

[0127] In one example, the conductive layer 33 is a tungsten metal layer, a copper metal layer, or a gold metal layer.

[0128] In one example, the top isolation layer 34 is a silicon nitride layer or a silicon oxynitride layer.

[0129] In one example, the portion of bit line 3 outside the connection layer 31 and bit line contact structure 2 is insulated from the substrate 1 by the dielectric layer 12. Optionally, the dielectric layer 12 can be an insulating layer such as a silicon nitride layer, a silicon oxide layer, or a silicon oxynitride layer. The thickness of the dielectric layer 12 can be selected and set according to actual needs.

[0130] In some embodiments, the height of the connection layer 31 is 35% to 65% of the height of the bit line 3. For example, the height of the connection layer 31 is 35%, 40%, 45%, 50%, 55%, 60%, or 65% of the height of the bit line 3.

[0131] In some embodiments, the first silicide layer 4 and the second silicide layer 5 may be the same silicide layer or different silicide layers.

[0132] Optionally, the orthographic projections of the first silicide layer 4 and the second silicide layer 5 onto the substrate 1 are at least within the orthographic projection range of the conductive layer 33 onto the substrate 1.

[0133] Here, the orthographic projections of the first silicide layer 4 and the second silicide layer 5 on the substrate 1 are at least within the orthographic projection range of the conductive layer 33 on the substrate 1, including: both the first silicide layer 4 and the second silicide layer 5 include portions located directly below (i.e., vertically below) the conductive layer 33, or, in addition to the portions located directly below (i.e., vertically below) the conductive layer 33, the first silicide layer 4 and / or the second silicide layer 5 also include portions whose orthographic projections are located outside the orthographic projection of the conductive layer 33 on the substrate 1.

[0134] In one example, the orthographic projection of the second silicide layer 5 on the substrate 1 lies within the orthographic projection of the conductive layer 33 on the substrate 1, and there is a gap between the boundary of the orthographic projection of the second silicide layer 5 on the substrate 1 and the boundary of the orthographic projection of the conductive layer 33 on the substrate 1.

[0135] Therefore, the thickness of the first silicide layer 4 and the thickness of the second silicide layer 5 can be the same or different.

[0136] In one example, the thickness of the first silicide layer 4 is equal to the thickness of the second silicide layer 5.

[0137] In one example, the thickness of the first silicide layer 4 is greater than the thickness of the second silicide layer 5.

[0138] In this embodiment, by adjusting the thickness of the first silicide layer 4 and the second silicide layer 5, the contact resistance between the bit line 3 and the bit line contact structure 2 can be reduced while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged. Furthermore, the distance between the bit line contact structure 2 and the bit line 3 and adjacent conductive structures can be increased, effectively reducing parasitic capacitance. This further improves the electrical performance of the semiconductor structure, thereby enhancing its reliability and yield.

[0139] Please continue reading. Figure 10 In some embodiments, the semiconductor structure further includes an isolation structure 6 and sidewalls 7. The isolation structure 6 is disposed on the sidewall of the first silicide layer 4. The sidewalls 7 are disposed on the sidewalls of the second silicide layer 5 and on the sidewalls of the bit lines 3 not covered by the second silicide layer 5.

[0140] Optionally, the isolation structure 6 is formed of a dielectric material with a high dielectric constant, such as a single dielectric layer or a stack of multiple dielectric layers. The isolation structure 6 is used to insulate the corresponding bit line contact structure 2, and the isolation structure 6 is disposed on the sidewall of the first silicide layer 4; that is, the first silicide layer 4 can be a component of the equivalent bit line contact structure to ensure that the dimensions of the equivalent bit line contact structure meet design requirements. (The equivalent bit line contact structure can be composed of the bit line contact structure 2 and the first silicide layer 4).

[0141] Optionally, the sidewall 7 can be formed of a dielectric material with a low dielectric constant, such as a single dielectric layer or a stack of multiple dielectric layers. The sidewall 7 is used to insulate the corresponding bit line 3, and it covers the second silicide layer 5 and the sidewall of the bit line 3; that is, the second silicide layer 5 can be a component of the equivalent bit line to ensure that the dimensions of the equivalent bit line meet design requirements. (The equivalent bit line can be formed by the bit line 3 and the second silicide layer 5 together). Furthermore, the thickness of the sidewall 7 can be selected according to actual needs.

[0142] In one example, the isolation structure 6 and the sidewall 7 are respectively constructed by stacking a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer.

[0143] Please continue reading. Figure 10 In some embodiments, the semiconductor structure further includes a memory node contact structure 8. The memory node contact structure 8 is insulated from the first silicide layer 4 through the isolation structure 6, and is insulated from the second silicide layer 5 through the sidewall 7.

[0144] Optionally, the storage node contact structure 8 includes a first conductive layer 81, a conductive transition layer 82, a second barrier layer 83, and a second conductive layer 84 sequentially stacked along a direction away from the substrate 1. However, it is not limited to this. The first conductive layer 81 is, for example, a doped polysilicon layer. The conductive transition layer 82 is, for example, a cobalt silicide layer. The second barrier layer 83 is, for example, a titanium nitride layer. The second conductive layer 84 is, for example, a tungsten metal layer.

[0145] Optionally, an insulating layer 9 is further provided between adjacent storage node contact structures 8. The insulating layer 9 can be a silicon nitride layer, such as one or more silicon nitride layers. Here, the insulating layer 9 refers to the entire insulating portion located between adjacent storage node contact structures 8.

[0146] In summary, the semiconductor structure and its fabrication method provided in this disclosure can, while ensuring that the design dimensions of the bit line 3 and the bit line contact hole 11 remain unchanged, not only reduce the contact resistance between the bit line contact structure 2 and the bit line 3, but also increase the distance between the bit line contact structure 2 and the bit line 3 and adjacent conductive structures, thereby effectively reducing parasitic capacitance. This effectively improves the electrical performance of the semiconductor structure, further enhancing its reliability and yield.

[0147] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0148] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a bit line contact structure and a bit line are sequentially formed; the bit line includes a connection layer connected to the bit line contact structure. The bit line contact structure and the sidewalls of the connecting layer are re-etched back; A first silicide layer is formed covering the sidewalls of the bit line contact structure, and a second silicide layer is formed covering the sidewalls of the connection layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthogonal projections of the first silicide layer and the second silicide layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The thickness of the first silicide layer is greater than the thickness of the second silicide layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The etch-back thickness of the bit line contact structure and the sidewall of the connecting layer ranges from 2 nm to 10 nm.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, The height of the connection layer is 35% to 65% of the bit line height.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first silicide layer covering the sidewalls of the bit line contact structure and a second silicide layer covering the sidewalls of the interconnect layer includes: A metal material layer is deposited on the sidewall of the bit line contact structure and the connecting layer after they have been etched back. The resulting structure is annealed to obtain the first silicide layer and the second silicide layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, After annealing the obtained structure to obtain the first silicide layer and the second silicide layer, the preparation method further includes: removing the residual metal material layer.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that, The annealing temperature for annealing the obtained structure is 300℃~700℃.

9. The method for preparing a semiconductor structure according to claim 6, characterized in that, A metal material layer is deposited on the sidewalls of the bit line contact structure and the connecting layer after they have been etched back, including: A first metal material layer is deposited on the sidewall of the bit line contact structure after it has been etched back. A second metallic material layer is deposited on the sidewall after the connecting layer has been etched back; The first metal material layer or the second metal material layer may be a single metal material layer or a stack of multiple metal material layers.

10. The method for preparing a semiconductor structure according to claim 1, characterized in that, After forming the first silicide layer covering the sidewalls of the bit line contact structure and the second silicide layer covering the sidewalls of the interconnect layer, the fabrication method further includes: An isolation structure is formed on the sidewall of the first silicide layer; Sidewalls are formed on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second silicide layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, After forming sidewalls on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second silicide layer, the fabrication method further includes: A storage node contact structure is formed; the storage node contact structure is insulated from the first silicide layer through the isolation structure, and the storage node contact structure is insulated from the second silicide layer through the sidewall.

12. A semiconductor structure, said semiconductor structure being prepared by the preparation method according to any one of claims 1-11, characterized in that, include: Substrate with bit line contact holes; The bit line contact structure is disposed within the bit line contact hole; A first silicide layer is disposed on the sidewall of the bit line contact structure; Bit line, the bit line including a connection layer connected to the bit line contact structure; And a second silicide layer is disposed on the sidewall of the connecting layer.

13. The semiconductor structure according to claim 12, characterized in that, The bit line further includes a conductive layer located on the side of the interconnect layer opposite to the substrate; wherein the orthogonal projections of the first silicide layer and the second silicide layer on the substrate are at least within the orthogonal projection range of the conductive layer on the substrate.

14. The semiconductor structure according to claim 13, characterized in that, The orthographic projection of the second silicide layer on the substrate lies within the orthographic projection of the conductive layer on the substrate, and there is a gap between the boundary of the orthographic projection of the second silicide layer on the substrate and the boundary of the orthographic projection of the conductive layer on the substrate.

15. The semiconductor structure according to claim 13, characterized in that, The thickness of the first silicide layer is greater than the thickness of the second silicide layer.

16. The semiconductor structure according to claim 12, characterized in that, The height of the connection layer is 35% to 65% of the bit line height.

17. The semiconductor structure according to claim 12, characterized in that, The semiconductor structure also includes: An isolation structure is disposed on the sidewall of the first silicide layer; Sidewalls are provided on the sidewalls of the second silicide layer and on the sidewalls of the bit lines not covered by the second silicide layer.

18. The semiconductor structure according to claim 17, characterized in that, The semiconductor structure also includes: Storage node contact structure; the storage node contact structure is insulated from the first silicide layer through the isolation structure, and the storage node contact structure is insulated from the second silicide layer through the sidewall.

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