Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor comprises the following steps: providing a substrate, the substrate comprising an array-arranged active region and an isolation structure separating the active regions, the substrate having opposite first and second surfaces; forming a buried word line structure, the buried word line structure being located on one side of the substrate close to the first surface and embedded in the active region; forming a bit line structure, the bit line structure being located on the first surface of the substrate and electrically connected with the active region; and forming a capacitor structure, the capacitor structure being located on the second surface of the substrate and connected with the active region in a one-to-one correspondence. The preparation method of the semiconductor structure can reduce the area of a single DRAM unit; meanwhile, since the transistor structure and the capacitor structure do not need to occupy the space of each other, the device size does not need to be shrunk, so that the device performance can be guaranteed to be unaffected. In addition, by embedding the buried word line structure into the active region, the gate control capability can be enhanced, and the working current can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to semiconductor structures and their preparation methods. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of an array of memory cells for storing data and peripheral circuitry surrounding the array. Each memory cell typically includes a word line structure, a bit line structure, and a capacitor. The word line voltage on the word line structure controls the switching on and off of transistors, allowing data to be read from or written to the capacitor via the bit line structure.

[0003] As manufacturing processes continue to advance, DRAM sizes are shrinking, with process nodes reaching 10nm and below. This significantly increases the energy density per unit area of ​​DRAM devices, negatively impacting device performance. Ensuring that device performance meets requirements while maintaining the trend of DRAM miniaturization is a pressing issue that needs to be addressed. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problem of performance degradation caused by DRAM size reduction, so that DRAM devices can still meet performance requirements while reducing size.

[0005] One embodiment of this application discloses a semiconductor structure, including: a substrate, including an array of active regions and an isolation structure separating the active regions; the substrate having opposing first and second surfaces; an embedded word line structure located on the side of the substrate near the first surface and embedded in the active regions; a bit line structure located on the first surface of the substrate and electrically connected to the active regions; and a capacitor structure located on the second surface of the substrate and connected to the active regions one by one.

[0006] In the aforementioned semiconductor structure, the word line structure, bit line structure, and active region are located on one side of the first surface of the substrate, while the capacitor structure is located on one side of the second surface of the substrate. This allows for the formation of both transistor and capacitor structures within the same region, reducing the area of ​​a single DRAM cell. Furthermore, since the transistor and capacitor structures do not need to encroach on each other's space, device size does not need to be miniaturized, thus ensuring that device performance remains unaffected. Additionally, because the buried word line structure is embedded within the active region, gate control capability is enhanced, and operating current is increased.

[0007] In one embodiment, the active region includes a source terminal, a drain terminal, and a channel region located between the source terminal and the drain terminal; a bit line structure is connected to the source terminal of the active region, and a capacitor structure is connected to the drain terminal of the active region.

[0008] In one embodiment, the buried word line structure has a word line conductive layer on the side away from the first surface, the word line conductive layer being embedded in a channel region in the active region; the buried word line structure also includes a gate oxide layer located between the word line conductive layer and the active region.

[0009] By embedding the word line conductive layer into the channel region of the active region, two current channels can be formed in the channel region, located on opposite sides of the word line structure, thereby increasing the device operating current and enhancing the gate control capability.

[0010] In one embodiment, the source and drain terminals are not on the same plane.

[0011] In one embodiment, the channel region is perpendicular to either the first surface or the second surface.

[0012] In one embodiment, the source and drain terminals are P-type doped and the channel region is N-type doped; or the source and drain terminals are N-type doped and the channel region is P-type doped.

[0013] In one embodiment, the embedded word line structure has a word line dielectric layer on the side near the first surface, located in the substrate, the surface of the word line dielectric layer near the first surface being flush with the first surface and exposed to the first surface of the substrate.

[0014] The word line dielectric layer can cover the gate oxide layer and the word line conductive layer in the substrate, providing good protection for the word line conductive layer and the gate oxide layer, and improving the stability of device performance.

[0015] In one embodiment, the semiconductor structure further includes a node contact structure located on the side of the substrate near the second surface, the surface of the node contact structure near the second surface being flush with the second surface and exposed to the second surface of the substrate; the capacitor structure is electrically connected to the drain terminal of the active region through the node contact structure.

[0016] Another aspect of this application discloses a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array of active regions and an isolation structure separating the active regions, the substrate having opposing first and second surfaces; forming a buried word line structure, the buried word line structure being located on the side of the substrate near the first surface and embedded in the active regions; forming a bit line structure, the bit line structure being located on the first surface of the substrate and electrically connected to the active regions; and forming a capacitor structure, the capacitor structure being located on the second surface of the substrate and correspondingly connected to the active regions.

[0017] The aforementioned semiconductor structure fabrication method, by forming word line structures, bit line structures, and active regions on the side near the first surface of the substrate, and forming capacitor structures on the side near the second surface of the substrate, allows the transistor structure and capacitor structure to share the same planar area, reducing the area of ​​a single DRAM cell. Simultaneously, since the transistor structure and capacitor structure do not need to encroach on each other's space, the device size does not need to be miniaturized, thus ensuring that device performance is not affected. Furthermore, by embedding the buried word line structure into the active region, gate control capability can be enhanced, and operating current can be increased.

[0018] In one embodiment, forming an embedded word line structure includes: forming a first patterned mask layer on a first surface; forming word line trenches in a substrate based on the first patterned mask layer, the word line trenches extending along a first direction; and forming an embedded word line structure in the word line trenches.

[0019] In one embodiment, forming an embedded word line structure in a word line trench includes: forming a gate oxide layer covering the bottom and sidewalls of the word line trench; forming a word line conductive layer filling the word line trench and covering a first surface; removing the word line conductive layer on the first surface; reducing the thickness of the word line conductive layer in the word line trench; and forming a word line dielectric layer on the upper surface of the word line conductive layer.

[0020] In one embodiment, forming a bitline structure includes: forming a bitline conductive material layer covering a first surface and an embedded word line structure; forming a second patterned mask layer on the upper surface of the bitline conductive material layer; and etching the bitline conductive material layer based on the second patterned mask layer until the first surface is exposed to form a bitline structure extending along a second direction.

[0021] In one embodiment, the bit-line conductive material layer includes a metal layer and a metal barrier layer, the metal barrier layer being located between the metal layer and the first surface.

[0022] In one embodiment, after forming the bit line structure, the method further includes: forming a bit line dielectric layer, the bit line dielectric layer filling the gaps between the bit line structures, and the top surface of the bit line dielectric layer being flush with the top surface of the bit line structure.

[0023] In one embodiment, after forming the bit line dielectric layer, the method further includes: forming an insulating material layer covering the surface of the bit line structure and the bit line dielectric layer; forming a metal interconnect layer on the surface of the insulating material layer; bonding the resulting structure to a support substrate, wherein the surface of the metal interconnect layer away from the substrate is the bonding surface; and thinning the second surface of the substrate.

[0024] In one embodiment, before forming the capacitor structure, the method further includes forming a node contact structure on one side of the substrate near the second surface, wherein the node contact structure is connected to the active region in a one-to-one correspondence.

[0025] In one embodiment, forming a capacitor structure includes: forming a plurality of arrayed capacitor structures on a second surface, the capacitor structure including a lower electrode, an upper electrode and a capacitor dielectric layer located between the lower electrode and the upper electrode, wherein the lower electrode is electrically connected to a node contact structure.

[0026] In one embodiment, the drain, source, and channel regions are formed in the active region by ion implantation or epitaxial doping.

[0027] In one embodiment, the substrate includes a silicon-on-insulator substrate. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of the cross-sectional structure of the substrate in one embodiment of this application;

[0031] Figure 3a This is a schematic cross-sectional view of a semiconductor structure after an active region and an isolation structure are formed in a substrate, according to an embodiment of this application.

[0032] Figure 3b For along Figure 3a A schematic diagram of the cross-sectional structure obtained by cutting along the aa' direction;

[0033] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the formation of the first patterned mask layer in one embodiment of this application;

[0034] Figure 5 This is a schematic cross-sectional view of the semiconductor structure after word line trenches are formed in one embodiment of this application;

[0035] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the word line conductive layer is formed in one embodiment of this application;

[0036] Figure 7This is a schematic cross-sectional view of the semiconductor structure after the word line dielectric layer is formed in one embodiment of this application;

[0037] Figure 8 This is a top view of the semiconductor structure after the embedded word line structure is formed in one embodiment of this application;

[0038] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after metal silicide formation in one embodiment of this application;

[0039] Figure 10a This is a schematic diagram of the cross-sectional structure obtained by cutting along the aa' direction after forming a bit line conductive material layer in one embodiment of this application;

[0040] Figure 10b This is a schematic diagram of the cross-sectional structure obtained by cutting along the bb' direction after forming the bit line conductive material layer in one embodiment of this application;

[0041] Figure 11a This is a top view of the semiconductor structure after the bit line structure is formed in one embodiment of this application;

[0042] Figure 11b For along Figure 11a A schematic diagram of the cross-sectional structure obtained by cutting along the aa' direction;

[0043] Figure 11c For along Figure 11a A schematic diagram of the cross-sectional structure obtained by cutting along the bb' direction;

[0044] Figure 12 This is a schematic cross-sectional view of the semiconductor structure after the bit line dielectric layer is formed in one embodiment of this application;

[0045] Figure 13a This is a schematic diagram of a cross-sectional structure obtained by cutting the semiconductor structure along the aa' direction after forming an insulating material layer and a metal interconnect layer in one embodiment of this application.

[0046] Figure 13b This is a schematic diagram of a cross-sectional structure obtained by cutting the semiconductor structure along the bb' direction after forming an insulating material layer and a metal interconnect layer in one embodiment of this application.

[0047] Figure 14 This is a schematic cross-sectional view of the semiconductor structure bonded to the support substrate in one embodiment of this application;

[0048] Figure 15 This is a schematic cross-sectional view of a semiconductor structure after thinning the second surface of the substrate in one embodiment of this application;

[0049] Figure 16 This is a schematic cross-sectional view of the semiconductor structure after the node contact structure is formed in one embodiment of this application;

[0050] Figure 17 This is a schematic cross-sectional view of the semiconductor structure after the capacitor structure is formed in one embodiment of this application.

[0051] Figure 18 This is a cross-sectional schematic diagram of a semiconductor structure in one embodiment of this application.

[0052] Explanation of icon numbers:

[0053] 10. Substrate; 11. First surface; 12. Second surface; 20. Active region; 21. Source terminal; 211. Metal silicide; 22. Channel region; 23. Drain terminal; 30. Isolation structure; 41. First patterned mask layer; 42. Word line trench; 50. Buried word line structure; 51. Gate oxide layer; 52. Word line conductive layer; 53. Word line dielectric layer; 60. Bit line structure; 61. Bit line conductive material layer; 611. Metal layer; 612. Metal barrier layer; 62. Bit line dielectric layer; 71. Insulating material layer; 72. Metal interconnect layer; 73. Support substrate; 80. Node contact structure; 90. Capacitor structure; 91. Lower electrode; 92. Capacitor dielectric layer; 93. Upper electrode. Detailed Implementation

[0054] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0056] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0057] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0058] With the continuous development of manufacturing processes, DRAM sizes are becoming smaller and smaller, with DRAM process nodes reaching 10nm and below. This significantly increases the energy density per unit area of ​​DRAM devices, negatively impacting device performance. Ensuring that device performance meets requirements while continuing the trend of DRAM miniaturization is a pressing issue. To address this problem, this application discloses a semiconductor structure and its fabrication method.

[0059] like Figure 1 As shown, one embodiment of this application discloses a method for fabricating a semiconductor structure, comprising:

[0060] S10: Provide a substrate, the substrate including an array of active regions and isolation structures separating the active regions, the substrate having opposing first and second surfaces;

[0061] S20: Forming an embedded word line structure, the embedded word line structure is located on the side of the substrate near the first surface and is embedded in the active region;

[0062] S30: Forming a bit line structure, the bit line structure is located on the first surface of the substrate and is electrically connected to the active region;

[0063] S40: Forming a capacitor structure located on the second surface of the substrate, which is connected to the active region one-to-one.

[0064] The aforementioned semiconductor structure fabrication method, by forming word line structures, bit line structures, and active regions on one side near the first surface of the substrate, and forming capacitor structures on one side near the second surface of the substrate, allows the transistor structure and capacitor structure to share the same planar region, reducing the cell area of ​​a single DRAM structure and increasing storage density. Simultaneously, since the transistor structure and capacitor structure are located on opposite sides of the substrate, they do not need to encroach on each other's space, thus eliminating the need for device size miniaturization and ensuring unaffected device performance. Furthermore, by embedding the buried word line structure into the active region, gate control capability can be enhanced, and operating current can be increased.

[0065] In step S10, the substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator (SOI) substrate. For example, as... Figure 2As shown, this embodiment uses a silicon-on-insulator (SiI) substrate as an example for illustration. The SiI substrate includes a top silicon layer, a back substrate, and a buried oxide layer between the top silicon layer and the back substrate. Active regions 20 arranged in an array and isolation structures 30 separating the active regions 20 are formed within the substrate 10, as shown... Figure 3a and Figure 3b As shown. For example, the isolation structure 30 may be a shallow trench isolation (STI) structure, and the material forming the shallow trench isolation structure 30 may include a silicon oxide layer. The shallow trench isolation structure 30 defines a plurality of active areas 20 (AA) in the substrate 10, and the plurality of active areas 20 may be arranged in a staggered array.

[0066] Top view of substrate 10 as shown Figure 3a As shown, the active regions 20 can be arranged parallel to each other, and the center of one active region 20 can be adjacent to the end portion of another adjacent active region 20. A schematic cross-sectional view of the substrate 10 along the aa' direction is shown below. Figure 3b As shown, each active region 20 includes a source terminal 21, a drain terminal 23 arranged in a vertical direction, and a channel region 22 located between the source terminal 21 and the drain terminal 23. The source terminal 21 is exposed to the first surface 11 of the substrate 10.

[0067] In some embodiments, the active region can be a PNP-type stacked structure, with source terminal 21 and drain terminal 23 being P-type doped and channel region 22 being N-type doped. Optionally, in some other embodiments, the active region is an NPN-type stacked structure, with source terminal 21 and drain terminal 23 being N-type doped and channel region 22 being P-type doped. As an example, drain terminal 23, source terminal 21, and channel region 22 can be formed in the active region 20 by ion implantation or epitaxial doping.

[0068] In step S20, as Figures 4 to 7 As shown, the steps for forming the embedded character line structure 50 include:

[0069] S21: A first patterned mask layer 41 is formed on the first surface 11, such as... Figure 4 As shown.

[0070] S22: Word line trenches 42 are formed in the substrate 10 based on the first patterned mask layer 41, and the word line trenches 42 extend along a first direction, such as... Figure 5 As shown.

[0071] S23: An embedded character line structure 50 is formed in the character line groove 42, such as Figure 6 and Figure 7 As shown.

[0072] The pattern in the first patterned mask layer 41 is used to define the size and position of the word line structure. For example, the first direction is... Figure 3a The bb' direction is shown in the diagram. The word line trench 42 intersects with the active region 20 in the substrate 10, and the bottom of the word line trench 42 extends to the channel region 22. For example, the bottom of the word line trench 42 is flush with the bottom of the channel region 22.

[0073] Optionally, in some embodiments, word line trenches 42 may be formed in the substrate 10 using self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).

[0074] In step S23, the step of forming the embedded character line structure 50 in the character line groove 42 includes:

[0075] S231: A gate oxide layer 51 is formed, which covers the bottom and sidewalls of the word line trench 42;

[0076] S232: Forming a word line conductive layer 52, the word line conductive layer 52 fills the word line trench 42 and covers the first surface 11;

[0077] S233: Remove the word line conductive layer 52 on the first surface 11;

[0078] S234: Reduce the thickness of the word line conductive layer 52 in the word line trench 42;

[0079] S235: A word line dielectric layer 53 is formed on the upper surface of the word line conductive layer 52.

[0080] In step S231, the gate oxide layer 51 may include, but is not limited to, a high dielectric constant material layer, such as a silicon oxide layer or a silicon oxynitride layer. For example, a silicon oxide layer may be formed on the bottom and sidewalls of the word trench 42 using chemical vapor deposition, atomic layer deposition, plasma vapor deposition, in-situ steam generation (ISSG), or rapid thermal oxidation (RTO) processes to serve as the gate oxide layer 51.

[0081] During the formation of the gate oxide layer 51, a silicon oxide layer is easily formed on the first surface 11 of the substrate 10, covering the top of the active region 20 and affecting the conductivity of the device. Therefore, chemical mechanical polishing (CMP) or etching processes can be used to remove the silicon oxide layer on the first surface 11 to expose the top of the active region 20.

[0082] In step S232, for example, the word line conductive layer 52 can be a metal layer 611 with low resistivity, such as Ge (germanium), W (tungsten), Cu (copper), or Au (gold). As an example, a deposition process can be used to deposit metal material in the word line trench 42 to form the word line conductive layer 52, which fills the word line trench 42 and covers the first surface 11.

[0083] In steps S233 and S234, plasma etching can be used to remove the word line conductive layer 52 on the first surface 11 and reduce the thickness of the word line conductive layer 52 in the word line trench 42, such as... Figure 6 As shown. Optionally, in some embodiments, after reducing the thickness of the word line conductive layer 52, a wet etching process can be used to remove part of the gate oxide layer 51, so that the top of the gate oxide layer 51 is lower than the first surface 11 and higher than the upper surface of the word line conductive layer 52.

[0084] Optionally, in some embodiments, anisotropic plasma etching can be used to etch the exposed gate oxide layer 51 in the horizontal direction, reducing the height of the gate oxide layer 51 so that the top of the gate oxide layer 51 is flush with the upper surface of the word line conductive layer 52. By using anisotropic plasma etching to etch the gate oxide layer 51, the etching direction can be mainly concentrated in the horizontal direction, minimizing the etching of the gate oxide layer 51 in the vertical direction, so that the gate oxide layer 51 is flush with the upper surface of the word line conductive layer 52 after etching.

[0085] In step S235, the word line dielectric layer 53 may be, for example, a silicon nitride layer. The word line dielectric layer 53 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes to cover the word line conductive layer 52 and the gate oxide layer 51. For example, the upper surface of the word line dielectric layer 53 is flush with the first surface 11, such as... Figure 7 As shown. After forming the embedded character line structure 50, the top view of the resulting structure is as follows. Figure 8 As shown.

[0086] The above-described semiconductor structure fabrication method, by reducing the height of the gate oxide layer 51, can ensure that the word line dielectric layer 53 simultaneously covers the word line conductive layer 52 and the gate oxide layer 51, preventing the gate oxide layer 51 from being exposed to the first surface 11 and damaged by other etching processes, thus providing good protection for the buried word line structure 50.

[0087] In step S30, a bit line structure 60 is formed on the first surface 11 of the substrate 10, and the bit line structure 60 is electrically connected to the active region 20. For example, as shown... Figures 9 to 11c As shown, the steps for forming the bitline structure 60 include:

[0088] S31: Forming a bit line conductive material layer 61, the bit line conductive material layer 61 covers the first surface 11 and the embedded word line structure 50, such as Figure 10a and Figure 10b As shown.

[0089] Alternatively, in some embodiments, such as Figure 9 As shown, before forming the bit line conductive material layer 61, a metal silicide 211 may also be formed on top of the active region 20. For example, a metal silicide 211 of a first thickness is formed on the source end 21 to reduce the resistance between the source end 21 and the bit line structure 60 and increase the conduction current.

[0090] Figure 10a This is a schematic diagram of the cross-sectional structure taken along the aa' direction. Figure 10b This is a schematic diagram of the cross-sectional structure taken along the bb' direction. (Combined with...) Figure 10a and Figure 10b It is understood that the bit line conductive material layer 61 covers the first surface 11 and the embedded word line structure 50, and is connected to the metal silicide 211 in the source terminal 21. For example, the bit line conductive material layer 61 includes a metal layer 611 and a metal barrier layer 612, with the metal barrier layer 612 located between the metal layer 611 and the first surface 11. The metal layer 611 may be, for example, a tungsten layer, and the metal barrier layer 612 may be, for example, a titanium layer or a titanium nitride layer. The metal barrier layer 612 prevents interpenetration between the metal layer 611 and the silicon.

[0091] S32: A second patterned mask layer is formed on the upper surface of the bit line conductive material layer 61.

[0092] The second patterned mask layer includes a plurality of strip structures extending along a second direction, the strip structures being spaced apart, and the upper surface of the bit line conductive material layer 61 being exposed between adjacent strip structures.

[0093] S33: Etch the bit line conductive material layer 61 based on the second patterned mask layer until the first surface 11 is exposed to form a bit line structure 60, the bit line structure 60 extending along the second direction, such as... Figure 11a , 11b and Figure 11c As shown.

[0094] in, Figure 11a A top view of the semiconductor structure after the formation of bitline structure 60. Figure 11b This is a schematic diagram of the cross-sectional structure taken along the aa' direction. Figure 11c This is a schematic diagram of the cross-sectional structure taken along the bb' direction. (Combined with...) Figures 11a to 11c It can be seen that the bit line structure 60 is arranged at intervals on the first surface 11, extends along the second direction, and is electrically connected to the source terminal 21 in the active region 20.

[0095] In some embodiments, after forming the bit line structure 60, the method further includes:

[0096] S34: Forming a bit line dielectric layer 62, which fills the gaps between bit line structures 60. The top surface of the bit line dielectric layer 62 is flush with the top surface of the bit line structure 60. Figure 12 As shown.

[0097] For example, the bit line dielectric layer 62 may include, but is not limited to, a silicon nitride layer, a carbon layer, a silicon oxide layer, or a silicon oxynitride layer. As an example, a silicon nitride layer may first be formed in the gaps between the bit line structures 60 using an atomic layer deposition process or a chemical vapor deposition process. The silicon nitride layer fills the gaps between the bit line structures 60 and covers the upper surface of the bit line structures 60. Then, a chemical mechanical polishing process is used to etch the silicon nitride layer until the top surface of the bit line structure 60 is exposed, thereby forming a bit line dielectric layer 62 that is flush with the top surface of the bit line structure 60.

[0098] In some embodiments, such as Figures 13a to 15 As shown, after forming the bit line dielectric layer 62, the following is also included:

[0099] S35: An insulating material layer 71 is formed, which covers the surface of the bit line structure 60 and the bit line dielectric layer 62.

[0100] S36: A metal interconnect layer 72 is formed on the surface of the insulating material layer 71, such as... Figure 13a and Figure 13b As shown.

[0101] For example, the insulating material layer 71 may be a silicon nitride layer, and the metal interconnect layer 72 may be a copper layer. Figure 13a This is a schematic diagram of the cross-sectional structure taken along the aa' direction. Figure 13b This is a schematic diagram of the cross-sectional structure taken along the bb' direction. (Combined with...) Figure 13a and Figure 13b It is understood that the insulating material layer 71 covers the upper surface of the bit line structure 60 and the bit line dielectric layer 62, and the metal interconnect layer 72 covers the upper surface of the insulating material layer 71. The insulating material layer 71 and the bit line dielectric layer 62 together encapsulate the bit line structure 60, providing protection for the bit line structure 60 and preventing electrical connection between the bit line structure 60 and the metal interconnect layer 72.

[0102] S37: Bond the obtained structure to the support substrate 73, wherein the surface of the metal interconnect layer 72 away from the substrate 10 is the bonding surface, such as... Figure 14 As shown.

[0103] By bonding the obtained structure to the support substrate 73, the obtained structure can be fixed on the support substrate 73, which facilitates subsequent thinning processes and capacitor fabrication processes.

[0104] S38: Thinning the second surface 12 of the substrate 10, such as... Figure 15 As shown.

[0105] For example, the second surface 12 can be polished using a chemical mechanical polishing process until the buried oxide layer in the silicon-on-insulator substrate is exposed, so as to facilitate the fabrication of the node contact structure 80 in the buried oxide layer in a subsequent process.

[0106] Optionally, in some embodiments, when the substrate 10 is a silicon substrate, it is not necessary to thin the second surface 12 of the substrate 10, and a capacitor structure 90 corresponding to the active region can be directly formed on the second surface 12.

[0107] In step S40, a capacitor structure 90 is formed on the second surface 12 of the substrate 10, and the capacitor structure 90 is connected to the active region 20 in a one-to-one correspondence. Figure 17 As shown.

[0108] In some embodiments, before forming the capacitor structure 90, the method further includes: forming a node contact structure 80 on one side of the substrate 10 near the second surface 12, wherein the node contact structure 80 is connected to the active region 20 in a one-to-one correspondence, such as... Figure 16 As shown, the node contact structure 80 penetrates the buried oxide layer in the silicon-on-insulator substrate. One end of the node contact structure 80 is electrically connected to the drain terminal 23 in the active region 20, and the other end is exposed to the second surface 12. For example, the node contact structure 80 may include, but is not limited to, a tungsten layer.

[0109] For example, the steps to form the capacitor structure 90 include:

[0110] S41: A plurality of arrayed capacitor structures 90 are formed on the second surface 12. The capacitor structure 90 includes a lower electrode 91, an upper electrode 93 and a capacitor dielectric layer 92 located between the lower electrode 91 and the upper electrode 93. The lower electrode 91 is electrically connected to the node contact structure 80.

[0111] like Figure 17 As shown, the capacitor structure 90 is electrically connected to the drain terminal 23 of the active region 20 through the node contact structure 80, and the capacitor structure 90 is connected to the active region 20 in a one-to-one correspondence.

[0112] The aforementioned semiconductor structure fabrication method, by forming word line structures, bit line structures, and active regions on the side near the first surface of the substrate, and forming capacitor structures on the side near the second surface of the substrate, allows the transistor structure and capacitor structure to share the same planar area, reducing the area of ​​a single DRAM cell. Simultaneously, since the transistor structure and capacitor structure do not need to encroach on each other's space, the device size does not need to be miniaturized, thus ensuring that device performance is not affected. Furthermore, by embedding the buried word line structure into the active region, gate control capability can be enhanced, and operating current can be increased.

[0113] As an example, by employing the semiconductor structure fabrication method described in the above embodiments, a cell area of ​​4F can be fabricated. 2 This is a DRAM device. Compared to traditional DRAM device structures, this DRAM device has a smaller cell area, thus achieving higher storage density.

[0114] Another aspect of this application discloses a semiconductor structure, such as Figure 18 As shown, the semiconductor structure includes: a substrate 10, including an array of active regions 20 and an isolation structure 30 separating the active regions 20; the substrate 10 has a first surface 11 and a second surface 12 opposite to each other; an embedded word line structure 50, located on the side of the substrate 10 near the first surface 11, embedded in the active regions 20; a bit line structure 60, located on the first surface 11 of the substrate 10, electrically connected to the active regions 20; and a capacitor structure 90, located on the second surface 12 of the substrate 10, corresponding to the active regions 20 one by one.

[0115] In the aforementioned semiconductor structure, the buried word line structure 50, bit line structure 60, and active region 20 are located on the side of substrate 10 near the first surface 11, while the capacitor structure 90 is located on the side of substrate 10 near the second surface 12. The transistor structure and capacitor structure 90 share the same area, reducing the area occupied by a single DRAM cell and increasing storage density. Simultaneously, since the transistor structure and capacitor structure 90 do not need to encroach on each other's space, the device size does not need to be miniaturized, thus ensuring that device performance remains unaffected. Furthermore, because the buried word line structure 50 is embedded within the active region 20, it enhances gate control capability and increases operating current.

[0116] For example, substrate 10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator (SOI) substrate. The isolation structure 30 may be a shallow trench isolation (STI) structure, and the material forming the shallow trench isolation structure 30 may include a silicon oxide layer. The shallow trench isolation structure 30 defines a plurality of active areas 20 (AA) in substrate 10. A top view of substrate 10 is shown below. Figure 3a As shown, multiple active regions 20 can be arranged in a staggered array, with the active regions 20 arranged parallel to each other, and the center of one active region 20 can be adjacent to the end portion of another adjacent active region 20.

[0117] Each active region 20 includes a source terminal 21, a drain terminal 23 arranged vertically, and a channel region 22 located between the source terminal 21 and the drain terminal 23. The channel region 22 is perpendicular to the first surface 11 or the second surface 12, and the source terminal 21 and the drain terminal 23 are not on the same plane. For example, the source terminal 21 is exposed to the first surface 11 of the substrate 10 and is electrically connected to the bit line structure 60; the drain terminal 23 is located on the side of the substrate 10 away from the first surface 11 and is electrically connected to the capacitor structure 90. For example, the active region can be a PNP type stacked structure, wherein the source terminal 21 and the drain terminal 23 are P-type doped, and the channel region 22 is N-type doped. Optionally, in some other embodiments, the active region is an NPN type stacked structure, wherein the source terminal 21 and the drain terminal 23 are N-type doped, and the channel region 22 is P-type doped.

[0118] Bit line structure 60 is located on the first surface 11 of substrate 10. For example, bit line structure 60 may include a metal layer 611 and a metal barrier layer 612, with the metal barrier layer 612 located between the metal layer 611 and the first surface 11. The metal layer 611 may be, for example, a tungsten layer, and the metal barrier layer 612 may be, for example, a titanium layer or a titanium nitride layer. The metal barrier layer 612 prevents interpenetration between the metal layer 611 and silicon. Figure 18 As shown, a bit line dielectric layer 62 is also provided between adjacent bit line structures 60 to completely separate each bit line structure 60. For example, the bit line dielectric layer 62 may include, but is not limited to, a silicon nitride layer, a carbon layer, a silicon oxide layer or a silicon oxynitride layer.

[0119] In some embodiments, such as Figure 18 As shown, the embedded word line structure 50 has a word line conductive layer 52 on the side away from the first surface 11, and the word line conductive layer 52 is embedded in the channel region 22 in the active region 20; the embedded word line structure 50 also includes a gate oxide layer 51 located between the word line conductive layer 52 and the active region 20.

[0120] For example, the gate oxide layer 51 may include, but is not limited to, a high dielectric constant material layer, such as a silicon oxide layer or a silicon oxynitride layer. The word line conductive layer 52 may be a metal layer 611 with low resistivity, such as, for example, Ge (germanium), W (tungsten), Cu (copper), or Au (gold).

[0121] The word line conductive layer 52 is embedded in the active region 20 and extends to the channel region 22, which can form two current channels in the active region 20, such as... Figure 18As shown, the two current channels are located on both sides of the embedded word line structure 50, which improves the transistor's on-current and gate control capabilities.

[0122] In some embodiments, please refer to Figure 18 The embedded word line structure 50 has a word line dielectric layer 53 on the side near the first surface 11, located in the substrate 10. The surface of the word line dielectric layer 53 near the first surface 11 is flush with the first surface 11 and exposed to the first surface 11 of the substrate 10.

[0123] The word line dielectric layer 53 covers the word line conductive layer 52 and the gate oxide layer 51 inside the substrate 10, which can provide good protection for the word line conductive layer 52 and the gate oxide layer 51 and improve device stability.

[0124] In some embodiments, such as Figure 18 As shown, the semiconductor structure also includes a node contact structure 80 located on the side of the substrate 10 near the second surface 12. The surface of the node contact structure 80 near the second surface 12 is flush with the second surface 12 and exposed to the second surface 12 of the substrate 10. The capacitor structure 90 is electrically connected to the drain terminal 23 of the active region 20 through the node contact structure 80.

[0125] For example, the material forming the node contact structure 80 may include, but is not limited to, a tungsten layer. The node contact structure 80 penetrates a buried oxide layer in a silicon-on-insulator substrate, with one end of the node contact structure 80 electrically connected to the drain terminal 23 in the active region 20, and the other end exposed on the second surface 12 and electrically connected to the capacitor structure 90.

[0126] For example, the capacitor structure 90 includes a lower electrode 91, an upper electrode 93, and a capacitor dielectric layer 92 located between the lower electrode 91 and the upper electrode 93. The lower electrode 91 is electrically connected to the node contact structure 80. The capacitor structure 90 is electrically connected to the drain terminal 23 of the active region 20 through the node contact structure 80.

[0127] One embodiment of this application also discloses a semiconductor device, including the semiconductor structure of any of the above embodiments. For example, the semiconductor device may be a DRAM device, and the cell area of ​​the DRAM device is 4F. 2 Compared to traditional DRAM device structures, the aforementioned semiconductor devices have higher storage density and conduction current.

[0128] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0129] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0130] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple active regions arranged in an array and an isolation structure separating the multiple active regions; the multiple active regions are arranged in a staggered array. The substrate has opposing first and second surfaces; An embedded word line structure is located in the substrate on the side close to the first surface and is embedded in the active region; the active region includes a source terminal, a drain terminal, and a channel region located between the source terminal and the drain terminal; the embedded word line structure has a word line conductive layer on the side away from the first surface, and the word line conductive layer is embedded in the channel region in the active region to form two current channels in the active region; The embedded word line structure also includes a gate oxide layer located between the word line conductive layer and the active region; The bitline structure is located on the first surface of the substrate and is electrically connected to the active region; A capacitor structure is located on the second surface of the substrate and is connected to the active region in a one-to-one correspondence. The bit line structure is connected to the source terminal of the active region, and the capacitor structure is connected to the drain terminal of the active region.

2. The semiconductor structure according to claim 1, characterized in that, The source terminal and the drain terminal are not on the same plane.

3. The semiconductor structure according to claim 1, characterized in that, The channel region is perpendicular to either the first surface or the second surface.

4. The semiconductor structure according to claim 1, characterized in that, The source and drain terminals are P-type doped, and the channel region is N-type doped; or The source and drain terminals are N-type doped, and the channel region is P-type doped.

5. The semiconductor structure according to claim 1, characterized in that, The embedded word line structure has a word line dielectric layer on the side near the first surface, located in the substrate, the surface of the word line dielectric layer near the first surface being flush with the first surface and exposed to the first surface of the substrate.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The semiconductor structure further includes a node contact structure located on the side of the substrate near the second surface. The surface of the node contact structure near the second surface is flush with the second surface and exposed to the second surface of the substrate. The capacitor structure is electrically connected to the drain terminal of the active region through the node contact structure.

7. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of active regions arranged in an array and an isolation structure separating the plurality of active regions, the plurality of active regions being arranged in a staggered array, the substrate having opposing first and second surfaces; An embedded word line structure is formed, wherein the embedded word line structure is located in the substrate on the side close to the first surface and is embedded in the active region; the active region includes a source terminal, a drain terminal, and a channel region located between the source terminal and the drain terminal; the embedded word line structure has a word line conductive layer on the side away from the first surface, and the word line conductive layer is embedded in the channel region in the active region, forming two current channels in the active region; The embedded word line structure also includes a gate oxide layer located between the word line conductive layer and the active region; A bit line structure is formed, the bit line structure being located on the first surface of the substrate and electrically connected to the active region; A capacitor structure is formed, which is located on the second surface of the substrate and is connected to the active region in a one-to-one correspondence.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of the embedded character line structure includes: A first patterned mask layer is formed on the first surface; Word line trenches are formed in the substrate based on the first patterned mask layer, and the word line trenches extend along a first direction; The embedded character line structure is formed in the character line groove.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The process of forming the embedded character line structure in the character line groove includes: A gate oxide layer is formed, which covers the bottom and sidewalls of the word line trench; A word line conductive layer is formed, which fills the word line trench and covers the first surface; Remove the word line conductive layer on the first surface; Reduce the thickness of the word line conductive layer in the word line trench; A word line dielectric layer is formed on the upper surface of the word line conductive layer.

10. The method for preparing a semiconductor structure according to claim 7, characterized in that, The formation of the bit line structure includes: A bit line conductive material layer is formed, the bit line conductive material layer covering the first surface and the embedded word line structure; A second patterned mask layer is formed on the upper surface of the bit line conductive material layer; The bitline conductive material layer is etched based on the second patterned mask layer until the first surface is exposed to form the bitline structure, which extends along the second direction.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The bit-line conductive material layer includes a metal layer and a metal barrier layer, wherein the metal barrier layer is located between the metal layer and the first surface.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, After forming the bitline structure, the method further includes: A bitline dielectric layer is formed, which fills the gaps between the bitline structures, and the top surface of the bitline dielectric layer is flush with the top surface of the bitline structure.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, After forming the bit line dielectric layer, the method further includes: An insulating material layer is formed, which covers the surfaces of the bit line structure and the bit line dielectric layer; A metal interconnect layer is formed on the surface of the insulating material layer; The resulting structure is bonded to a support substrate, wherein the surface of the metal interconnect layer away from the substrate is the bonding surface; The second surface of the substrate is thinned.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Before forming the capacitor structure, the method further includes: A node contact structure is formed on the side of the substrate near the second surface, and the node contact structure is connected to the active region in a one-to-one correspondence.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the capacitor structure includes: A plurality of capacitor structures are formed on the second surface in an array. The capacitor structure includes a lower electrode, an upper electrode, and a capacitor dielectric layer located between the lower electrode and the upper electrode, wherein the lower electrode is electrically connected to the node contact structure.

16. The method for preparing a semiconductor structure according to claim 7, characterized in that, Drain, source, and channel regions are formed in the active region by ion implantation or epitaxial doping.

17. The method for preparing a semiconductor structure according to any one of claims 7-16, characterized in that, The substrate includes a silicon-on-insulator substrate.

Images