Method for manufacturing a semiconductor element

Abstract

A method of fabricating a semiconductor device is provided. The method includes providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each of which passes through the upper dielectric layer and the metallization layer; removing the upper dielectric layer; forming a width control structure between the first sacrificial layer and the second sacrificial layer, wherein the width control structure defines a recess to expose the metallization layer; forming a protective layer within the recess of the width control structure; removing the width control structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first sacrificial layer and the second sacrificial layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Applications Nos. 17 / 831,593 and 17 / 831,892 (i.e., priority date "June 3, 2022"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a method for fabricating a semiconductor device. In particular, it relates to a method that uses a width control structure to determine the width of a word line. Background Technology

[0003] With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high efficiency and miniaturization. Technological advancements in IC materials and design have resulted in several generations of ICs, each with smaller and more complex circuits than the previous generation.

[0004] A Dynamic Random Access Memory (DRAM) element is a type of random access memory that stores each bit of data in a single capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F... 2 DRAM cells are developed where F represents the minimum feature width or critical dimension (CD) of the lithography process. However, recently, with the continuous reduction of word line pitch, DRAM manufacturers face a significant challenge in reducing the area of ​​memory cells. For example, a single bit's channel can easily come into contact with a word line, leading to a short circuit due to a stacking error in the lithography process.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate including a first capacitor structure and a second capacitor structure; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each passing through the upper dielectric layer and the metallization layer, wherein the first sacrificial layer perpendicularly overlaps the first capacitor structure, and the second sacrificial layer perpendicularly overlaps the second capacitor structure; removing the upper dielectric layer; forming a width control structure between the first and second sacrificial layers, wherein the width control structure defines a recess to expose the metallization layer; forming a protective layer within the recess of the width control structure; removing the width control structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first and second sacrificial layers.

[0007] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer passing through the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first direction, and the second sacrificial layer does not overlap with the first and third sacrificial layers along the first direction; forming a width control structure between the first and third sacrificial layers, wherein the width control structure defines a recess to expose the upper dielectric layer; forming a protective layer within the recess; removing the width control structure to expose a portion of the metallization layer; and patterning the metallization layer to form a first character line surrounding the first sacrificial layer, a second character line surrounding the second sacrificial layer, and a third character line surrounding the third sacrificial layer.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer and a second sacrificial layer through the upper dielectric layer and the metallization layer; removing a portion of the upper dielectric layer between the first and second sacrificial layers to expose the metallization layer; forming a width control structure to cover a first portion of the metallization layer and expose a second portion of the metallization layer; and patterning the metallization layer to form a first character line surrounding the first sacrificial layer and a second character line surrounding the second sacrificial layer.

[0009] The embodiments disclosed herein provide a method for fabricating a semiconductor device. In this embodiment, the pattern of the character line can be determined by a width control structure. Furthermore, the character line can be formed without using a photolithography process, which could lead to overlay errors and subsequently leakage current between a channel layer and the character line. Additionally, the width of the character line can be precisely controlled by determining the thickness of the width control structure. Therefore, the performance of the semiconductor device can be improved.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0011] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with element numbers in the drawings, which represent similar elements throughout the description.

[0012] Figure 1A This is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0013] Figure 1B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 1A The semiconductor device shown is shown in cross section along line A-A'.

[0014] Figure 2A , Figure 2B and Figure 2C This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0015] Figure 3A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0016] Figure 3B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 3A The section along line A-A'.

[0017] Figure 4A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0018] Figure 4B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 4A The section along line A-A'.

[0019] Figure 5A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0020] Figure 5B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 5A The section along line A-A'.

[0021] Figure 6A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0022] Figure 6B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 6A The section along line A-A'.

[0023] Figure 7A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0024] Figure 7B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 7A The section along line A-A'.

[0025] Figure 8A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0026] Figure 8B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8A The section along line A-A'.

[0027] Figure 9A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0028] Figure 9B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 9A The section along line A-A'.

[0029] Figure 10A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0030] Figure 10B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 10AThe section along line A-A'.

[0031] Figure 11A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0032] Figure 11B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 11A The section along line A-A'.

[0033] Figure 12A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0034] Figure 12B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 12A The section along line A-A'.

[0035] Figure 13A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0036] Figure 13B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 13A The section along line A-A'.

[0037] Figure 14A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0038] Figure 14B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 14A The section along line A-A'.

[0039] Figure 15A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0040] Figure 15B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 15A The section along line A-A'.

[0041] Figure 16A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0042] Figure 16B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 16A The section along line A-A'.

[0043] Figure 17A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0044] Figure 17B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 17A The section along line A-A'.

[0045] Figure 18A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0046] Figure 18B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 18A The section along line A-A'.

[0047] Figure 19A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure.

[0048] Figure 19B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 19A The section along line A-A'.

[0049] The reference numerals in the attached figures are explained as follows:

[0050] 100: Semiconductor components

[0051] 110: Base

[0052] 112: Capacitor Structure

[0053] 112-1: Capacitor Structure

[0054] 112-3: Capacitor Structure

[0055] 114: Contact embolism

[0056] 116: Insulation layer

[0057] 120: Dielectric structure

[0058] 121: Dielectric layer

[0059] 122: Dielectric layer

[0060] 122s1: Sidewall

[0061] 122s2: Sidewall

[0062] 123: Spacer-bound dielectric

[0063] 124: Gap element

[0064] 124-1: Spacer

[0065] 124-2: Spacer

[0066] 125: Filler layer

[0067] 126: Insulation layer

[0068] 130: Character Line

[0069] 130-1: Character Line

[0070] 130-2: Character Line

[0071] 130-3: Character Line

[0072] 132: Metallization layer

[0073] 132p1: Part

[0074] 132p2: Part

[0075] 142: Gate dielectric layer

[0076] 144: Channel Layer

[0077] 144-1: Channel Layer

[0078] 144-2: Channel Layer

[0079] 144-3: Channel Layer

[0080] 150: Bit line

[0081] 150-1: Bitline

[0082] 150-2: Bitline

[0083] 161r: Opening

[0084] 161r-1: Opening

[0085] 161r-2: Opening

[0086] 161r-3: Opening

[0087] 163r: Hole

[0088] 163r-1: Hole

[0089] 163r-2: Hole

[0090] 163r-3: Hole

[0091] 170: Sacrifice Layer

[0092] 170-1: Sacrifice Layer

[0093] 170-2: Sacrificial Layer

[0094] 170-3: Sacrifice Layer

[0095] 180: Masking Pattern

[0096] 181: Masking layer

[0097] 183: Masking layer

[0098] 190: Width control layer

[0099] 192: Width Control Structure

[0100] 192r: Depression

[0101] 200: Preparation method

[0102] 202: Steps

[0103] 204: Steps

[0104] 206: Steps

[0105] 208: Steps

[0106] 210: Steps

[0107] 212: Steps

[0108] 214: Steps

[0109] 216: Steps

[0110] 218: Steps

[0111] 220: Steps

[0112] 222: Steps

[0113] 224: Steps

[0114] 226: Steps

[0115] 228: Steps

[0116] 230: Steps

[0117] 232: Steps

[0118] 234: Steps

[0119] T1: Thickness

[0120] W1: Width

[0121] X: Axis

[0122] Y: axis

[0123] Z: Axis Detailed Implementation

[0124] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0125] It should be understood that when a component is referred to as "connected to" or "coupled to" another component, the initial component may be directly connected to or coupled to the other component or other intermediate components.

[0126] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0127] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0128] It should be understood that, in the description of this disclosure, the term "about" as used to describe the quantity of ingredients, components, or reactants of this disclosure refers to variations in quantity that may occur, for example, through typical measurements used to prepare concentrates or solutions and liquid handling procedures. Furthermore, variations may occur due to negligence in measurement procedures, differences in the manufacture, source, or purity of the ingredients used to manufacture the composition or carry out the method. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0129] Figure 1A This is a top view schematic diagram illustrating a semiconductor element 100 according to some embodiments of the present disclosure.

[0130] In some embodiments, the semiconductor element 100 may include a cell region in which, for example, a [missing information] is formed. Figure 1A and Figure 1B The illustrated memory element is a memory element with the following structure. For example, the memory element may include a dynamic random access memory (DRAM) element, an over-the-top (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, for example, a DRAM may include a transistor, a capacitor, and other elements. During a read operation, a word line is asserted, turning on the transistor. The actuated transistor allows voltage to pass across the capacitor for reading via a sense amplifier through a bit line. During a write operation, when the word line is asserted, the data to be written is available on the bit line.

[0131] In some embodiments, the semiconductor element 100 may include a surrounding area (not shown) for forming a logic element (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) element, a sensor element, a microelectromechanical system (MEMS) element, a signal processing element (e.g., a digital signal processing (DSP) element), a front-end element (e.g., an analog front-end (AFE) element), or other elements.

[0132] like Figure 1A As shown, the semiconductor device 100 may include a substrate 110, a dielectric structure 120, a plurality of word lines 130, a plurality of gate dielectric layers 142, a plurality of channel layers 144, and a plurality of bit lines 150.

[0133] The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 110 may include an elemental semiconductor, including silicon or germanium in a single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of: silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy having a gradient Ge characteristic, wherein the Si to Ge composition changes from a ratio at one location of the gradient SiGe characteristic to another ratio at another location of the gradient SiGe characteristic. In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 110 may have a multilayer structure, or the substrate 110 may include a multilayer compound semiconductor structure.

[0134] The substrate 110 may have multiple doped regions therein (not shown). In some embodiments, p-type and / or n-type dopants may be doped into the substrate 110. In some embodiments, p-type dopants include boron (B), other group III elements, or any combination thereof. In some embodiments, n-type dopants include arsenic (As), phosphorus (P), other group V elements, or any combination thereof.

[0135] The dielectric structure 120 may be disposed on the substrate 110. In some embodiments, the dielectric structure 120 may include a multilayer structure. In some embodiments, the dielectric structure 120 may include silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON) or other suitable materials.

[0136] Each character line 130 (e.g., 130-1, 130-2, and 130-3) may extend along the Y-axis. Each character line 130 may be parallel. In some embodiments, each character line 130 may be physically separated by a dielectric structure 120. The character lines 130 may include conductive materials such as tungsten (W), copper (Cu), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, titanium nitride (TiN), the like, and / or combinations thereof.

[0137] In some embodiments, a gate dielectric layer 142 may be disposed on a substrate 110. In some embodiments, each gate dielectric layer 142 may be surrounded by a corresponding word line 130. In some embodiments, the gate dielectric layer 142 may have an annular shape or other suitable profile. However, this disclosure is not limited thereto. In some embodiments, the gate dielectric layer 142 may comprise silicon oxide (SiO2). x ), silicon nitride (Si x N y The gate dielectric layer may comprise a dielectric material, such as a high-dielectric-constant dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer may comprise a dielectric material, such as a high-dielectric-constant dielectric material. A high-dielectric-constant dielectric material may have a dielectric constant (k-value) greater than 4. High-dielectric-constant dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other applicable materials. Other suitable materials are within the scope of this disclosure.

[0138] In some embodiments, channel layers 144 may be disposed on substrate 110. In some embodiments, each channel layer 144 may be surrounded by a corresponding gate dielectric layer 142. In some embodiments, channel layers 144 may be surrounded by word lines 130. For example, channel layer 144-1 may be surrounded by word lines 130-1. Channel layer 144-2 may be surrounded by word lines 130-2. Channel layer 144-3 may be surrounded by word lines 130-3. Channel layer 144-1 may be aligned with channel layer 144-3 along the X-axis. Channel layer 144-2 may be unaligned with channel layer 144-1 (or channel layer 144-3) along the X-axis. In some embodiments, channel layers 144 may have a circular, elliptical, oval, or other suitable profile. However, this disclosure is not limited thereto.

[0139] The channel layer 144 material may include an amorphous semiconductor, a polycrystalline semiconductor, and / or a metal oxide. The semiconductor may include germanium (Ge), silicon (Si), tin (Sn), and antimony (Sb), but is not limited thereto. The metal oxide may include indium oxide, tin oxide, zinc oxide, a binary metal oxide, a ternary metal oxide, and a tetravalent metal oxide. A binary metal oxide may be, for example, an In-Zn based oxide (IZO), a Sn-Zn based oxide, an Al-Zn based oxide, a Zn-Mg based oxide, a Sn-Mg based oxide, an In-Mg based oxide, or an In-Ga based oxide. In-Ga-Zn oxide (IGO), and three-component metal oxides such as In-Ga-Zn based oxide (also represented as IGZO), In-Al-Zn oxide, In-S silicon oxide (also represented as ITO), In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, etc. The oxides include In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides; and four-component metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. However, this disclosure is not limited thereto.

[0140] Each bit line 150 (e.g., 150-1 and 150-2) may extend along the X-axis. Each bit line 150 may be parallel. Each bit line 150 may be physically separated. In some embodiments, bit lines 150 may be located at a horizontal bit plane (or height) above word lines 130. Bit line 150-1 may cover channel layers 144-1 and 144-3. Bit line 150-2 may cover channel layer 144-2. Bit lines 150 may contain conductive materials such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and / or combinations thereof. However, this disclosure is not limited thereto.

[0141] Figure 1B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 1A The semiconductor element 100 shown is in cross section along section line A-A'.

[0142] like Figure 1B As shown, the semiconductor element 100 also includes a plurality of capacitor structures 112 (e.g., 112-1 and 112-3). In some embodiments, channel layer 144-1 may cover or perpendicularly overlap capacitor structure 112-1. In some embodiments, channel layer 144-3 may cover or perpendicularly overlap capacitor structure 112-3. In some embodiments, from a top view, each capacitor structure 112-1 and 112-3 may have a circular profile, an oval profile, an elliptical profile, or a similar profile.

[0143] In some embodiments, each capacitor structure 112-1 and 112-3 may include a first electrode, a capacitor dielectric, and a second electrode (not shown). In some embodiments, the capacitor dielectric may surround the first electrode. In some embodiments, the second electrode may surround the first electrode. In some embodiments, the second electrode may surround the capacitor dielectric. In some embodiments, the capacitor dielectric may be disposed between the first electrode and the second electrode.

[0144] The first electrode and / or the second electrode may comprise a semiconductor material or a conductive material. The semiconductor material may comprise polycrystalline silicon or other suitable materials. The conductive material may comprise tungsten, copper, aluminum, tantalum, or other suitable materials.

[0145] The dielectric of a capacitor may include dielectric materials such as silicon oxide, tungsten oxide, zirconium oxide, copper oxide, aluminum oxide, hafnium oxide, or the like.

[0146] The semiconductor element 100 may also include a plurality of contact plugs 114. In some embodiments, the contact plugs 114 may be disposed on the capacitor structure 112. In some embodiments, the contact plugs 114 may be configured to connect the capacitor structure 112 to the channel layer 144. In some embodiments, the contact plugs 114 may include metals such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, or combinations thereof.

[0147] The semiconductor element 100 may further include an insulating layer 116. The insulating layer 116 can separate the plurality of capacitor structures 112. For example, the insulating layer 116 may comprise silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (N2OSi2), silicon nitride oxide (N2OSi2), a high dielectric constant material, or a combination thereof. The dielectric layer contact plug 114 can also be considered as an interlayer dielectric.

[0148] like Figure 1B As shown, the gate dielectric layer 142 may extend between the contact plug 114 and the bit line 150 (e.g., 150-1). The gate dielectric layer 142 may pass through the dielectric structure 120. The gate dielectric layer 142 may pass through the word line 130.

[0149] Channel layer 144 may extend between contact plug 114 and bit line (e.g., 150-1). Channel layer 144 may pass through dielectric structure 120. Channel layer 144 may pass through word line 130.

[0150] Figure 2A , Figure 2B and Figure 2C This is a flowchart illustrating a method 200 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0151] Please refer to Figure 2A The fabrication method 200 begins with step 202, which provides a substrate. In some embodiments, a plurality of capacitor structures (e.g., first, second, and third capacitor structures) may be formed within the substrate. The first capacitor structure may be aligned with the third capacitor structure along a first axis. The second capacitor structure may be misaligned along the first axis with the first capacitor structure (or the third capacitor structure). In some embodiments, a plurality of contact plugs may be formed on the capacitor structures. In some embodiments, an insulating layer may be formed on the substrate. The insulating layer may be configured to separate the contact plugs.

[0152] The fabrication method 200 continues with step 204, which involves forming a lower dielectric layer, a metallization layer, and an upper dielectric layer. In some embodiments, the lower dielectric layer may be formed on the substrate. In some embodiments, the metallization layer may be formed on the lower dielectric layer. In some embodiments, the upper dielectric layer may be formed on the metallization layer.

[0153] The fabrication method 200 continues with step 206, which involves forming a plurality of openings (e.g., first, second, and third openings). A portion of the lower dielectric layer, the upper dielectric layer, and the metallization layer may be removed. In some embodiments, each opening may extend through the lower dielectric layer, the upper dielectric layer, and the metallization layer. In some embodiments, the insulating layer may be exposed via the opening.

[0154] The fabrication method 200 continues with step 208, which involves forming multiple sacrificial layers (e.g., first, second, and third sacrificial layers). For example, the first sacrificial layer may be formed within the first opening. The second sacrificial layer may be formed within the second opening. The third sacrificial layer may be formed within the third opening. In some embodiments, the sacrificial layers may vertically overlap the capacitor structure. For example, the first sacrificial layer may vertically overlap the first capacitor structure. The second sacrificial layer may vertically overlap the second capacitor structure. The third sacrificial layer may vertically overlap the third capacitor structure. In some embodiments, the sacrificial layers may include polysilicon, gallium nitride, aluminum gallium nitride, titanium nitride, tantalum nitride, or other suitable materials.

[0155] The fabrication method 200 continues with step 210, which involves forming a mask pattern. In some embodiments, the mask pattern may include a first mask layer and a second mask layer. In some embodiments, each of the first mask layer and the second mask layer may extend along a second axis, wherein the second axis is substantially perpendicular to the first axis. In some embodiments, the first mask layer may vertically overlap the first sacrificial layer. In some embodiments, the second mask layer may vertically overlap the third sacrificial layer. In some embodiments, the second sacrificial layer may be exposed by the mask pattern.

[0156] Fabrication method 200 continues with step 212, which involves removing a portion of the upper dielectric layer. In some embodiments, the portion of the upper dielectric layer exposed by the mask pattern is removable. The upper dielectric layer does not overlap the second capacitor structure. The sidewalls of the upper dielectric layer are exposed. For example, a first sidewall and a second sidewall of the upper dielectric layer are exposed.

[0157] Please refer to Figure 2B The preparation method 200 continues with step 214, which involves forming a spacer-defining dielectric. In some embodiments, the spacer-defining dielectric may be conformally formed on the sacrificial layers and the metallization layer. The spacer-defining dielectric may cover the first sidewall and the second sidewall of the upper dielectric layer.

[0158] The fabrication method 200 continues with step 216, in which a plurality of spacers (e.g., first and second spacers) may be formed. In some embodiments, a portion of the dielectric material defined by the spacer may be removed to form the spacers. In some embodiments, the dielectric material defined by the spacer may be removed from the upper surface of the sacrificial layer and on the metallization layer. In some embodiments, the spacer may be formed on the sidewalls of the upper dielectric layer. For example, the first spacer may be formed on the first sidewall of the dielectric structure. The second spacer may be formed on the second sidewall of the dielectric structure. In some embodiments, the spacer may extend along the second axis.

[0159] The fabrication method 200 continues with step 218, which involves forming a width control layer. In some embodiments, the width control layer may be conformally formed on the sacrificial layers, the spacers, and the metallization layer. In some embodiments, the material of the width control layer may be different from that of the spacers. In some embodiments, the thickness of the width control layer may be used to determine a width of the character lines.

[0160] The fabrication method 200 continues with step 220, which involves forming a width-controlled structure (or a controlled-width structure). In some embodiments, multiple portions of the width-controlled layer on the sacrificial layers, the upper dielectric layer, the spacers, and the metallization layer are removed. In some embodiments, the width-controlled structure may be formed on the first sidewall and the second sidewall of the upper dielectric layer.

[0161] In some embodiments, the width control structure may be formed on the sidewall of the gap. In some embodiments, the thickness of the width control structure may be used to determine a width of a character line. In some embodiments, the width control structure may define a recess to expose the metallization layer. In some embodiments, the width control structure may cover a first portion of the metallization layer. In some embodiments, a second portion of the metallization layer may be exposed by the width control structure.

[0162] Preparation method 200 continues with step 222, which involves forming a filler layer. In some embodiments, the filler layer may be formed within the recess. In some embodiments, the filler layer may cover the second portion of the metallization layer.

[0163] Please refer to Figure 2C The fabrication method 200 continues with step 224, which is to remove the width control structure. In some embodiments, the first portion of the metallization layer may be exposed by the sacrificial layer, the upper dielectric layer, the spacer, and the filling layer.

[0164] The fabrication method 200 continues with step 226, which involves forming a plurality of character lines (e.g., first, second, and third character lines). In some embodiments, the first portion of the metallization layer may be removed. In some embodiments, the second portion of the metallization layer may be used to define the character line. In some embodiments, the width of the character line may be determined by controlling the thickness of the width control structure. In some embodiments, a portion of the lower dielectric layer may be removed. A trench may be formed.

[0165] Preparation method 200 continues with step 228, which involves forming an insulating layer. In some embodiments, the insulating layer may be formed within the trench, thereby creating a dielectric structure.

[0166] The fabrication method 200 continues with step 230, which involves forming a plurality of recesses (e.g., first, second, and third recesses). In some embodiments, the sacrificial layer may be removed to form the recesses. In some embodiments, the recesses may extend through the dielectric structure and the character line.

[0167] The fabrication method 200 continues with step 232, which involves forming a plurality of gate dielectric layers and a plurality of channel layers (e.g., first, second, and third channel layers). In some embodiments, the gate dielectric layers may be formed within the first recess, the second recess, and the third recess. In some embodiments, the first channel layer may be formed within the first recess. In some embodiments, the second channel layer may be formed within the second recess. In some embodiments, the third channel layer may be formed within the third recess.

[0168] The fabrication method 200 continues with step 234, which involves forming a plurality of bit lines (e.g., a first bit line and a second bit line). In some embodiments, the first bit line may cover the first channel layer and the third channel layer. In some embodiments, the second bit line may cover the second channel layer.

[0169] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A as well as Figure 19A This is a top view schematic diagram illustrating one or more stages of an example of a method for preparing a semiconductor device according to some embodiments of this disclosure. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B as well as Figure 19B They are Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A as well as Figure 19A The diagram shows a cross-sectional view. It should be understood that, for the sake of brevity, some elements are illustrated with cross-sectional views rather than top views.

[0170] Please refer to Figure 3A and Figure 3B A substrate 110 may be provided. In some embodiments, a plurality of capacitor structures 112 (e.g., 112-1 and 112-3) may be formed within the substrate 110. Capacitor structure 112-1 may be aligned with capacitor structure 112-3 along the X-axis. In some embodiments, capacitor structure 112 may have a circular, elliptical, oval, or other suitable profile. However, this disclosure is not limited thereto. In some embodiments, a plurality of contact plugs 114 may be formed on capacitor structure 112. In some embodiments, an insulating layer 116 may be formed on substrate 110. Insulating layer 116 may be configured to separate the contact plugs 114.

[0171] Please refer to Figure 4A and Figure 4B A dielectric layer 121, a metallization layer 132, and an upper dielectric layer 122 can be formed. In some embodiments, the dielectric layer 121 (or an upper dielectric layer) can be formed on the substrate 110. In some embodiments, the metallization layer 132 can be formed on the dielectric layer 121. In some embodiments, the dielectric layer 122 (or an upper dielectric layer) can be formed on the metallization layer 132. The dielectric layers 121 and / or 122 may comprise silicon oxide (SiO2). x ), silicon nitride (Si x Ny The dielectric layer 121, dielectric layer 122, and metallization layer 132 may be fabricated using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or other suitable processes.

[0172] Please refer to Figure 5A and Figure 5B This forms multiple openings 161r (e.g., 161r-1, 161r-2, and 161r-3). A portion of the dielectric layer 121, dielectric layer 122, and metallization layer 132 can be removed. In some embodiments, the openings 161r may extend through the dielectric layer 121, dielectric layer 122, and metallization layer 132. In some embodiments, the insulating layer 116 may be exposed via the openings 161r. In some embodiments, opening 161r-1 may be aligned with opening 161r-3 along the X-axis. Opening 161r-1 may be misaligned with opening 161r-2 along the X-axis.

[0173] Please refer to Figure 6A and Figure 6B Multiple sacrificial layers 170 (e.g., 170-1, 170-2, and 170-3) may be formed. For example, sacrificial layer 170-1 may be formed within opening 161r-1. Sacrificial layer 170-2 may be formed within opening 161r-2. Sacrificial layer 170-3 may be formed within opening 161r-3. In some embodiments, sacrificial layers 170 may be vertically overlapped or aligned with capacitor structure 112 along the Z-axis. For example, sacrificial layer 170-1 may be vertically overlapped with capacitor structure 112-1. Sacrificial layer 170-3 may be vertically overlapped with capacitor structure 112-3. In some embodiments, sacrificial layer 170-1 may be aligned with sacrificial layer 170-3 along the Z-axis. Sacrificial layer 170-1 may be aligned with sacrificial layer 170-2 along the X-axis.

[0174] In some embodiments, the material of the sacrificial layer 170 is different from that of the dielectric layer 121 (or 122). In some embodiments, the material of the sacrificial layer 170 is different from that of the metallization layer 132. In some embodiments, the sacrificial layer 170 may comprise polysilicon, gallium nitride, aluminum gallium nitride, titanium nitride, tantalum nitride, or other suitable materials. The fabrication technology of the sacrificial layer 170 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0175] Please refer to Figure 7A and Figure 7BA mask pattern 180 can be formed. In some embodiments, the mask pattern 180 may include a mask layer 181 and a mask layer 183. In some embodiments, each of the mask layers 181 and 183 may vertically overlap the sacrificial layer 170-1. In some embodiments, the mask layer 183 may vertically overlap the sacrificial layer 170-3. In some embodiments, the sacrificial layer 170-2 may not vertically overlap the mask pattern 180.

[0176] In some embodiments, the mask pattern 180 may include a multilayer structure. The mask pattern 180 may include carbon, silicon oxide (SiO2), such as flowable oxide (FOX), tonnen silazene (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorosilicate glass (FSG), or other suitable materials.

[0177] Please refer to Figure 8A and Figure 8B A portion of the removable dielectric layer 122. A removable mask pattern 180. In some embodiments, this portion of the removable dielectric layer 122 exposed by the mask pattern 180. Figure 8A As shown, the sidewalls of dielectric layer 122 can be exposed. For example, one sidewall 122s1 and one sidewall 122s2 of dielectric layer 122 can be exposed.

[0178] Please refer to Figure 9A and Figure 9B A spacer-defining dielectric 123 may be formed. In some embodiments, the spacer-defining dielectric 123 may be conformally formed on the sacrificial layer 170 and the metallization layer 132. The spacer-defining dielectric 123 may cover the sidewalls 122s1 and 122s2 of the dielectric layer 122.

[0179] The spacer-defined dielectric 123 may contain silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON) or other suitable materials. For example, the fabrication techniques for the spacer defining dielectric 123 may include ALD, CVD, PVD, LPCVD, PECVD or other suitable processes.

[0180] Please refer to Figure 10A and Figure 10BMultiple spacers 124 (e.g., 124-1 and 124-2) may be formed. In some embodiments, a portion of the spacer-defined dielectric 123 may be removed to form the spacers 124. In some embodiments, the spacers defining the dielectric 123 on the upper surface of the sacrificial layer 170 and on the metallization layer 132 may be removed. In some embodiments, the spacers 124 may be formed on a sidewall of the dielectric layer 122. For example, spacer 124-1 may be formed on a sidewall 122s1 of the dielectric structure 120. Spacer 124-2 may be formed on a sidewall 122s2 of the dielectric structure 120. In some embodiments, the spacers 124 may be formed on a sidewall of the sacrificial layer 170. In some embodiments, the spacers 124 may extend along the Y-axis.

[0181] Please refer to Figure 11A and Figure 11B A width control layer 190 can be formed. In some embodiments, the width control layer 190 may be conformally formed on the sacrificial layer 170, the spacer 124, and the metallization layer 132. Figure 11A As shown, the width control layer 190 can be conformally formed on the dielectric layer 122.

[0182] In some embodiments, the material of the width control layer 190 may be different from that of the spacer 124. In some embodiments, the width control layer 190 may comprise silicon nitride (Si). x N y ), silicon oxynitride (SiON) or other suitable materials. For example, the fabrication technology of the width control layer 190 may include ALD, CVD, PVD, LPCVD, PECVD or other suitable processes.

[0183] The width control layer 190 may have a thickness T1. In some embodiments, the thickness T1 of the width control layer 190 may be used to determine a width of a character line, which will be formed sequentially.

[0184] Please refer to Figure 12A and Figure 12BA width control structure 192 may be formed. In some embodiments, portions of the width control layer 190 on the upper surface of the sacrificial layer 170, the dielectric layer 122, the spacer 124, and the metallization layer 132 are removed. In some embodiments, the width control structure 192 may be formed on the sidewall 122s1 of the dielectric layer 122. In some embodiments, the width control structure 192 may be formed on the sidewall 122s2 of the dielectric layer 122. In some embodiments, the width control structure 192 may be formed on the sidewall (not shown) of the spacer 124. In some embodiments, a thickness of the width control structure 192 approximately equal to the thickness T1 may be used to determine a width of a character line, which will be formed sequentially. In some embodiments, the width control structure 192 may define a recess 192r to expose the metal layer 132. In some embodiments, the width control structure 192 may cover a portion 132p1 of the metallization layer 132. In some embodiments, a portion 132p2 of the metallization layer 132 may be exposed by the width control structure 192.

[0185] Please refer to Figure 13A and Figure 13B A filler layer 125 may be formed. In some embodiments, the filler layer 125 may be formed within the recess 192r. In some embodiments, the filler layer 125 may cover a portion 132p2 of the metallization layer 132. In some embodiments, the filler layer 125 may comprise silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON) or other suitable materials. For example, the fabrication technology of filler layer 125 may include CVD, ALD, PVD, LPCVD, PECVD or other suitable processes.

[0186] Please refer to Figure 14A and Figure 14B A removable width control structure 192 is provided. In some embodiments, a portion 132p1 of the metallization layer 132 may be exposed by the sacrificial layer 170, the dielectric layer 122, the spacer 124, and the fill layer 125. A portion 132p2 is covered by the fill layer 125.

[0187] Please refer to Figure 15A and Figure 15BMultiple character lines 130 (e.g., 130-1, 130-2, and 130-3) may be formed. In some embodiments, a portion 132p1 of the metallization layer 132 may be removed. In some embodiments, a portion 132p2 of the metallization layer 132 may be used to define the character lines 130. In some embodiments, a width W1 of the character lines 130 may be determined by the thickness of the width control structure 192. In some embodiments, a portion of the dielectric layer 121 may be removed. A recess 162r may be formed. In some embodiments, the recess 162r may be located between the character lines 130.

[0188] Please refer to Figure 16A and Figure 16B An insulating layer 126 may be formed. In some embodiments, the insulating layer 126 may be formed within a recess 162r, thereby creating a dielectric structure 120.

[0189] Please refer to Figure 17A and Figure 17B A hole 163r can be formed (e.g., 163r-1, 163r-2, and 163r-3). In some embodiments, the sacrificial layer 170 can be removed to form a plurality of holes 163r. In some embodiments, the holes 163r can pass through the dielectric structure 120 and the word line 130. Hole 163r-1 can be aligned with hole 163r-3 along the X-axis. Hole 163r-1 can be aligned with hole 163r-2 along the X-axis.

[0190] Please refer to Figure 18A and Figure 18B Multiple dielectric layers 142 and multiple channel layers 144 (e.g., 144-1, 144-2, and 144-3) may be formed. In some embodiments, the gate dielectric layer 142 may be formed within vias 163r-1, 163r-2, and 163r-3. In some embodiments, channel layer 144-1 may be formed within via 163r-1. In some embodiments, channel layer 144-2 may be formed within via 163r-2. In some embodiments, channel layer 144-3 may be formed within via 163r-3.

[0191] Please refer to Figure 19A and Figure 19B Multiple bit lines 150 (e.g., 150-1 and 150-2) can be formed. In some embodiments, bit line 150-1 may cover channel layers 144-1 and 144-3. In some embodiments, bit line 150-2 may cover channel layer 144-2.

[0192] In this embodiment, the pattern of the word line 130 can be determined by the width control structure 192. The word line 130 can be formed without using a photolithography process, which could cause overlay errors and subsequently lead to leakage current between the channel layer 144 and the word line 130. Furthermore, the width of the word line 130 can be precisely controlled by determining the thickness of the width control structure 192. Therefore, the performance of the semiconductor device 100 can be improved.

[0193] One embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate including a first capacitor structure and a second capacitor structure; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer and a second sacrificial layer, each passing through the upper dielectric layer and the metallization layer, wherein the first sacrificial layer perpendicularly overlaps the first capacitor structure, and the second sacrificial layer perpendicularly overlaps the second capacitor structure; removing the upper dielectric layer; forming a width control structure between the first and second sacrificial layers, wherein the width control structure defines a recess to expose the metallization layer; forming a protective layer within the recess of the width control structure; removing the width control structure to expose a portion of the metallization layer; and patterning the metallization layer to form a word line between the first and second sacrificial layers.

[0194] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer passing through the upper dielectric layer and the metallization layer, wherein the first sacrificial layer is aligned with the third sacrificial layer along a first direction, and the second sacrificial layer does not overlap with the first and third sacrificial layers along the first direction; forming a width control structure between the first and third sacrificial layers, wherein the width control structure defines a recess to expose the upper dielectric layer; forming a protective layer within the recess; removing the width control structure to expose a portion of the metallization layer; and patterning the metallization layer to form a first character line surrounding the first sacrificial layer, a second character line surrounding the second sacrificial layer, and a third character line surrounding the third sacrificial layer.

[0195] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate; forming a metallization layer on the substrate; forming an upper dielectric layer on the metallization layer; forming a first sacrificial layer and a second sacrificial layer through the upper dielectric layer and the metallization layer; removing a portion of the upper dielectric layer between the first and second sacrificial layers to expose the metallization layer; forming a width control structure to cover a first portion of the metallization layer and expose a second portion of the metallization layer; and patterning the metallization layer to form a first character line surrounding the first sacrificial layer and a second character line surrounding the second sacrificial layer.

[0196] The embodiments disclosed herein provide a method for fabricating a semiconductor device. In this embodiment, the pattern of the character line can be determined by a width control structure. Furthermore, the character line can be formed without using a photolithography process, which could lead to overlay errors and subsequently leakage current between a channel layer and the character line. Additionally, the width of the character line can be precisely controlled by determining the thickness of the width control structure. Therefore, the performance of the semiconductor device can be improved.

[0197] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0198] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: A substrate is provided, wherein a first capacitor structure and a second capacitor structure are included in the substrate; A metallization layer is formed on the substrate; An upper dielectric layer is formed on the metallization layer; A first sacrificial layer and a second sacrificial layer are formed, each of which passes through the upper dielectric layer and the metallization layer, wherein the first sacrificial layer overlaps perpendicularly with the first capacitor structure and the second sacrificial layer overlaps perpendicularly with the second capacitor structure. Remove the upper dielectric layer; A width control layer is formed to cover the first sacrificial layer, the second sacrificial layer, and the metallization layer; A portion of the width control layer is removed to form a width control structure between the first sacrificial layer and the second sacrificial layer, wherein the width control structure defines a recess to expose the metallization layer; A protective layer is formed within the recess of the width-controlling structure; Remove the width control structure to expose a portion of the metallization layer; as well as The metallization layer is patterned to form a character line between the first sacrificial layer and the second sacrificial layer.

2. The preparation method according to claim 1, further comprising forming a first spacer on the first sacrificial layer and forming a second spacer on the second sacrificial layer, wherein the width control structure is between the first spacer and the second spacer.

3. The preparation method according to claim 2, wherein the width control layer covers the first spacer and the second spacer.

4. The preparation method according to claim 3, wherein the width control structure does not overlap perpendicularly with the first capacitor structure.

5. The preparation method of claim 3, wherein the width control structure is separated from the first sacrificial layer via the first spacer.

6. The preparation method according to claim 3, wherein a material of the first spacer is different from a material of the width control structure.

7. The preparation method of claim 1, wherein the width control structure is configured to determine a width of the character line.

8. The preparation method according to claim 1, further comprising: Remove the first sacrificial layer and the second sacrificial layer to form a first hole and a second hole; as well as A first channel layer is formed within the first hole, and a second channel layer is formed within the second hole.

9. The preparation method of claim 2, wherein passing through the metallization layer includes removing a portion of the metallization layer exposed by the first spacer, the second spacer, and the protective layer.

10. The preparation method according to claim 9, further comprising: A lower dielectric layer is formed on the substrate, wherein the lower dielectric layer is disposed between the metallization layer and the substrate; This involves removing a portion of the lower dielectric layer that is exposed through the first spacer, the second spacer, and the protective layer.

Images