A current detection circuit and method for a fully integrated gallium nitride power chip

Abstract

The embodiment of the application provides a current detection circuit and a current detection method for a full-integrated gallium nitride power chip, and relates to the technical field of the gallium nitride power chip. In the embodiment, an on-chip voltage stabilizer (U21) is used to realize an on-chip negative voltage, and a feedback loop formed by a clamping operational amplifier (U1) and a gallium nitride detection tube is used to clamp the source potential of the gallium nitride detection tube near the source potential of the gallium nitride power tube, so that accurate current detection is realized, and the current flowing through the gallium nitride power tube can be accurately detected under the premise of low power loss, thereby solving the problems of large current detection loss and inaccurate detection by the gallium nitride detection tube. In addition, in order to deal with the serious mismatching condition that may exist in the process, an automatic zero adjustment scheme can be used to reduce the operational amplifier offset voltage. The circuit structure can be applied to a function module such as overcurrent protection and peak current control, and provides conditions for loading more intelligent gallium nitride on-chip function modules.

Description

Technical Field

[0001] This application relates to the field of gallium nitride power chip technology, and in particular to a current detection circuit and method for a fully integrated gallium nitride power chip. Background Technology

[0002] In high-power-density and high-frequency applications, gallium nitride (GaN) power devices are gradually replacing traditional silicon power devices due to their advantages of lower on-resistance and gate charge. Currently, mainstream GaN power device products on the market are mainly divided into two categories: hybrid solutions and monolithic integrated solutions, with monolithic integrated solutions also known as fully integrated solutions.

[0003] Hybrid solutions involve designing gate drive and control circuitry on a silicon-based chip for mature commercial discrete gallium nitride (GaN) power devices, and then bonding or routing the two together. The loop parasitic inductance introduced by bonding or routing can lead to serious radiated electromagnetic interference (EMI) and reliability issues. Monolithic integration solutions, on the other hand, integrate the drive and control circuitry with the power device on a single chip, effectively addressing the problems inherent in hybrid solutions.

[0004] Limited by the immaturity of gallium nitride (GaN) integration technology, most existing fully integrated GaN power chip designs are relatively simple, aiming to address process challenges such as the lack of usable p-channel devices, poor matching performance, and high threshold voltage for low-voltage HEMTs. Further optimization of on-chip GaN circuit design, the integration of more intelligent on-chip functional modules, and the achievement of accurate on-chip current sensing with low loss have become key issues.

[0005] In existing technologies, a relatively simple current sensing scheme typically involves connecting a precise resistor to the source of an off-chip power device to directly detect the device's current. This scheme is relatively accurate, but the large current flowing through the sensing resistor results in significant losses. To avoid these losses, a similar approach is to connect a sensing transistor in parallel with the power transistor, i.e., a sense HEMT, and detect the power transistor's current by sensing the current of the sense HEMT. However, if a resistor is connected in series with the source of the sense HEMT to obtain the detection voltage, the sources of the power transistor and the sensing transistor will not be completely parallel, leading to voltage distortion and inaccurate current detection from the power device. Summary of the Invention

[0006] This application introduces a current detection circuit and method for fully integrated gallium nitride (GaN) power chips. Fully integrated GaN power chips refer to integrated chips designed using GaN integrated circuit technology, distinct from traditional methods that use discrete GaN components bonded to silicon-based drives. The solution presented in this application can accurately detect the current flowing through power devices with low power loss and can be applied to the protection and control of GaN integrated circuits.

[0007] In a first aspect, embodiments of this application provide a current detection circuit for a fully integrated gallium nitride power chip, used to detect the current of a gallium nitride power transistor; the current detection circuit includes: a gallium nitride detection transistor and a negative feedback loop;

[0008] The gallium nitride power transistor and the gallium nitride detection transistor have a proportional width-to-length ratio to ensure that the gallium nitride detection transistor can proportionally replicate the current of the gallium nitride power transistor.

[0009] The negative feedback loop includes a clamping operational amplifier, a negative feedback switching transistor, and a sampling unit;

[0010] The drain of the gallium nitride (GaN) detection transistor is connected to the drain of the gallium nitride (GaN) power transistor, the gate of the GaN detection transistor is connected to the gate of the GaN power transistor, the source of the GaN detection transistor is connected to the non-inverting input of the clamping operational amplifier, the source of the GaN power transistor is connected to the inverting input of the clamping operational amplifier, the output of the clamping operational amplifier is connected to the gate of the negative feedback switch transistor, the drain of the negative feedback switch transistor is connected to the source of the GaN detection transistor, the source of the negative feedback switch transistor is connected to the first terminal of the sampling unit, and the second terminal of the sampling unit is connected to a negative voltage point. The negative voltage point is used to provide a potential lower than the source potential of the GaN power transistor to enable the negative feedback loop.

[0011] Optionally, the current detection circuit further includes a negative voltage regulator, the positive terminal of which is connected to a first power supply, and the reference terminal of which is connected to the source of the gallium nitride power transistor; the negative terminal of the negative voltage regulator is used to provide a potential lower than the potential of the reference terminal of the negative voltage regulator.

[0012] Optionally, the sampling unit includes a sampling resistor;

[0013] The source of the negative feedback switch is connected to the first terminal of the sampling resistor, and the second terminal of the sampling resistor is connected to the negative voltage point;

[0014] The first end of the sampling resistor is used as the sampling terminal output, and the sampling resistor converts the detected current into the voltage of the sampling terminal and outputs it.

[0015] Optionally, the sampling unit includes a MOS transistor, the gate of which is connected to a first voltage, the first voltage being used to make the MOS transistor operate in the linear region;

[0016] The source of the negative feedback switch is connected to the drain of the MOS transistor, the source of the MOS transistor is connected to the negative voltage point, the drain of the MOS transistor serves as the sampling terminal, and the MOS transistor converts the detected current into the voltage of the sampling terminal and outputs it.

[0017] Optionally, the current detection circuit further includes an offset voltage storage circuit;

[0018] The offset voltage storage circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a bias unit, and a capacitor;

[0019] The first end of the bias unit is connected to the second power supply, the second end of the bias unit is connected to the non-inverting input of the clamping operational amplifier and the drain of the first switching transistor, the source of the first switching transistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the inverting input of the clamping operational amplifier.

[0020] The source of the gallium nitride power transistor is indirectly connected to the inverting input of the clamping operational amplifier; the source of the second switch transistor and the source of the third switch transistor are connected to the source of the gallium nitride power transistor, and the drain of the third switch transistor is connected to the first terminal of the capacitor; the drain of the second switch transistor is connected to the second terminal of the capacitor and the inverting input of the clamping operational amplifier.

[0021] The gates of the first switch and the second switch are both connected to signals that are in phase with the control signal of the gallium nitride power transistor.

[0022] The gate of the third switch is connected to a signal that is inversely related to the control signal of the gallium nitride power transistor.

[0023] Optionally, the biasing unit includes a fourth switching transistor and a biasing resistor;

[0024] The drain of the fourth switching transistor is connected to the second power supply, the source of the fourth switching transistor is connected to the first end of the bias resistor, and the second end of the bias resistor is connected to the non-inverting input of the clamping operational amplifier and the drain of the first switching transistor.

[0025] The gates of the first switch, the fourth switch, and the second switch are all connected to signals that are in phase with the control signal of the gallium nitride power transistor.

[0026] Optionally, the first switch, the second switch, the third switch, the fourth switch, and the negative feedback switch are all enhancement-mode NMOS transistors.

[0027] Secondly, embodiments of this application provide a current detection method for a fully integrated gallium nitride power chip, applied to the current detection circuit of the fully integrated gallium nitride power chip of the first aspect, the current detection method comprising:

[0028] The same control signal is applied to the gate of the gallium nitride power transistor and the gate of the gallium nitride detection transistor;

[0029] The current of the gallium nitride power transistor is determined based on the voltage across the sampling unit.

[0030] Optionally, the current detection circuit further includes an offset voltage storage circuit;

[0031] The offset voltage storage circuit includes: a first switching transistor, a second switching transistor, a third switching transistor, a bias unit, and a capacitor;

[0032] The first end of the bias unit is connected to the second power supply, the second end of the bias unit is connected to the non-inverting input of the clamping operational amplifier and the drain of the first switching transistor, the source of the first switching transistor is connected to the first end of the capacitor, and the second end of the capacitor is connected to the inverting input of the clamping operational amplifier.

[0033] The source of the gallium nitride power transistor is indirectly connected to the inverting input of the clamping operational amplifier; the source of the second switch transistor and the source of the third switch transistor are connected to the source of the gallium nitride power transistor, and the drain of the third switch transistor is connected to the first terminal of the capacitor; the drain of the second switch transistor is connected to the second terminal of the capacitor and the inverting input of the clamping operational amplifier.

[0034] The current detection method further includes:

[0035] When the control signal is low, a high level is applied to the gate of the first switch and the gate of the second switch, and a low level is applied to the gate of the third switch, so that the capacitor stores the offset voltage at the two input terminals of the clamping operational amplifier.

[0036] When the control signal is high, a low level is applied to the gate of the first switch and the gate of the second switch, and a high level is applied to the gate of the third switch, so that the capacitor adds the stored voltage to the inverting input of the clamping operational amplifier when the gallium nitride power transistor is turned on.

[0037] Thirdly, embodiments of this application provide a fully integrated gallium nitride power chip, including the current detection circuit of the first aspect.

[0038] Compared with the prior art, this application has the following advantages:

[0039] In the current detection circuit for a fully integrated gallium nitride power chip provided in this application embodiment, the gate and drain of the gallium nitride power transistor and the gallium nitride detection transistor are connected to the same potential node. The negative feedback loop clamps the source potential of the gallium nitride detection transistor to the vicinity of the potential of the gallium nitride power transistor. That is, the gate, source, and drain of the gallium nitride detection transistor and the gallium nitride power transistor are all kept at the same potential. Therefore, the detection transistor can accurately replicate the current of the power transistor in a proportional manner, thereby achieving accurate current detection. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of a current detection circuit for a fully integrated gallium nitride power chip provided in this application embodiment;

[0042] Figure 2 for Figure 1 The sampling resistor in the diagram is replaced with a current detection circuit diagram of a MOSFET operating in the linear region;

[0043] Figure 3 A schematic diagram of a current detection circuit with offset voltage storage circuit provided for an embodiment of this application;

[0044] Figure 4 for Figure 3 A schematic diagram of the timing of node signals in the diagram;

[0045] Figure 5 for Figure 3 A schematic diagram of the offset voltage storage step in the process;

[0046] Figure 6 for Figure 3 A schematic diagram of the offset voltage discharge steps in the process;

[0047] Figure 7 for Figure 3 A schematic diagram showing the bias unit without a resistor;

[0048] Figure 8 for Figure 3 A schematic diagram omitting transistors from the bias unit;

[0049] Figure 9 A schematic diagram of an overcurrent protection circuit provided in an embodiment of this application;

[0050] Figure 10 A schematic diagram of a loop cycle-by-cycle peak current control circuit provided in this application embodiment;

[0051] Figure 11 for Figure 10 Timing diagram in BCM mode. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. The components of the embodiments of this application described in the accompanying drawings can generally be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0054] In the description of this application, it should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The term "connection" should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0055] The sources of existing detection and power transistors are not fully connected in parallel, leading to voltage distortion issues. Furthermore, most fully integrated gallium nitride power chip designs are relatively simple and lack on-chip, low-loss, precise current sensing solutions.

[0056] To achieve accurate on-chip detection of the current flowing through the gallium nitride power transistor, please refer to [link / reference]. Figure 1 This application provides a current detection circuit for a fully integrated gallium nitride (GaN) power chip (also known as a fully integrated GaN power driver chip). This current detection circuit is integrated onto the fully integrated GaN power chip using an All-GaN process. The circuit includes a GaN sensor (Sense HEMT) and a negative feedback loop. The GaN power transistor (Power HEMT) and the GaN sensor (Sense HEMT) have a proportional width-to-length ratio to ensure that the Sense HEMT can proportionally replicate the current of the Power HEMT (1 / n I in the figure). D (This is for illustrative purposes only). The negative feedback loop includes clamping operational amplifier U1, negative feedback switch M0, sampling unit U22, and negative voltage regulator U21. It has the following connections:

[0057] The drain of the gallium nitride (GaN) sensor Sense HEMT is connected to the drain of the gallium nitride power transistor Power HEMT. The gate of the GaN sensor Sense HEMT is connected to the gate of the gallium nitride power transistor Power HEMT. The source of the GaN sensor Sense HEMT is connected to the non-inverting input of clamping operational amplifier U1. The source of the gallium nitride power transistor Power HEMT is connected to the inverting input of clamping operational amplifier U1. The output of clamping operational amplifier U1 is connected to the gate of negative feedback switch M0. The drain of negative feedback switch M0 is connected to the source of the GaN sensor Sense HEMT. The source of negative feedback switch M0 is connected to the first terminal of sampling unit U22. The second terminal of sampling unit U22 is connected to the negative terminal of negative voltage regulator U21. The positive terminal of negative voltage regulator U21 is connected to the first power supply VCC. The reference terminal of negative voltage regulator U21 is connected to the source of gallium nitride power transistor Power HEMT.

[0058] The area outlined in gray in the diagram can be placed on a gallium nitride integrated chip, which refers to a monolithic chip based on GaN-on-SOI technology or other gallium nitride integration technologies. The box X in the diagram (VCC, S, D, V...) SENSE The box (X) next to a node indicates that it can be used as an external port of the chip and connected to an external PAD (interface).

[0059] The devices in the gray area of ​​the figure can also be partially set on another chip and then bonded together. For example, the gray area in the figure also includes the power drive circuit U0, which can also be set on another chip.

[0060] Next Figure 1 As an example, the working principle of this current detection circuit is introduced:

[0061] 1. The power drive circuit U0 is based on the signal source V. PWMA control signal is output to the gate of the GaN power transistor (Power HEMT) and the gate of the GaN sense transistor (Sense HEMT). This control signal has sufficient drive current to quickly turn the Power HEMT on or off. The gates and drains of the Power HEMT and Sense HEMT are connected to the same potential node and have a proportional width-to-length ratio to ensure the sense transistor can proportionally replicate the power transistor current. Clamping operational amplifier U1 controls the switching of the negative feedback switch M0 based on the voltage difference between the source of the Sense HEMT (X node) and the source of the Power HEMT (S node), forming a negative feedback loop: when the source voltage of the Sense HEMT is too high, the negative feedback switch M0 is turned on to reduce the source voltage of the Sense HEMT. The S node to X node constitutes unity-gain feedback, with the X node potential clamped near the S node potential.

[0062] 2. As can be seen from the above conditions, the gate, source, and drain of the gallium nitride power transistor (Power HEMT) and the gallium nitride sense transistor (Sense HEMT) are all kept at the same potential. Therefore, the sense transistor can accurately replicate the current of the power transistor in a proportional manner, thus achieving accurate current detection.

[0063] 3. Figure 1 In the diagram, the voltage within parentheses is the relative potential with the negative terminal of the negative voltage regulator U21 as the 0V reference potential, while the voltage outside the parentheses is the relative potential with the S node as the 0V reference potential, i.e., with the source of the gallium nitride power transistor PowerHEMT as the 0V reference potential and the S node grounded. The negative voltage regulator U21 utilizes the isolation characteristics of the GaN-on-SOI process to convert an external positive voltage into an on-chip equivalent negative voltage, ensuring the normal operation of the negative feedback switch M0, and enabling operation through the sampling resistor R. SENSE The current flowing through the detection tube is converted from current to voltage.

[0064] Figure 1 As an example, the sampling unit U11 includes a sampling resistor R. SENSE . Figure 2 An alternative implementation is provided, wherein the sampling unit U22 includes a MOS transistor, the gate of which is connected to a first voltage V. b The first voltage V b Used to make the MOSFET operate in the linear region. Similar to the sampling resistor R. SENSE The source of the negative feedback switch M0 is connected to the source of the MOS transistor, the drain of the MOS transistor is connected to the negative voltage point, and the source of the MOS transistor serves as a sampling terminal to provide voltage for detecting the current of the gallium nitride power transistor Power HEMT.

[0065] Figure 1 As an example, the negative voltage regulator U21 provides a potential lower than the source potential of the gallium nitride power transistor (Power HEMT) to enable the negative feedback loop. Alternatively, the negative voltage regulator U21 can be removed, and a negative voltage external port can be provided on the fully integrated gallium nitride power chip, with the second end of the sampling unit U22 connected to this negative voltage external port.

[0066] Figure 1 , Figure 2 In the illustrated implementation, due to defects in the fully integrated gallium nitride process, clamping operational amplifier misalignment may occur. This misalignment causes the gate-source voltage of the gallium nitride detection transistor to deviate from the expected gate-source voltage of the gallium nitride power transistor, thereby reducing the accuracy of current detection. Figure 3 This paper demonstrates an implementation method for solving the offset problem of clamped operational amplifiers. The current detection circuit also includes an offset voltage storage circuit U30. Specifically, the offset voltage storage circuit U30 may include: a first switch M1, a second switch M2, a third switch M3, and a fourth switch M4. dummy Bias resistor R dummy and capacitor C AZ .

[0067] First switch M1, second switch M2, third switch M3, fourth switch M dummy The negative feedback switch M0 can be an enhancement-mode NMOS transistor. One of the innovations of this circuit is that it is designed without PMOS, making it suitable for fully integrated gallium nitride processes.

[0068] according to Figure 3 It has the following connection relationship:

[0069] Fourth switch M dummy The drain of the transistor is connected to the second power supply VDD, and the fourth switching transistor M is connected to the second power supply VDD. dummy Source connection bias resistor R dummy The first terminal, bias resistor R dummy The second terminal is connected to the non-inverting input of the clamping operational amplifier U1 and the drain of the first switching transistor M1. The source of the first switching transistor M1 is connected to capacitor C. AZ The first terminal, capacitor C AZ The second terminal is connected to the inverting input terminal of the clamping operational amplifier U1;

[0070] The drain capacitor C of the third switching transistor M3 is connected to... AZ The first terminal, the source of the third switching transistor M3, is connected to the source of the gallium nitride power transistor Power HEMT;

[0071] The drain capacitor C of the second switching transistor M2 is connected to... AZAt the second terminal, the source of the second switching transistor M2 is connected to the source of the gallium nitride power transistor Power HEMT (in Figure 3 In this scheme, the source of the gallium nitride power transistor (Power HEMT) is indirectly connected to the inverting input of the clamping operational amplifier (U1) via the second switch M2, rather than being directly connected.

[0072] The gate of the first switch M1, the fourth switch M dummy The gates of both the first and second switching transistors M2 are connected to a signal V that is in phase with the control signal of the gallium nitride power transistor Power HEMT. AZ ;

[0073] The gate of the third switch M3 is connected to a signal V that is inversely phase to the control signal of the gallium nitride power transistor Power HEMT. SEN .

[0074] Next, according to Figures 4 to 6 This section introduces the working principle of the offset voltage storage circuit. Figure 4 This demonstrates the drive voltage V of the gallium nitride power transistor. G Signal V AZ Signal V SEN Clamping voltage V at node X CLAMP The current I of the gallium nitride power transistor D Resistance R SENSE First terminal voltage V SENSE Timing diagram:

[0075] 1. The driving voltage V of the gallium nitride power transistor G When the voltage level is low, no large current flows through the gallium nitride power transistor, V AZ High level, V SEN When the level is low, the circuit is in automatic zeroing mode, such as... Figure 5 M dummy When M1 and M2 are turned on and M3 is turned off, the offset voltage between the two input terminals of the op-amp is stored in capacitor C. AZ In the middle (as shown by the dashed arrow in the figure).

[0076] 2. The driving voltage V of the gallium nitride power transistor G When the voltage jumps to high level, both the gallium nitride detection transistor and the gallium nitride power transistor are turned on, and V AZ V is low level. SEN When the signal is high, the circuit enters the current detection state, such as... Figure 6 M dummy With M1 and M2 off and M3 on, the offset voltage stored in the previous state is inverted and applied to the op-amp input (as shown by the dashed arrow in the figure). The clamping voltage V at node X... CLAMP It is reduced to the S-node potential, which is near 0V, to compensate for the offset of the op-amp itself.

[0077] In other words, this solution utilizes the on-chip capacitor C AZ It stores and corrects potential offset voltages to address op-amp offset issues, enabling the gallium nitride (GaN) sensor to accurately replicate the GaN power transistor current I. D This enables accurate detection of current.

[0078] from Figure 1 , Figure 3 It can also be seen that the voltages of the first power supply VCC and the second power supply VDD can be different, with VDD being 5-6V, supplying power to the power drive circuit. Based on the reference terminal 0V of the negative voltage regulator, the negative voltage regulator can stabilize VCC at 16V, and VCC can supply power to the simultaneous clamping operational amplifier.

[0079] Figure 3 In the example, the fourth switch M dummy and bias resistor R dummy The fourth switching transistor M serves to provide the operating voltage. dummy and bias resistor R dummy This forms a bias unit U31. The bias unit U31 can also be implemented through other methods, such as:

[0080] 1. The bias unit U31 may have only one transistor, for example, only the fourth switching transistor M. dummy And the bias resistor R dummy Omitted, such as Figure 7 At this point, it may be necessary to use appropriate processes to give the transistor sufficient voltage resistance;

[0081] 2. The bias unit U31 can have only one bias resistor R. dummy Put the fourth switch M dummy Omitted, such as Figure 8 .

[0082] Based on the above current detection circuit, this application embodiment also provides a current detection method for a fully integrated gallium nitride power chip, applied to the above current detection circuit. This current detection method includes:

[0083] The same control signal is applied to the gate of the gallium nitride power HEMT and the gate of the gallium nitride sense HEMT;

[0084] Based on the sampling resistor R SENSE The voltage across the terminals determines the current of the gallium nitride power transistor (Power HEMT).

[0085] Furthermore, when the current detection circuit includes an offset voltage storage circuit, while applying the same control signal to the gate of the gallium nitride power transistor (Power HEMT) and the gate of the gallium nitride sense transistor (Sense HEMT) as described above, a signal is also applied to the gate of the switching transistor in the offset voltage storage circuit:

[0086] When the control signal is low, the gate of the first switch M1 and the fourth switch M dummy A high level is applied to the gate of the first and second switching transistors M2, and a low level is applied to the gate of the third switching transistor M3, so that capacitor C... AZ Store the offset voltage at the two input terminals of the clamping operational amplifier U1;

[0087] When the control signal is high, the gate of the first switch M1 and the fourth switch M... dummy A low level is applied to the gate of the first and second switching transistors M2, and a high level is applied to the gate of the third switching transistor M3, so that capacitor C... AZ When the gallium nitride power transistor Power HEMT is turned on, the stored voltage is applied to the inverting input of the clamping operational amplifier U1.

[0088] Figure 9 This paper demonstrates an implementation of the aforementioned current detection circuit in an overcurrent protection circuit. The circuit includes a blanking circuit U40, a comparator U50, a logic control module U60, and a power drive circuit U0 connected in sequence. These components can be integrated with the current detection circuit onto a single chip. Its working principle is as follows:

[0089] Using R in the current detection circuit SENSE Obtain current detection voltage V SENSE After the blanking circuit U40 removes the glitches, the voltage is compared with the on-chip reference voltage V. REF The comparison is performed using comparator U50. When V SENSE More than V REF When V indicates that the current of the gallium nitride power transistor (GaN power transistor) exceeds the preset value, comparator U50 outputs an enable signal, which controls the power drive circuit U0 through logic module U40, causing the power drive circuit U0 to output a low level, thus stopping the GaN power transistor from working. SENSE Normal means not exceeding V REF At that time, the circuit is in normal working condition.

[0090] Figure 10 This paper demonstrates an implementation of the aforementioned current sensing circuit in a loop cycle-by-cycle peak current control circuit. The circuit includes a blanking circuit U40, a comparator U50, a latch U60, and a power drive circuit U0 connected in sequence. These components can be integrated with the current sensing circuit onto a single chip. The working principle is as follows:

[0091] The collected voltage V SENSE After the glitch is removed by the blanking circuit U40, it is compared with the reference voltage V by the comparator U50. REF The comparison shows that the output voltage of the blanking circuit is greater than V. REF At this time, the comparator U50 output triggers the falling edge of the latch output Q, thereby adjusting the pulse width. The rising edge of the latch output Q is provided by a fixed clock CLK, such as... Figure 11 As shown. The voltage V output at the latch output terminal Q. Q Used as a PWM signal, it is provided to the power drive circuit U0, ultimately determining the on-time of the gallium nitride power transistor (PowerHEMT) in each cycle. This embodiment utilizes the aspect ratio of the on-chip gallium nitride power transistor to the gallium nitride detection transistor, and R... SENSE The resistance value and the externally set reference voltage limit the peak inductor current to a fixed value. Specifically, when the BUCK topology operates in BCM (Boundary Conduction Mode), the output current I... LOAD It is equal to half of the peak inductor current.

[0092] Based on the current detection circuit described above, this application embodiment also provides a fully integrated gallium nitride power chip, which may include any of the above-described current detection circuits, overcurrent protection circuits, or loop cycle-by-cycle peak current control circuits.

[0093] In summary, this application provides a current detection circuit for fully integrated gallium nitride (GaN) power chips. It utilizes an on-chip negative voltage regulator to achieve on-chip negative voltage, which powers a clamping operational amplifier (op-amp). A feedback loop formed by the clamping op-amp and the GaN sensor clamps the source potential of the GaN sensor near the source potential of the GaN power chip, thus achieving accurate current detection. Simultaneously, it accurately detects the current flowing through the GaN power chip with low power loss, solving the problems of high current detection loss and inaccurate detection using GaN sensors. Furthermore, to address potential severe process mismatches, an automatic zero-adjustment scheme is employed to reduce op-amp offset voltage. This circuit structure can be applied to various power chip circuit modules requiring current detection, such as overcurrent protection and peak current control modules, facilitating the integration of more intelligent on-chip GaN functional modules.

[0094] The apparatus and system embodiments described above are merely illustrative. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement these embodiments without any creative effort.

[0095] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A current detection circuit for a fully integrated gallium nitride power chip, used to detect the current of a gallium nitride power transistor (PowerHEMT); characterized in that, The current detection circuit is integrated on a fully integrated gallium nitride power chip using a fully integrated gallium nitride process. The current detection circuit includes a gallium nitride sensor (Sense HEMT) and a negative feedback loop. The gallium nitride power transistor (Power HEMT) and the gallium nitride sense transistor (Sense HEMT) have a proportional width-to-length ratio to ensure that the gallium nitride sense transistor (Sense HEMT) can proportionally replicate the current of the gallium nitride power transistor (Power HEMT). The negative feedback loop includes a clamping operational amplifier (U1), a negative feedback switch (M0), and a sampling unit (U22). The drain of the gallium nitride (GaN) sensor (Sense HEMT) is connected to the drain of the gallium nitride (GaN) power transistor (Power HEMT), and the gate of the GaN sensor (Sense HEMT) is connected to the gate of the GaN power transistor (Power HEMT). The source of the GaN sensor (Sense HEMT) is connected to the non-inverting input of the clamping operational amplifier (U1), and the source of the GaN power transistor (Power HEMT) is connected to the inverting input of the clamping operational amplifier (U1). The output of the clamping operational amplifier (U1) is connected to the gate of the negative feedback switch (M0), and the drain of the negative feedback switch (M0) is connected to the source of the GaN sensor (Sense HEMT). The source of the negative feedback switch (M0) is connected to the first terminal of the sampling unit (U22), and the second terminal of the sampling unit (U22) is connected to a negative voltage point. The negative voltage point is used to provide a voltage lower than that of the GaN power transistor (Power HEMT). The potential of the HEMT source electrode potential is used to turn on the negative feedback loop; The current detection circuit also includes an offset voltage storage circuit (U30). The offset voltage storage circuit (U30) includes: a first switch (M1), a second switch (M2), a third switch (M3), a bias unit (U31), and a capacitor (CAZ); The first terminal of the bias unit (U31) is connected to the second power supply (VDD), the second terminal of the bias unit (U31) is connected to the non-inverting input terminal of the clamping operational amplifier (U1) and the drain of the first switching transistor (M1), the source of the first switching transistor (M1) is connected to the first terminal of the capacitor (CAZ), and the second terminal of the capacitor (CAZ) is connected to the inverting input terminal of the clamping operational amplifier (U1). The source of the gallium nitride power transistor (Power HEMT) is indirectly connected to the inverting input of the clamping operational amplifier (U1); the sources of the second switch transistor (M2) and the third switch transistor (M3) are connected to the source of the gallium nitride power transistor (Power HEMT), and the drain of the third switch transistor (M3) is connected to the first terminal of the capacitor (CAZ); the drain of the second switch transistor (M2) is connected to the second terminal of the capacitor (CAZ) and the inverting input of the clamping operational amplifier (U1). The gates of the first switch (M1) and the second switch (M2) are both connected to signals that are in phase with the control signal of the gallium nitride power transistor (Power HEMT); The gate of the third switch (M3) is connected to a signal that is inversely related to the control signal of the gallium nitride power transistor (Power HEMT).

2. The current detection circuit as described in claim 1, characterized in that, The current detection circuit also includes a negative voltage regulator (U21), the positive terminal of which is connected to a first power supply (VCC), and the reference terminal of which is connected to the source of the gallium nitride power transistor (Power HEMT); the negative terminal of the negative voltage regulator (U21) is used to provide a potential lower than the reference terminal potential of the negative voltage regulator (U21).

3. The current detection circuit as described in claim 1, characterized in that, The sampling unit (U22) includes a sampling resistor (R). SENSE ); The source of the negative feedback switch (M0) is connected to the sampling resistor (R). SENSE The first terminal of the sampling resistor (R) SENSE The second end of the device is connected to the negative pressure point; The sampling resistor (R) SENSE The first terminal of the sampling resistor (R) is output as the sampling terminal. SENSE The detected current is converted into a voltage at the sampling terminal and output.

4. The current detection circuit as described in claim 1, characterized in that, The sampling unit (U22) includes a MOS transistor, the gate of which is connected to a first voltage (V). b The first voltage is used to make the MOS transistor operate in the linear region; The source of the negative feedback switch (M0) is connected to the drain of the MOS transistor, the source of the MOS transistor is connected to the negative voltage point, the drain of the MOS transistor serves as the sampling terminal, and the MOS transistor converts the detected current into the voltage of the sampling terminal and outputs it.

5. The current detection circuit as described in claim 1, characterized in that, The bias unit (U31) includes a fourth switch (M). dummy ) and bias resistor (R dummy ); The fourth switch (M) dummy The drain of the fourth switching transistor (M) is connected to the second power supply (VDD). dummy The source of the bias resistor (R) is connected to the bias resistor. dummy The first terminal of the bias resistor (R) dummy The second end of the clamping operational amplifier (U1) is connected to the non-inverting input terminal of the clamping operational amplifier (U1) and the drain of the first switching transistor (M1); The gate of the first switch (M1), the fourth switch (M dummy The gates of the first and second switching transistors (M2) are both connected to signals that are in phase with the control signal of the gallium nitride power transistor (Power HEMT).

6. The current detection circuit as described in claim 5, characterized in that, The first switch (M1), the second switch (M2), the third switch (M3), and the fourth switch (M4) dummy Both the negative feedback switch (M0) and the negative feedback switch are enhancement-mode NMOS transistors.

7. A current detection method for a fully integrated gallium nitride power chip, characterized in that, The current detection circuit applied to the fully integrated gallium nitride power chip according to any one of claims 1 to 6, wherein the current detection method includes: The same control signal is applied to the gate of the gallium nitride power transistor (Power HEMT) and the gate of the gallium nitride sense HEMT; The current of the gallium nitride power transistor (Power HEMT) is determined based on the voltage across the sampling unit (U22).

8. The current detection method as described in claim 7, characterized in that, The current detection circuit also includes an offset voltage storage circuit (U30). The offset voltage storage circuit (U30) includes: a first switching transistor (M1), a second switching transistor (M2), a third switching transistor (M3), a bias unit (U31), and a capacitor (C). AZ ); The first terminal of the bias unit (U31) is connected to the second power supply (VDD), and the second terminal of the bias unit (U31) is connected to the non-inverting input terminal of the clamping operational amplifier (U1) and the drain of the first switching transistor (M1). The source of the first switching transistor (M1) is connected to the capacitor (C). AZ The first terminal of the capacitor (C) AZ The second terminal of the clamping operational amplifier (U1) is connected to the inverting input terminal of the clamping operational amplifier (U1); The source of the gallium nitride power transistor (Power HEMT) is indirectly connected to the inverting input of the clamping operational amplifier (U1); the sources of the second switch (M2) and the third switch (M3) are connected to the source of the gallium nitride power transistor (Power HEMT), and the drain of the third switch (M3) is connected to the capacitor (C). AZ The first terminal of the second switching transistor (M2) is connected to the drain of the capacitor (C). AZ The second terminal of the clamping operational amplifier (U1) and the inverting input terminal of the clamping operational amplifier (U1); The current detection method further includes: When the control signal is low, a high level is applied to the gate of the first switch (M1) and the gate of the second switch (M2), and a low level is applied to the gate of the third switch (M3), so that the capacitor (C) AZ The offset voltages at the two input terminals of the clamping operational amplifier (U1) are stored. When the control signal is high, a low level is applied to the gate of the first switch (M1) and the gate of the second switch (M2), and a high level is applied to the gate of the third switch (M3), so that the capacitor (C) AZ When the gallium nitride power transistor (Power HEMT) is turned on, the stored voltage is applied to the inverting input of the clamping operational amplifier (U1).

9. A fully integrated gallium nitride power chip, characterized in that, The current detection circuit includes any one of claims 1 to 6.

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