A data processing method, device, system, electronic device, and storage medium

Abstract

The application relates to the technical field of computers and discloses a data processing method, device and system, electronic equipment and a storage medium, the method comprising the following steps: acquiring a plurality of pieces of mapping data to be written into an incremental buffer area; performing data compression on the mapping data according to continuous information of physical block addresses represented by the plurality of pieces of mapping data, to obtain compressed mapping data; and writing the compressed mapping data into the incremental buffer area. The method provided by the above scheme can improve the use efficiency of the incremental buffer area, reduce the number of times of flushing the mapping data, and improve the performance of an SSD by performing data compression on the mapping data before writing the mapping data into the incremental buffer area and finally writing the compressed mapping data into the incremental buffer area.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, system, electronic device, and storage medium. Background Technology

[0002] With the emergence and widespread use of NAND flash memory, solid-state drives (SSDs) based on NAND flash memory have become a hot topic in the storage field due to their higher reliability, better performance, and lower power consumption. SSDs typically use an L2P mapping table to construct the mapping relationship between the host's logical block address (LBA) and the SSD's physical block address (PBA). Therefore, how the L2P mapping table data is handled directly affects SSD performance.

[0003] In existing technologies, the mapping table is usually divided into several parts and stored in a base buffer and an increment buffer. When the increment buffer is full, an increment buffer and a base buffer are merged and stored on the NAND.

[0004] However, due to the limited capacity of the incremental buffer, frequently flushing the mapped data to the NAND during SSD operation will reduce the performance of the SSD and is also detrimental to ensuring the lifespan of the NAND of the SSD. Summary of the Invention

[0005] This application provides a data processing method, apparatus, system, electronic device, and storage medium to address the shortcomings of existing technologies, such as reduced SSD performance.

[0006] The first aspect of this application provides a data processing method, including:

[0007] Retrieve several mapping data entries to be written to the incremental buffer;

[0008] Based on the continuous physical block address information represented by the several mapping data, the mapping data is compressed to obtain compressed mapping data.

[0009] The compressed mapping data is written into the incremental buffer.

[0010] Optionally, the mapping data includes a one-to-one correspondence of logical block addresses, old physical block addresses, and new physical block addresses. The step of compressing the mapping data based on the continuous physical block address information represented by the plurality of mapping data to obtain compressed mapping data includes:

[0011] The mapping data is split into first mapping data and second mapping data; wherein, the first mapping data includes a one-to-one logical block address and an old physical block address, and the second mapping data includes a one-to-one logical block address and a new physical block address;

[0012] Based on the continuity information of the old physical block address represented by the first mapping data, the first mapping data is split into several segments of first sub-data.

[0013] For any of the first sub-data, generate the first compressed sub-data corresponding to the first sub-data based on the length of the first sub-data, the starting logical block address, and the first starting sub-data of the first sub-data;

[0014] Merge the first compressed sub-data corresponding to each of the first sub-data to obtain the first compressed data corresponding to the first mapped data;

[0015] Based on the contiguous information of the new physical block address represented by the second mapping data, the second mapping data is split into several segments of second sub-data;

[0016] For any second sub-data, generate the second compressed sub-data corresponding to the second sub-data based on the length of the second sub-data, the starting logical block address, and the first starting sub-data of the first sub-data;

[0017] Merge the second compressed sub-data corresponding to each of the second sub-data to obtain the second compressed data corresponding to the second mapped data;

[0018] The first compressed data and the second compressed data are merged to obtain the compressed mapping data.

[0019] Optionally, the first mapping data includes a sequence number, and the step of splitting the first mapping data into several segments of first sub-data based on the continuity information of the old physical block addresses represented by the first mapping data includes:

[0020] Traverse the data in the first mapping data from front to back, and take the first data in the first mapping data as the first starting sub-data;

[0021] If the difference in old physical block address between the traversed data and the first starting sub-data is equal to the difference in their sequence numbers, then the data is determined to be continuous data with the old physical block address with the first starting sub-data.

[0022] When traversing to data whose old physical block address difference with the first starting data is not equal to the sequence number difference between the two, this data is used as the new first starting sub-data.

[0023] According to each of the first starting sub-data, the first mapping data is divided into several segments of first sub-data;

[0024] In each of the first sub-data, the data consists of continuous old physical block addresses.

[0025] Optionally, the second mapping data includes a sequence number, and the step of splitting the second mapping data into several segments of second sub-data based on the new physical block address continuation information represented by the second mapping data includes:

[0026] Traverse the data in the second mapping data from front to back, and take the first data in the second mapping data as the second starting sub-data;

[0027] If the difference between the new physical block address of the traversed data and the second starting sub-data is equal to the difference in their sequence numbers, then the data and the second starting sub-data are determined to be consecutive data with new physical block addresses.

[0028] When traversing to data whose new physical block address difference with the second starting data is not equal to the sequence number difference between the two, this data is taken as the new second starting sub-data.

[0029] According to each of the second starting sub-data, the second mapping data is split into several segments of second sub-data;

[0030] Each of the second sub-data items contains consecutive data of the new physical block address.

[0031] Optionally, the compressed mapping data includes at least the starting logical block address, length, starting sub-data, and sub-data type corresponding to each sub-data.

[0032] Optionally, the method further includes:

[0033] When the data storage volume of the incremental buffer reaches a preset threshold, the compressed mapping data is extracted from the incremental buffer.

[0034] Extract the base quantity data from the base quantity buffer;

[0035] The compressed mapping data is merged with the base data to obtain merged mapping data.

[0036] The merged mapping data is saved to the flash memory of the solid-state drive.

[0037] A second aspect of this application provides a data processing apparatus, comprising:

[0038] The acquisition module is used to acquire several pieces of mapping data to be written to the incremental buffer;

[0039] The compression module is used to compress the mapping data according to the continuous physical block address information represented by the several mapping data to obtain compressed mapping data.

[0040] The processing module is used to write the compressed mapping data into the incremental buffer.

[0041] A third aspect of this application provides a data processing system, comprising:

[0042] Random access memory and flash conversion layer controller, wherein the random access memory includes several incremental buffers and base buffers;

[0043] The flash memory conversion layer controller uses the data processing method described in the first aspect and various possible designs of the first aspect to process the mapped data to be written to the incremental buffer.

[0044] A fourth aspect of this application provides an electronic device, comprising: at least one processor and a memory;

[0045] The memory stores computer-executed instructions;

[0046] The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method described in the first aspect above and various possible designs of the first aspect.

[0047] The fifth aspect of this application provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, implement the method described in the first aspect above and various possible designs of the first aspect.

[0048] The technical solution of this application has the following advantages:

[0049] This application provides a data processing method, apparatus, system, electronic device, and storage medium. The method includes: acquiring several pieces of mapping data to be written to an incremental buffer; compressing the mapping data based on the physical block address contiguous information represented by the several pieces of mapping data to obtain compressed mapping data; and writing the compressed mapping data into the incremental buffer. The method provided above improves the efficiency of the incremental buffer and reduces the number of times the mapping data is flushed, thereby improving the performance of the SSD, by compressing the mapping data before writing it into the incremental buffer and finally writing the compressed mapping data into the incremental buffer. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0051] Figure 1 A schematic diagram of the basic quantity buffer structure provided for the implementation of this application;

[0052] Figure 2 A schematic diagram of the incremental buffer structure provided for the implementation of this application;

[0053] Figure 3 A schematic diagram of the structure of the merged mapping data provided for the implementation of this application;

[0054] Figure 4 This is a schematic diagram of the incremental data structure provided in an embodiment of this application;

[0055] Figure 5 A flowchart illustrating the data processing method provided in an embodiment of this application;

[0056] Figure 6 A schematic diagram of the structure of the compressed sub-data provided for the implementation of this application;

[0057] Figure 7 This is a schematic diagram of the code execution flow of the data processing method provided in the embodiments of this application;

[0058] Figure 8 This is a schematic diagram of the structure of the data processing apparatus provided in the embodiments of this application;

[0059] Figure 9 This is a schematic diagram of the structure of the data processing system provided in the embodiments of this application;

[0060] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0061] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0063] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. In the following descriptions of embodiments, "a plurality of" means two or more, unless otherwise explicitly defined.

[0064] In existing technologies, SSD systems use an L2P table to establish a mapping relationship between the host's LBA and the SSD's PBA, and the FTL controller updates and maintains this mapping relationship to enable the host to perform read, write, and erase functions on the NAND flash memory. Typically, the size of the L2P mapping table is about one-thousandth of the SSD's capacity; for example, a 1TB SSD's L2P mapping table is approximately 1GB. Given the large capacity of the mapping table, it cannot be stored as a single copy. Instead, the mapping table is divided into several parts and stored in RAM in a base buffer of equal length, and an increment buffer of equal length is allocated in RAM. For example... Figure 1 The diagram shown is a schematic of the basic quantity buffer structure provided in this application. Figure 2 The diagram shown illustrates the incremental buffer structure provided in this application. The base buffer stores the PBA corresponding to each LBA, with LBA_0 being the PBA corresponding to LBA=0 and LBA_1 being the PBA corresponding to LBA=1. The delta buffer stores the delta entries, with Delta_0, Delta_1, etc., being the delta entries. When a new mapping relationship is generated, in addition to updating the base buffer with the new L2P mapping relationship, it is also saved to the delta buffer. When a delta buffer is full, header information is added to the delta buffer data, and then a base buffer is merged to obtain the merged mapping data. The merged mapping data is then written to the NAND flash. For example... Figure 3 The diagram shown is a schematic representation of the structure of the merged mapping data provided in this application. The header information includes the characteristic information of the merged base buffer and increment buffer.

[0065] Typically, the increment of a mapping needs to save information including the original mapping relationship and the new mapping relationship. Common storage structures include... Figure 4 As shown, this includes LBA, Old PBA, and New PBA. Figure 4 The schematic diagram of the incremental data structure provided in this application embodiment represents a mapping relationship in a 4KB space on the host. Each entry occupies 12 bytes. Using this structure to store incremental data, a 10KB Delta Buffer can store a maximum of 853 Delta Entry A's, representing a 3412KB mapping relationship. This representation is simple and direct, but for enterprise-level SSD systems, large-scale and frequent data writes will generate a large amount of incremental information, burdening the data cache and affecting NAND performance. The space occupancy of each structure in the incremental data Delta Entry A is shown in the table below:

[0066]

[0067] To address the aforementioned issues, this application provides a data processing method comprising: acquiring several pieces of mapping data to be written to an incremental buffer; compressing the mapping data based on the physical block address continuation information represented by the several pieces of mapping data to obtain compressed mapping data; and writing the compressed mapping data into the incremental buffer. The method provided above improves the efficiency of the incremental buffer and reduces the number of times the mapping data is flushed, thereby improving SSD performance, by compressing the mapping data before writing it into the incremental buffer and finally writing the compressed mapping data into the incremental buffer.

[0068] The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0069] This application provides a data processing method for compressing mapped data to be written to an incremental buffer. The execution subject of this application is an electronic device, such as a server, desktop computer, laptop computer, tablet computer, or other electronic device that can be used to compress mapped data to be written to an incremental buffer.

[0070] like Figure 5 The diagram shown is a flowchart illustrating a data processing method provided in an embodiment of this application. The method includes:

[0071] Step 501: Obtain several mapping data entries to be written to the incremental buffer.

[0072] Specifically, based on a preset data acquisition device, several mapping data entries to be written to the incremental buffer by the host can be acquired.

[0073] Step 502: Based on the continuous information of physical block addresses represented by several mapping data, the mapping data is compressed to obtain compressed mapping data.

[0074] It should be noted that, based on the characteristics of host data writing and NAND storage space allocation, the LBA, Old PBA, and New PBA in the new mapping relationship are likely to be consecutive. Therefore, based on the continuous physical block address information represented by the currently obtained mapping data, corresponding data compression operations can be performed on these mapping data to obtain compressed mapping data.

[0075] Step 503: Write the compressed mapping data into the incremental buffer.

[0076] The compressed mapping data will be much smaller than the original mapping data to be written to the incremental buffer. Therefore, writing the compressed mapping data into the incremental buffer reduces the space occupied by the mapping data in the incremental buffer and improves the efficiency of the incremental buffer.

[0077] Furthermore, in one embodiment, when the data storage volume of the incremental buffer reaches a preset threshold, compressed mapping data is extracted from the incremental buffer; base data is extracted from the base buffer; the compressed mapping data and the base data are merged to obtain merged mapping data; and the merged mapping data is saved to the flash memory of the solid-state drive.

[0078] The preset threshold can be set according to the capacity of the incremental buffer. When the data storage of the incremental buffer reaches the preset threshold, it is determined that the incremental buffer is full. Then, the compressed mapping data is extracted from the incremental buffer, and then a base buffer is selected. The compressed mapping data stored in the incremental buffer is merged with the base data stored in the base buffer to obtain the merged mapping data. Finally, the merged mapping data is saved to the NAND flash memory of the solid-state drive through the communication interface between the incremental buffer and the base buffer.

[0079] Specifically, in one embodiment, when the data storage volume of the incremental buffer reaches a preset threshold, the compressed mapping data currently stored in the incremental buffer can be compressed a second time to further release the storage space of the incremental buffer, thereby improving the utilization rate of the incremental buffer.

[0080] Based on the above embodiments, the mapping data includes a one-to-one logical block address, an old physical block address, and a new physical block address. To improve the compression efficiency of cached data and achieve maximum data compression while ensuring data validity, as an implementable approach, in one embodiment, the mapping data is compressed according to the continuous physical block address information represented by several mapping data entries to obtain compressed mapping data, including:

[0081] Step 5021: Split the mapping data into first mapping data and second mapping data; wherein, the first mapping data includes a one-to-one logical block address and an old physical block address, and the second mapping data includes a one-to-one logical block address and a new physical block address.

[0082] Step 5022: Based on the continuity information of the old physical block address represented by the first mapping data, the first mapping data is split into several segments of first sub-data.

[0083] Step 5023: For any first sub-data, generate the first compressed sub-data corresponding to the first sub-data according to the length of the first sub-data, the starting logical block address and the first starting sub-data of the first sub-data;

[0084] Step 5024: Merge the first compressed sub-data corresponding to each first sub-data to obtain the first compressed data corresponding to the first mapped data;

[0085] Step 5025: Based on the continuous information of the new physical block address represented by the second mapping data, the second mapping data is split into several segments of second sub-data.

[0086] Step 5026: For any second sub-data, generate the second compressed sub-data corresponding to the second sub-data based on the length of the second sub-data, the starting logical block address and the first starting sub-data of the first sub-data;

[0087] Step 5027: Merge the second compressed sub-data corresponding to each second sub-data to obtain the second compressed data corresponding to the second mapping data;

[0088] Step 5028: Merge the first compressed data and the second compressed data to obtain the compressed mapping data.

[0089] Among them, such as Figure 6 The diagram shown is a schematic representation of the structure of the compressed sub-data provided in this application. The compressed mapping data includes at least the starting logical block address, length, starting sub-data, and sub-data type corresponding to each sub-data. One compressed sub-data occupies 12 bytes. The space occupancy of each structure in the compressed sub-data obtained after data compression of the incremental data Delta Entry A is shown in the table below:

[0090]

[0091] Specifically, in one embodiment, the first mapping data includes a sequence number. The data in the first mapping data can be traversed from front to back, and the first data in the first mapping data is taken as the first starting sub-data. If the old physical block address difference between the traversed data and the first starting sub-data is equal to the sequence number difference between them, then the data and the first starting sub-data are determined to be continuous data with the old physical block address. When the data traversed is not equal to the sequence number difference between the old physical block address and the first starting data, the data is taken as the new first starting sub-data. The first mapping data is split into several segments of first sub-data according to each first starting sub-data.

[0092] Each of the first sub-data items contains continuous data of old physical block addresses.

[0093] Similarly, in one embodiment, the second mapping data includes a sequence number. The data in the second mapping data is traversed from front to back, and the first data in the second mapping data is taken as the second starting sub-data. If the difference in the new physical block address between the traversed data and the second starting sub-data is equal to the difference in their sequence numbers, then the data and the second starting sub-data are determined to be continuous data with the new physical block address. When the difference in the new physical block address between the traversed data and the second starting data is not equal to the difference in their sequence numbers, the data is taken as the new second starting sub-data. The second mapping data is split into several segments of second sub-data according to each second starting sub-data.

[0094] Each of the second sub-data items contains consecutive data of the new physical block address.

[0095] For example, as shown in the table below, there are 20 mapping data entries to be written to the incremental buffer provided in this application embodiment, numbered 1 to 20.

[0096]

[0097]

[0098] Furthermore, the above 20 mapping data entries are further divided into the following first mapping data and second mapping data:

[0099]

[0100] Specifically, in the first mapping data, 1-6 constitute a first sub-data set with a length of 6, a starting logical block address of 0x161bf6, and a first starting sub-data set of 0x4a84ca. 7-20 constitute another first sub-data set with a length of 14, a starting logical block address of 0x161bfc, and a first starting sub-data set of 0x4a86b0. In the second mapping data, 1-16 constitute a second sub-data set with a length of 16, a starting logical block address of 0x161bf6, and a second starting sub-data set of 0x509220. 17-20 constitute another second sub-data set with a length of 4, a starting logical block address of 0x161c07, and a second starting sub-data set of 0x509410. The structure of the compressed mapping data obtained after compressing these 20 mapping data sets is shown in the table below:

[0101] 1 0x161bf6 0 16 0x509220 2 0x161c07 0 4 0x509410 3 0x161bf6 1 6 0x4a84ca 4 0x161bfc 1 14 0x4a86b0

[0102] In this context, Start LBA represents the starting logical block address, Start PBA represents the starting sub-data (first starting sub-data or second starting sub-data), and the type is used to characterize whether it is the first sub-data or the second sub-data. The first sub-data (OldPBA) is represented as 1, and the second sub-data (New PBA) is represented as 0. If these 20 mapping data entries were directly stored in the incremental buffer using traditional techniques, they would occupy 12 * 20 = 240 bytes. However, using the method provided in this application, storing the incremental data only occupies 12 * 4 = 48 bytes, greatly improving the efficiency of the incremental buffer.

[0103] To facilitate the reproduction of the data processing methods provided in the embodiments of this application by those skilled in the art, such as Figure 7 The diagram shows the code execution flow of the data processing method provided in this application embodiment. Here, `pba_in` is the input list of PBAs (mapping data) that needs to be segmented and compressed, `list_long` is the length of the PBA list (e.g., the list length is 20 as described above), and `Index` records the position of the starting PBA in the list for each consecutive PBA segment (the sequence number corresponding to the starting sub-data). Taking the above 20 mapping data as an example, when the input `pba_in` is the Old PBA column (first sub-data) and `list_long` is 20, the output `Index` = {4, 16}; when the input `pba_in` is the New PBA column (second sub-data) and `list_long` is 20, the output `Index` = {16, 4}, and so on. Figure 7 The process shown is as follows Figure 5 The illustrated process is an exemplary implementation, and the two implementations are based on the same principle, so they will not be described again.

[0104] The data processing method provided in this application involves acquiring several mapping data entries to be written to the incremental buffer; compressing the mapping data based on the continuous physical block address information represented by the several mapping data entries to obtain compressed mapping data; and writing the compressed mapping data into the incremental buffer. The method provided above improves the efficiency of the incremental buffer by compressing the mapping data before writing it into the incremental buffer and reducing the number of times the mapping data is flushed, thereby improving SSD performance. By representing the continuous L2P incremental mapping relationship using a starting address and length, the utilization rate of the incremental buffer is improved. This reduces the space occupied by the incremental buffer in RAM and the frequency of L2P mapping table flushing to NAND during system operation, minimizing the impact on write performance and extending the lifespan of NAND.

[0105] This application provides a data processing apparatus for executing the data processing method provided in the above embodiments.

[0106] like Figure 8 The diagram shown is a structural schematic of a data processing apparatus provided in an embodiment of this application. The data processing apparatus 80 includes: an acquisition module 801, a compression module 802, and a processing module 803.

[0107] The module includes an acquisition module for acquiring several mapping data entries to be written to the incremental buffer; a compression module for compressing the mapping data based on the continuous physical block address information represented by the several mapping data entries to obtain compressed mapping data; and a processing module for writing the compressed mapping data into the incremental buffer.

[0108] Regarding the data processing apparatus in this embodiment, the specific manner in which each module performs its operations has been described in detail in the embodiments related to the method, and will not be elaborated upon here.

[0109] The data processing apparatus provided in this application embodiment is used to execute the data processing method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0110] This application provides a data processing system for executing the data processing method provided in the above embodiments.

[0111] like Figure 9 The diagram shown is a schematic representation of the data processing system provided in an embodiment of this application. The data processing system includes: random access memory (RAM) and a flash translation layer controller (FTL controller). The random access memory includes several incremental buffers and a base buffer.

[0112] The flash memory conversion layer controller uses the data processing method provided in the above embodiments to process the mapped data to be written to the incremental buffer.

[0113] Specifically, the host device sends several mapping data entries to be written to the incremental buffer to the flash conversion layer controller via an interface. After receiving the mapping data from the flash conversion layer controller, the host device first compresses the data based on the data processing method provided in the above embodiment. Finally, the compressed mapping data is saved to the incremental buffer. When the data storage volume of the incremental buffer reaches a preset threshold, the flash conversion layer controller extracts the compressed mapping data from the incremental buffer and extracts the base data from the base buffer. The compressed mapping data and the base data are then merged to obtain the merged mapping data. Finally, the merged mapping data is saved to the NAND flash memory of the solid-state drive via an interface.

[0114] The data processing system provided in this application embodiment is used to execute the data processing method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0115] This application provides an electronic device for executing the data processing method provided in the above embodiments.

[0116] like Figure 10 The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. The electronic device 100 includes at least one processor 1001 and a memory 1002.

[0117] The memory stores computer-executable instructions; at least one processor executes the computer-executable instructions stored in the memory, causing the at least one processor to perform the data processing method provided in the above embodiments.

[0118] The electronic device provided in this application embodiment is used to execute the data processing method provided in the above embodiment. Its implementation method and principle are the same, and will not be described again.

[0119] This application provides a computer-readable storage medium storing computer-executable instructions. When a processor executes the computer-executable instructions, it implements the data processing method provided in any of the above embodiments.

[0120] The storage medium containing computer-executable instructions provided in this application embodiment can be used to store computer-executable instructions for the data processing method provided in the foregoing embodiments. Its implementation method and principle are the same, and will not be described again.

[0121] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0122] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units.

[0124] The integrated units implemented as software functional units described above can be stored in a computer-readable storage medium. These software functional units, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute some steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0126] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data processing method, characterized in that, include: Retrieve several mapping data entries to be written to the incremental buffer; Based on the continuous physical block address information represented by the several mapping data, the mapping data is compressed to obtain compressed mapping data. Write the compressed mapping data into the incremental buffer; The mapping data includes a one-to-one correspondence of logical block addresses, old physical block addresses, and new physical block addresses. The step of compressing the mapping data based on the continuous physical block address information represented by the plurality of mapping data to obtain compressed mapping data includes: The mapping data is split into first mapping data and second mapping data; wherein, the first mapping data includes a one-to-one logical block address and an old physical block address, and the second mapping data includes a one-to-one logical block address and a new physical block address; Based on the continuity information of the old physical block address represented by the first mapping data, the first mapping data is split into several segments of first sub-data. For any of the first sub-data, generate the first compressed sub-data corresponding to the first sub-data based on the length of the first sub-data, the starting logical block address, and the first starting sub-data of the first sub-data; Merge the first compressed sub-data corresponding to each of the first sub-data to obtain the first compressed data corresponding to the first mapped data; Based on the continuous information of the new physical block address represented by the second mapping data, the second mapping data is split into several segments of second sub-data; For any second sub-data, generate the second compressed sub-data corresponding to the second sub-data based on the length of the second sub-data, the starting logical block address, and the first starting sub-data of the first sub-data; Merge the second compressed sub-data corresponding to each of the second sub-data to obtain the second compressed data corresponding to the second mapped data; The first compressed data and the second compressed data are merged to obtain the compressed mapping data.

2. The method according to claim 1, characterized in that, The first mapping data includes a sequence number. The step of splitting the first mapping data into several segments of first sub-data based on the continuity information of the old physical block addresses represented by the first mapping data includes: Traverse the data in the first mapping data from front to back, and take the first data in the first mapping data as the first starting sub-data; If the difference in old physical block address between the traversed data and the first starting sub-data is equal to the difference in their sequence numbers, then the data is determined to be continuous data with the old physical block address with the first starting sub-data. When traversing to data whose old physical block address difference with the first starting sub-data is not equal to the sequence number difference between the two, the data is taken as the new first starting sub-data. According to each of the first starting sub-data, the first mapping data is divided into several segments of first sub-data; In each of the first sub-data, the data consists of continuous old physical block addresses.

3. The method according to claim 1, characterized in that, The second mapping data includes a sequence number. Based on the continuous information of the new physical block address represented by the second mapping data, the second mapping data is divided into several segments of second sub-data, including: Traverse the data in the second mapping data from front to back, and take the first data in the second mapping data as the second starting sub-data; If the difference between the new physical block address of the traversed data and the second starting sub-data is equal to the difference in their sequence numbers, then the data and the second starting sub-data are determined to be consecutive data with new physical block addresses. When traversing to a data whose new physical block address difference with the second starting sub-data is not equal to the sequence number difference between the two, the data is taken as the new second starting sub-data. According to each of the second starting sub-data, the second mapping data is split into several segments of second sub-data; Each of the second sub-data items contains consecutive data of the new physical block address.

4. The method according to claim 1, characterized in that, The compressed mapping data includes at least the starting logical block address, length, starting sub-data, and sub-data type corresponding to each sub-data.

5. The method according to claim 1, characterized in that, The method further includes: When the data storage volume of the incremental buffer reaches a preset threshold, the compressed mapping data is extracted from the incremental buffer. Extract the base quantity data from the base quantity buffer; The compressed mapping data is merged with the base data to obtain merged mapping data. The merged mapping data is saved to the flash memory of the solid-state drive.

6. A data processing apparatus, characterized in that, include: The acquisition module is used to acquire several pieces of mapping data to be written to the incremental buffer; The compression module is used to compress the mapping data according to the continuous physical block address information represented by the several mapping data to obtain compressed mapping data. The processing module is used to write the compressed mapping data into the incremental buffer; The mapping data includes a one-to-one correspondence of logical block addresses, old physical block addresses, and new physical block addresses. The compression module is specifically used for: The mapping data is split into first mapping data and second mapping data; wherein, the first mapping data includes a one-to-one logical block address and an old physical block address, and the second mapping data includes a one-to-one logical block address and a new physical block address; Based on the continuity information of the old physical block address represented by the first mapping data, the first mapping data is split into several segments of first sub-data. For any of the first sub-data, generate the first compressed sub-data corresponding to the first sub-data based on the length of the first sub-data, the starting logical block address, and the first starting sub-data of the first sub-data; Merge the first compressed sub-data corresponding to each of the first sub-data to obtain the first compressed data corresponding to the first mapped data; Based on the continuous information of the new physical block address represented by the second mapping data, the second mapping data is split into several segments of second sub-data; For any second sub-data, generate the second compressed sub-data corresponding to the second sub-data based on the length of the second sub-data, the starting logical block address, and the first starting sub-data of the first sub-data; Merge the second compressed sub-data corresponding to each of the second sub-data to obtain the second compressed data corresponding to the second mapped data; The first compressed data and the second compressed data are merged to obtain the compressed mapping data.

7. A data processing system, characterized in that, include: Random access memory and flash conversion layer controller, wherein the random access memory includes several incremental buffers and base buffers; The flash memory conversion layer controller uses the data processing method as described in any one of claims 1 to 5 to process the mapped data to be written to the incremental buffer.

8. An electronic device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the method as described in any one of claims 1 to 5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the method as described in any one of claims 1 to 5.

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