A finite field multiplier, divider and arithmetic circuit based on matrix operations

Abstract

This invention relates to a finite field multiplier, divider, and arithmetic circuit based on matrix operations, and relates to the field of arithmetic circuit design. The finite field multiplier based on matrix operations includes constructing matrix Y by calling or calculating the corresponding matrix according to the characteristic polynomial P. i The matrix construction module provides a matrix; it constructs matrix Y using a matrix. i The matrix generation module generates matrix B by multiplying the element bi corresponding to multiplier b and performing a bitwise XOR operation; the result calculation module calculates the product of multiplicand a and matrix B to obtain the finite field multiplication result. The finite field multiplier based on matrix operations first transforms multiplier b into matrix B, with the delay provided by the matrix generation module (i.e., one-level AND gate and one-level XOR gate), and then multiplies multiplicand a and matrix B. This process is performed in parallel, with the delay also consisting of one-level AND gate and one-level XOR gate, resulting in high computational efficiency. The finite field divider based on matrix operations is implemented by adding an inversion module to the finite field multiplier based on matrix operations, making the implementation simple.

Description

Technical Field

[0001] This invention relates to the field of finite field arithmetic technology, and in particular to a finite field multiplier, divider and arithmetic circuit based on matrix operations. Background Technology

[0002] A finite field, also known as a Galois field, is a set of elements with a finite number of elements. Operations such as addition, subtraction, multiplication, and division can be defined within this set, and these operations satisfy the commutative, associative, and distributive laws of algebraic operations. A finite field is usually denoted as GF( ), where p is a prime number, and the number of elements in the finite field is . Finite field GF( It has important applications in fields such as block ciphers, pseudo-random number generators, and encoding / decoding.

[0003] The finite field GF(2) contains only two elements: 0 and 1. Addition is defined as the XOR operation, and multiplication is defined as the AND operation. Addition and subtraction in finite field multipliers are defined as bitwise XOR operations. Multiplication is more complex, requiring polynomial multiplication followed by taking the remainder of the characteristic polynomial. In digital circuits, one method to implement a finite field multiplier is using a linear feedback shift register (LFP) or a lookup table. A LFP can only process one bit at a time, requiring eight clock cycles to complete the operation. A lookup table requires a large number of computation and storage units. Other methods involve expanding the LFP within a single clock cycle; this essentially compresses eight clock cycles into one, resulting in a significant delay within that clock cycle and hindering high speed. Another method to reduce area and increase speed is to expand the characteristic polynomial, simplifying the expression. However, this method is only suitable for circuits with specific polynomials and expressions, such as AES, and lacks general applicability. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, the present invention provides a finite field multiplier, divider, and arithmetic circuit based on matrix operations.

[0005] In a first aspect, the present invention provides a finite field multiplier based on matrix operations, comprising: an input interface for receiving a multiplicand a, a multiplier b, and a characteristic polynomial P; and a matrix construction matrix providing module (1) for calling or calculating the corresponding matrix construction matrix Y based on the characteristic polynomial P. i ; Matrix generation module (2), used to construct matrix Y using a matrix. i Multiplying the matrix by the element bi corresponding to the multiplier b and then performing a bitwise XOR operation yields matrix B, where matrix B corresponding to the multiplier b is represented as: B = b0Y0^b1Y1^…^bn-1 Y n-1 The result calculation module (3) is used to calculate the product of the multiplicand a and the matrix B in parallel to obtain the finite field multiplication result.

[0006] Furthermore, based on the characteristic polynomial P, the corresponding lookup table and matrix are calculated to construct matrix Y. i include: Determine vector q i The characteristic polynomial P satisfies the following relationship: x n = p n-1 x n-1 + … + p1x + p0; Vector q1 is the characteristic polynomial P, and vector q2 corresponds to x. n+1 The calculation method is as follows: shift q1 to the left by 1 bit. If the highest bit of vector q1 is 1, add the result of the left shift to vector q1; and so on to obtain all vectors q. i ; The first row to the (n-1)th row of the lookup table are vectors q. n-1 q n-2 To find q2 and q1, the query table contains rows n to 2n-1. An identity matrix of n; matrix construction matrix Y0 represents rows n to 2n-1 of the lookup table, Y1 represents the position of Y0 in the lookup table shifted up one row, Y... i The position of Y0 in the lookup table is moved up i rows, and so on, to obtain all the matrices and construct the matrix Y0-Y. n-1 .

[0007] Furthermore, the matrix construction matrix providing module generates a linear transformation circuit for generating the matrix construction matrix to calculate the corresponding matrix construction matrix Y based on the characteristic polynomial P. i .

[0008] Furthermore, the matrix generation module includes: a module for constructing matrix Y. i An AND gate that performs an AND operation on the element bi corresponding to the multiplier b, wherein the number of AND gates is set according to the specifications of the matrix being constructed; and an XOR gate that performs a bitwise XOR operation on the result of the AND operation.

[0009] Furthermore, the result calculation module includes several AND gates for multiplying the multiplier a with the column elements of matrix B, wherein the number of AND gates is set according to the size of the finite field; and an XOR gate for performing a bitwise XOR operation on the multiplication result, thereby realizing the right multiplication of the multiplier a by matrix B.

[0010] Furthermore, the result calculation module includes a convolution operation circuit that performs vector-matrix multiplication.

[0011] Secondly, embodiments of the present invention provide a finite field divider based on matrix operations. Applying the aforementioned finite field multiplier based on matrix operations, the finite field divider includes: an inversion module for inverting matrix B, wherein the inversion module is disposed between the matrix generation module and the result calculation module of the finite field multiplier based on matrix operations; the result calculation module calculates the multiplicand a and the inverse matrix B. -1 The product of these terms yields the result of division over a finite field.

[0012] Furthermore, the inversion module includes a matrix inversion operation circuit based on LU decomposition.

[0013] Thirdly, the present invention provides an operational circuit structure, which includes any one or more of the aforementioned finite field multiplier based on matrix operations and the aforementioned finite field divider based on matrix operations.

[0014] The technical solutions provided in the embodiments of the present invention have the following advantages compared with the prior art: This application's finite field multiplier based on matrix operations includes constructing matrix Y by calling or calculating the corresponding matrix according to the characteristic polynomial P. i The matrix construction module provides a matrix; it constructs matrix Y using a matrix. i The module generates matrix B by multiplying the element bi corresponding to multiplier b and performing a bitwise XOR operation; the module calculates the result of the finite field multiplication by computing the product of multiplicand a and matrix B in parallel. The matrix construction module is relatively independent and mainly provides the matrix Y corresponding to the characteristic polynomial for the calculation process. i The independence is reflected in the matrix Y provided for construction. i It is independent of the characteristic polynomial and the input of the multiplication operation. A finite field multiplier based on matrix operations performs multiplication in two steps: first, the multiplier b is transformed into a matrix B, with the delay introduced by the matrix generation module (i.e., a single-level AND gate and a single-level XOR gate); the multiplication of the multiplicand a into matrix B is performed in parallel, with the delay also consisting of a single-level AND gate and a single-level XOR gate, resulting in high computational efficiency. Furthermore, this finite field multiplier based on matrix operations supports the implementation of a divider.

[0015] This application proposes a finite field divider based on matrix operations. Between the matrix generation module and the result calculation module of a finite field multiplier based on matrix operations, an inversion module is set up. The result calculation module calculates the multiplicand *a* and the inverse matrix *B*. -1 The product of the products yields the finite field division result. The finite field divider based on matrix operations is implemented on the basis of the finite field multiplier based on matrix operations. The implementation method is simple, and the reuse of the finite field multiplier and divider based on matrix operations can be supported by configuring selection elements. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of a finite field multiplier based on matrix operations provided in an embodiment of the present invention; Figure 2 A schematic diagram of a finite field divider based on matrix operations provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a finite field multiplier provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of an operational circuit provided in an embodiment of the present invention.

[0019] The labels and their meanings in the diagram are as follows: 1. Matrix construction module, 2. Matrix generation module, 3. Result calculation module, 4. Inversion module, 5. Polynomial provision module, 6. First calculation module, 7. Second calculation module, 8. Transformation module, 9. Third calculation module, 10. Selection module. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] Example 1 This invention provides a finite field multiplier. The finite field multiplier divides the process of calculating the modulo remainder when encountering a carry in finite field multiplication into two parts: multiplication calculation and carry conversion calculation. The carry conversion scheme is stored separately. In actual calculation, the carry conversion scheme is called after the multiplication is completed, so that the multiplication calculation is not affected by the carry conversion, thus speeding up the operation. The characteristic polynomial, multiplicand, and multiplier are called separately. When the characteristic polynomial is called, the carry conversion scheme is changed, thereby realizing the replacement of the polynomial.

[0023] See Figure 3 As shown, the finite field multiplier includes: an input interface for receiving multiplicand a, multiplier b, and characteristic polynomial P; a polynomial providing module 5 for calling or calculating the polynomial required for carry transformation according to the characteristic polynomial P; and a module for calculating the product ab of each bit of multiplicand a and multiplier b using multiplicand a and multiplier b. i The first calculation module 6; will ab i The second calculation module 7 shifts i bits to the left and XORs (adds) all the shifted results to obtain ab; the conversion module 8 uses the carry conversion polynomial to convert each bit in ab to a finite field when carry conversion is needed; and the third calculation module 9 adds the converted results.

[0024] In one embodiment, the first calculation module 6 and the conversion module 8 each include a plurality of AND gates; wherein the inputs of the AND gates of the first calculation module are connected to an input interface, and the outputs are connected to the inputs of the second calculation module 7; the inputs of the AND gates of the second calculation module 8 are connected to the outputs of the polynomial providing module 5 and the second calculation module 7, and the outputs are connected to a third calculation module. In the second calculation module 8, each AND gate receives a different polynomial provided by the polynomial providing module 5. The second calculation module 7 includes two-input XOR gates, three-input XOR gates, etc., and the third calculation module 9 is an XOR gate.

[0025] The principle of the finite field multiplier is as follows: The finite field multiplier is applied to the finite field GF( Let's take the finite field GF( as an example for illustration.) Each digit in the multiplication table can be viewed as an 8-digit number, with each digit containing only 0 and 1 elements. Ignoring the limitations of a finite field, the multiplication operation involves multiplying a bitwise position of the multiplicand *a* and the multiplier *b*. If that bitwise position of *b* is 0, the product is 0; if it's 1, the product is *a*. When multiplying the least significant bits of *a* and *b*, the product is the result. If multiplying the second least significant bit of *a* and *b*, the product is shifted left by one bit; if multiplying the third least significant bit of *a* and *b*, the product is shifted left by two bits; and so on, until the product of each bitwise position of *a* and *b* is obtained. Finally, the results are summed to obtain the product of *a* and *b*. This bitwise multiplication operation of *a* and *b* is parallel and highly efficient. However, considering the limitations of a finite field, a left shift could potentially cause the most significant bit of the product to overflow. When the highest bit overflows, the process of processing the highest bit of the product includes: finding the value corresponding to the highest bit in the finite field, and then adding this value to the product after removing the highest bit. For each bit of the product of multiplying the multiplicands a and b, the overflowing bits are identified, and their corresponding values ​​in the finite field are found. Finally, all the finite field values ​​are added together to obtain the final finite field product. In this way, true finite field multiplication is achieved, and each bit carrying only requires one lookup and one XOR operation, reducing the number of high-bit operations.

[0026] The process of converting the overflow bit into a finite field in the above process includes: For ease of representation, GF( The numbers in ) are represented as a polynomial: Therefore, a b=c can be expressed as The product has 15 terms. When i is greater than 7, the product overflows. When i equals 8, x... 8 It can be transformed into the characteristic polynomial p, x in a finite field. 9 equals x 8 Shifting left by 1 bit means shifting the characteristic polynomial left by 1 bit. If the highest bit overflows, convert the highest bit back to the characteristic polynomial and add it to x. 9 The remaining bits, so x 9This is also converted into numbers in a finite field. Similarly, the numbers in the finite field corresponding to each term where i is greater than 7 can be obtained. In actual circuit design, the bitwise progressive operation of the polynomial provider module 5 will generate a certain delay in calculating the polynomial. Since the correspondence is only related to the characteristic polynomial and not to the input vector, the correspondence can be stored in the memory unit for later use. If the characteristic polynomial is changed, only the correspondence in the memory unit needs to be retrieved again; the structure of the first calculation module 6, the second calculation module 7, the conversion module 8, and the third calculation module 9 does not need to be changed. Several exemplary characteristic polynomials in hexadecimal representation are given below: the characteristic polynomial is 1b (used for AES encryption), and the corresponding polynomials include: P0=1b, P1=36, P2=6c, P3=d8, P4=ab, P5=4d, P6=9a. The characteristic polynomial is 1d, and the corresponding polynomials include: P0=1d, P1=3a, P2=74, P3=e8, P4=cd, P5=87, P6=13. The characteristic polynomial is 2b, and the corresponding polynomials include: P0=2b, P1=56, P2=ac, P3=73, P4=e6, P5=e7, P6=e5.

[0027] The finite field multiplier from Figure 3 As can be seen, inputs a and b undergo two levels of AND operations and two levels of XOR operations to obtain the output. The multiplication operation is highly parallelized, and the polynomial module is relatively independent, not occupying multiplication operation time, resulting in high multiplication efficiency. However, the finite field multiplier first performs multiplication operations and then converts to a finite field, which requires handling carry and has poor reversibility, making division impossible. Furthermore, this application provides a finite field multiplier based on matrix operations.

[0028] Example 2 This invention provides a finite field multiplier based on matrix operations. The matrix-operation-based finite field multiplier transforms Galois field multiplication into multiplication of a multiplicand and a matrix, where the matrix is ​​obtained by transforming the multiplier. Because matrix operations have high parallelism, the computational speed of finite field multiplication can be improved.

[0029] In the specific implementation process, please refer to Figure 1 As shown, the finite field multiplier based on matrix operations includes: an input interface that receives the multiplicand a, the multiplier b, and the characteristic polynomial P; a matrix construction module 1 that calls or calculates the corresponding matrix Yi based on the characteristic polynomial P; and a matrix generation module 2 that multiplies the constructed matrix Yi with the element bi corresponding to the multiplier b and then performs a bitwise XOR operation to obtain matrix B, where the matrix B corresponding to the multiplier b is represented as: B = b0Y0^b1Y1^…^b n- 1Y n-1; Calculate the product of the multiplicand a and matrix B to obtain the result of finite field multiplication (module 3).

[0030] In one implementation, the matrix construction matrix providing module 1 generates a linear transformation circuit for generating the matrix construction matrix to calculate the corresponding matrix construction matrix Y based on the characteristic polynomial P. i .

[0031] In another implementation, matrix Y is constructed beforehand from the characteristic polynomial P and the matrix corresponding to the characteristic polynomial P. i The matrix is ​​constructed and stored as a query table. The matrix construction module 1 constructs matrix Y by matching the corresponding matrix from the query table based on the characteristic polynomial P. i Several exemplary sets of characteristic polynomials, polynomials, and matrix constructions in hexadecimal representation are given below: The characteristic polynomial is 1b (used for AES encryption), and the corresponding matrix construction matrices include: Y0=8040201008040201, Y1=1b80402010080402, Y2=361b804020100804, Y3=6c361b8040201008, Y4=d86c361b80402010, Y5=abd86c361b804020, Y6=4dabd86c361b8040, Y7=9a4dabd86c361b80.

[0032] The characteristic polynomial is 1d, and the corresponding matrix construction matrices include: Y0=8040201008040201, Y1=1d80402010080402, Y2=3a1d804020100804, Y3=743a1d8040201008, Y4=e8743a1d80402010, Y5=cde8743a1d804020, Y6=87cde8743a1d8040, Y7=1387cde8743a1d80.

[0033] The characteristic polynomial is 2b, and the corresponding matrix construction matrices include: Y0=8040201008040201, Y1=2b80402010080402, Y2=562b804020100804, Y3=ac562b8040201008, Y4=73ac562b80402010, Y5=e673ac562b804020, Y6=e7e673ac562b8040, Y7=e5e7e673ac562b80.

[0034] In one embodiment, the matrix generation module (2) includes: a matrix Y constructed from the matrix Y. iAn AND gate that multiplies the element bi corresponding to the multiplier b, wherein the number of AND gates is set according to the size of the finite field; and an XOR gate that performs a bitwise XOR operation on the multiplication result.

[0035] In one embodiment, the result calculation module 3 includes several AND gates for multiplying the multiplier a with the column elements of matrix B, wherein the number of AND gates is set according to the size of the finite field; and an XOR gate for performing a bitwise XOR operation on the multiplication result.

[0036] In another embodiment, the result calculation module 3 includes a convolution operation circuit for multiplying vectors and matrices. When the size of the finite field is greater than a certain threshold, using the convolution operation circuit to multiply vectors and matrices is more efficient.

[0037] The principle of this application is as follows: Finite field GF( The multiplication operation of ) is represented as a b = c, where a represents the multiplicand, c represents the result of the multiplication operation, a and c are n-dimensional row vectors, and b is the multiplier. "b" can be considered an operation on the multiplicand a, since the multiplicand a and the result c have the same dimension. The operation corresponding to "b" is a linear transformation of the multiplicand a, which can be represented using matrix multiplication, i.e., aB = c. Here, B is an integer n. For n-dimensional matrices, vectors, and matrix multiplication operations, the operation rules in GF(2) must be followed. The form of matrix B needs to be determined to ensure that the result of linear transformation is consistent with the result of multiplication.

[0038] Finite field GF( This can be viewed as a vector space over GF(2) with dimension n, and a set of linearly independent vectors is chosen as the basis of this vector space. The set {y0, y1, y2, ..., y...} is selected. n-1}={2 0 , 2 1 , 2 2 , …, 2 n-1 Using y = b0y0 + b1y1 + ... + b n-1 y n-1 In binary, b i Let be the value of the i-th bit of the multiplier b. Since each bit is independent, b = b0y0 + b1y1 + ... + b n-1 y n-1 The addition operation in the expression is replaced with an XOR operation, i.e.: b = b0y0^b1y1^…^b n-1 y n-1 ^ represents bitwise XOR. Then a b= b0a y0^ b1a y1^ … ^ b n- 1a y n-1 .Will" y i The corresponding operation constructs matrix "Y" using a matrix. i " indicates. And according to the matrix operation rules: aB^aC=a(B^C), then a b = a(b0Y0^ b1Y1^ … ^ b n-1 Y n-1 ),Right now" The operation represented by "b" is denoted by matrix B, where B = b0Y0^b1Y1^…^b n-1 Y n-1 Thus, a matrix B related to the multiplier b is established, and the result of multiplying the multiplicand a and the multiplier b is equal to the product of the multiplicand a and the matrix B.

[0039] Calculate the corresponding lookup table and construct matrix Y based on the characteristic polynomial P. i To determine the matrix Y, construct matrix Y. i Specific representation: Determine vector q i The characteristic polynomial P satisfies the following relationship: x n = p n-1 x n-1 + … + p1x + p0; Vector q1 is the characteristic polynomial P, and vector q2 corresponds to x. n+1 The calculation method is as follows: shift q1 to the left by 1 bit. If the highest bit of vector q1 is 1, add the result of the left shift to vector q1; and so on to obtain all vectors q. i ; The first row to the (n-1)th row of the lookup table are vectors q. n-1 q n-2 To find q2 and q1, the query table contains rows n to 2n-1. An identity matrix of n; matrix construction matrix Y0 represents rows n to 2n-1 of the lookup table, Y1 represents the position of Y0 in the lookup table shifted up one row, Y... i The position of Y0 in the lookup table is moved up i rows, and so on, to obtain all the matrices and construct the matrix Y0-Y. n-1 .

[0040] For the finite field GF( Multiplication operations (a, Y) involve carry-over and do not involve taking the remainder of a polynomial. i The corresponding multiplication is a 2 iIn binary, this means shifting 'a' left by 'i' bits. The lookup table corresponding to the input vector 'b' is then represented as: ; The query table has n dimensions. 2n-1. For a 2 0 There is no carry, and the corresponding Y0 is n. An identity matrix of n. For a 2 1 Shifting 'a' left by 1 bit results in a carry, requiring a remainder operation. According to finite field arithmetic rules, the remainder result depends on the highest bit of 'a'. Furthermore, removing the first column of the identity matrix and padding it with zeros on the right is equivalent to removing the last row and padding it with zeros on the top. Therefore, the corresponding Y1 is obtained by removing the last row of Y0 and adding a row vector q1 to the first row. The specific form of q1 depends on GF( The characteristic polynomial p is of the form of Y1. Similarly, Y2 is obtained by removing the last row of Y1 and adding row vector q2 to the first row; and so on, to obtain all the Y1 and Y2 forms. i .

[0041] Determine vector q i Specific form: in GF( On x, the characteristic polynomial p satisfies the following relation: n =p n-1 x n-1 +…+p1x+p0; q1 corresponds to x n Therefore, vector q1 is the characteristic polynomial p. q2 corresponds to x. n+1 Therefore, q2 is represented as q1 shifted left by 1 bit. If the most significant bit of q1 is 1, the result of the left shift needs to be added to q1. This process can be repeated to obtain all possible values ​​of q. i .

[0042] from Figure 1 As can be seen from the above description, the matrix construction module is relatively independent, mainly providing the matrix Y corresponding to the characteristic polynomial for the calculation process. i A finite field multiplier based on matrix operations performs multiplication in two steps. First, the multiplier b is transformed into a matrix B. The delay is introduced by the matrix generation module, i.e., a single AND gate and a single XOR gate. The multiplication of the multiplicand a into matrix B is performed in parallel, with the delay also consisting of a single AND gate and a single XOR gate. This method offers high computational efficiency.

[0043] Example 3 This invention provides a finite field divider based on matrix operations. This matrix operation-based finite field divider is implemented based on a matrix operation-based finite field multiplier, achieving division while inheriting the advantages of the matrix operation-based finite field divider. For details, please refer to... Figure 2 As shown, the finite field divider based on matrix operations includes: a finite field multiplier based on matrix operations and an inversion module 4 for inverting matrix B. The result calculation module of the finite field multiplier based on matrix operations calculates the multiplicand a and the inverse matrix B. -1 The product yields the result of finite field division. An exemplary inversion module employs a matrix inversion operation circuit based on LU decomposition.

[0044] The principle of a finite field divider based on matrix operations is as follows: Since a finite field multiplier based on matrix operations essentially transforms the input multiplier b into a matrix B, and then calculates the product of vector a and matrix B, the finite field product c can be obtained. Multiplying both sides of aB=c by B on the right... -1 , for a=c B -1 The calculation result shows that some operation was performed on c to obtain a, and according to the rules of operation in finite fields, a... b = c, a = c / b. Therefore, multiply by B on the right. -1 Matrix operations are equivalent to division by b. Therefore, by adding an inversion module for matrix B after the matrix generation module of the multiplier based on matrix operations, a finite field divider based on matrix operations can be obtained by performing the matrix inversion operation once.

[0045] Example 4 This invention provides an arithmetic circuit, which includes any one or more of the aforementioned finite field multiplier based on matrix operations and the aforementioned finite field divider based on matrix operations.

[0046] As an example of an operational circuit, see [reference]. Figure 4 As shown, in this embodiment of the invention, a selection module 10 is provided after the matrix generation module 2 of the finite field multiplier based on matrix operations. The selection module 10 selectively connects to the result calculation module 3 or the inversion module 4 to achieve the reuse of the finite field multiplier and the finite field divider based on matrix operations. The resulting operational circuit occupies less space.

[0047] This application's finite field multiplier based on matrix operations includes constructing matrix Y by calling or calculating the corresponding matrix according to the characteristic polynomial P. i The matrix construction module provides a matrix; it constructs matrix Y using a matrix. i The module generates matrix B by multiplying the element bi corresponding to multiplier b and performing a bitwise XOR operation; the module calculates the result of the finite field multiplication by computing the product of multiplicand a and matrix B in parallel. The matrix construction module is relatively independent and mainly provides the matrix Y corresponding to the characteristic polynomial for the calculation process. i The independence is reflected in the matrix Y provided for construction.i It is independent of the characteristic polynomial and the input of the multiplication operation. A finite field multiplier based on matrix operations performs multiplication in two steps: first, the multiplier b is transformed into a matrix B, with the delay introduced by the matrix generation module (i.e., a single-level AND gate and a single-level XOR gate); the multiplication of the multiplicand a into matrix B is performed in parallel, with the delay also consisting of a single-level AND gate and a single-level XOR gate, resulting in high computational efficiency. Furthermore, this finite field multiplier based on matrix operations supports the implementation of a divider.

[0048] This application proposes a finite field divider based on matrix operations. Between the matrix generation module and the result calculation module of a finite field multiplier based on matrix operations, an inversion module is set up. The result calculation module calculates the multiplicand *a* and the inverse matrix *B*. -1 The product of the products yields the finite field division result. The finite field divider based on matrix operations is implemented on the basis of the finite field multiplier based on matrix operations. The implementation method is simple, and the reuse of the finite field multiplier and divider based on matrix operations can be supported by configuring selection elements.

[0049] In the embodiments provided by this invention, it should be understood that the disclosed structures and methods can be implemented in other ways. For example, the structural embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, structures, or units, and may be electrical, mechanical, or other forms.

[0050] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0051] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0052] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A finite field multiplier based on matrix operations, characterized in that, Galois field multiplication is converted into multiplication of a multiplicand and a matrix, wherein the matrix is ​​obtained by the multiplier. Matrix operations have high parallelism, improving the operation speed of finite field multiplication. It includes: an input interface for receiving the multiplicand a, multiplier b, and characteristic polynomial P; and a matrix construction module (1) for calling or calculating the corresponding matrix construction matrix Y based on the characteristic polynomial P. i Among them, the matrix construction module (1) calculates the corresponding lookup table and matrix construction matrix Y based on the characteristic polynomial P. i Includes: the matrix construction matrix providing module to generate a linear transformation circuit for the matrix construction matrix to calculate the corresponding matrix construction matrix Y based on the characteristic polynomial P. i Determine vector q i The characteristic polynomial P satisfies the following relationship: x n = p n-1 x n-1 + … + p1x + p0; Vector q1 is the characteristic polynomial P, and vector q2 corresponds to x. n+1 The calculation method is as follows: shift q1 to the left by 1 bit. If the highest bit of vector q1 is 1, add the result of the left shift to vector q1; and so on to obtain all vectors q. i Y0 is n For an identity matrix of n, Y1 is obtained by removing the last row of Y0 and adding row vector q1 to the first row; Y2 is obtained by removing the last row of Y1 and adding row vector q2 to the first row; and so on, to obtain all Y... i ; The first row to the (n-1)th row of the lookup table are vectors q. n-1 q n-2 To find q2 and q1, the query table contains rows n to 2n-1. An identity matrix of n, i.e., a matrix constructed from matrix Y0, where Y1 is the matrix shifted up one row from the position of Y0 in the lookup table. i The position of Y0 in the lookup table is moved up i rows, and so on, to obtain all the matrices and construct the matrix Y0-Y. n-1 ; Matrix generation module (2) is used to construct matrix Y using a matrix. i After multiplying the element bi corresponding to the multiplier b, a bitwise XOR operation is performed to obtain matrix B. The matrix generation module (2) includes: a matrix Y constructed from the matrix bi. i An AND gate performs a bitwise AND operation on the element bi corresponding to the multiplier b, where the number of AND gates is set according to the matrix construction specifications; and an XOR gate performs a bitwise XOR operation on the result of the AND operation, where the matrix B corresponding to the multiplier b is represented as: B = b0Y0^b1Y1^…^b n-1 Y n-1 ; The result calculation module (3) is used to calculate the product of the multiplicand a and the matrix B in parallel to obtain the finite field multiplication result. The result calculation module (3) includes several AND gates for multiplying the multiplicand a and the matrix B, wherein the number of AND gates is set according to the size of the finite field; and an XOR gate for performing a bitwise XOR operation on the multiplication result to realize the right multiplication of the multiplicand a by the matrix B. The result calculation module 3 includes a convolution operation circuit for multiplying a vector and a matrix. When the size of the finite field is greater than a certain threshold, the convolution operation circuit is used to realize the multiplication of the vector and the matrix.

2. The finite field multiplier based on matrix operations according to claim 1, characterized in that, Construct matrix Y based on the characteristic polynomial P and the matrix called. i This includes: pre-constructing matrix Y from the characteristic polynomial P and the matrix corresponding to the characteristic polynomial P. i The matrix is ​​constructed and stored as a query table. The matrix construction module constructs matrix Y by matching the corresponding matrix from the query table based on the characteristic polynomial P. i .

3. A finite field divider based on matrix operations, employing the finite field multiplier based on matrix operations as described in claim 1 or 2, characterized in that, The finite field divider based on matrix operations includes: an inversion module (4) for inverting matrix B, wherein the inversion module (4) is located between the matrix generation module and the result calculation module of the finite field multiplier based on matrix operations, and the result calculation module calculates the multiplicand a and the inverse matrix B. -1 The product of these terms yields the result of division over a finite field.

4. The finite field divider based on matrix operations according to claim 3, characterized in that, The inversion module includes a matrix inversion operation circuit based on LU decomposition.

5. An operational circuit, characterized in that, The operational circuit includes: any one or more of the finite field multiplier based on matrix operations as described in any one of claims 1 or 2 and the finite field divider based on matrix operations as described in any one of claims 3 or 4.

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