Test method and device of storage system, electronic equipment and storage medium

Abstract

The present disclosure provides a test method and device of a storage system, an electronic device and a storage medium, relates to the technical field of computers, and particularly relates to the technical field of chip testing. The implementation scheme is as follows: a test path of a storage system and a plurality of input data used for testing the storage system are acquired, the test path is a storage sequence with a first storage in a plurality of storages as a starting point and a second storage in the plurality of storages as a terminal point, and each storage in the plurality of storages is divided into a plurality of storage areas; the plurality of input data are sequentially input into idle storage areas of the first storage, so that each input data in the plurality of input data sequentially passes through idle storage areas of each storage in the test path and is output by the second storage; a plurality of output data output by the second storage are acquired; and a test result of the storage system is determined based on the plurality of input data and the plurality of output data.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of chip technology, specifically to a testing method and apparatus for a storage system, an electronic device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Different types of memory have different speeds, capacities, and costs. Generally, the faster the memory, the smaller the capacity, and the higher the cost. Modern computers often use multi-level storage structures, combining memory devices with different performance characteristics into a storage system to achieve optimal cost-effectiveness.

[0003] The methods described in this section are not necessarily methods that had been previously conceived or adopted. Unless otherwise specified, no method described in this section should be assumed to be prior art simply because it is included in this section. Similarly, unless otherwise specified, the issues mentioned in this section should not be considered to be accepted in any prior art. Summary of the Invention

[0004] This disclosure provides a method and apparatus for testing storage systems, an electronic device, a computer-readable storage medium, and a computer program product.

[0005] According to one aspect of this disclosure, a method for testing a storage system is provided, wherein the storage system includes multiple memories at different levels, the method comprising: acquiring a test path for the storage system and multiple input data for testing the storage system, wherein the test path is a sequence of memories starting from a first memory among the multiple memories and ending at a second memory among the multiple memories, and each memory among the multiple memories is divided into multiple storage areas; sequentially inputting the multiple input data into a free storage area of ​​the first memory, such that each input data sequentially passes through the free storage areas of each memory in the test path and is output by the second memory; acquiring multiple output data output by the second memory; and determining a test result for the storage system based on the multiple input data and the multiple output data.

[0006] According to another aspect of this disclosure, a testing apparatus for a storage system is provided, wherein the storage system includes multiple memories at different levels, the apparatus comprising: an acquisition module configured to acquire a test path of the storage system and multiple input data for testing the storage system, wherein the test path is a sequence of memories starting from a first memory among the multiple memories and ending at a second memory among the multiple memories, and each memory among the multiple memories is divided into multiple storage areas; an input module configured to sequentially input the multiple input data into a free storage area of ​​the first memory, such that each input data sequentially passes through the free storage areas of each memory in the test path and is output by the second memory; an output module configured to acquire multiple output data output by the second memory; and a first determination module configured to determine a test result of the storage system based on the multiple input data and the multiple output data.

[0007] According to another aspect of this disclosure, a chip is provided that includes the aforementioned apparatus.

[0008] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described above.

[0009] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause the computer to perform the above-described method.

[0010] According to another aspect of this disclosure, a computer program product is provided, including a computer program, wherein the computer program, when executed by a processor, is capable of implementing the above-described method.

[0011] According to one or more embodiments of this disclosure, accurate testing of the storage system can be achieved.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0014] Figure 1 A schematic diagram of an exemplary system in which various methods described herein may be implemented according to embodiments of the present disclosure is shown;

[0015] Figure 2 A flowchart of a testing method for a storage system according to an embodiment of the present disclosure is shown;

[0016] Figure 3 A schematic diagram illustrating the testing process of a secondary storage system according to an embodiment of the present disclosure is shown;

[0017] Figure 4A , 4B A schematic diagram illustrating the testing process of a three-level storage system according to an embodiment of the present disclosure is shown;

[0018] Figure 5 A structural block diagram of a test apparatus for a storage system according to an embodiment of the present disclosure is shown; and

[0019] Figure 6 A structural block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0020] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0021] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0022] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. Furthermore, the term "and / or" as used in this disclosure covers any one of the listed items and all possible combinations thereof. "More than" means two or more.

[0023] Multiple memory modules at different levels can form a storage system. To ensure the reliability and stability of the storage system, it needs to be tested before it is put into production or use.

[0024] In related technologies, each memory in a storage system is typically tested separately to obtain the performance of each individual memory. The performance of the entire storage system is then estimated based on the performance of each memory. Because each memory is tested individually, it operates independently without interaction with other memories in the system. However, in real-world storage system applications, multiple levels of memory work collaboratively, with significant read / write interactions between adjacent levels. Therefore, the above testing approach does not reflect the actual application conditions of storage systems, leading to inaccurate test results that fail to reflect the actual performance of the storage system.

[0025] To address the aforementioned problems, this disclosure provides a testing method for a storage system. According to embodiments of this disclosure, during the testing process, each memory in the storage system is divided into multiple storage areas. Multiple input data are sequentially input into the free storage area of ​​the first memory in the test path and flow along the test path through the free storage areas of each memory, thereby realizing pipelined testing of the storage system. During the testing process, multiple memories work collaboratively and engage in read / write interactions, thus simulating the real working state of the storage system, making the test environment consistent with actual conditions, and thereby improving the accuracy of the test results.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of an exemplary system 100 in which the various methods and apparatus described herein can be implemented according to embodiments of this disclosure is shown. Reference Figure 1 The system 100 includes one or more client devices 101, 102, 103, 104, 105 and 106, a server 120, and one or more communication networks 110 coupling the one or more client devices to the server 120. The client devices 101, 102, 103, 104, 105 and 106 can be configured to execute one or more applications.

[0028] In embodiments of this disclosure, server 120 may run one or more services or software applications that enable the execution of test methods for the storage system.

[0029] In some embodiments, server 120 may also provide other services or software applications, which may include non-virtual and virtual environments. In some embodiments, these services may be provided as web-based services or cloud services, such as to users of client devices 101, 102, 103, 104, 105, and / or 106 under a Software as a Service (SaaS) model.

[0030] exist Figure 1 In the configuration shown, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or combinations thereof that can be executed by one or more processors. Users operating client devices 101, 102, 103, 104, 105, and / or 106 can sequentially interact with server 120 using one or more client applications to utilize the services provided by these components. It should be understood that various different system configurations are possible and may differ from system 100. Therefore, Figure 1 This is an example of a system used to implement the various methods described herein, and is not intended to be limiting.

[0031] Users can use client devices 101, 102, 103, 104, 105, and / or 106 to send initial commands. The client devices can provide an interface that allows users to interact with the client devices. The client devices can also output information to the user through this interface. Although... Figure 1 Only six client devices are described, but those skilled in the art will understand that this disclosure can support any number of client devices.

[0032] Client devices 101, 102, 103, 104, 105, and / or 106 may include various categories of computer devices, such as portable handheld devices, general-purpose computers (such as personal computers and laptops), workstation computers, wearable devices, smart screen devices, self-service terminal devices, service robots, gaming systems, thin clients, various messaging devices, sensors, or other sensing devices. These computer devices can run various categories and versions of software applications and operating systems, such as Microsoft Windows, Apple iOS, UNIX-like operating systems, Linux or Linux-like operating systems (such as Google Chrome OS); or include various mobile operating systems, such as Microsoft Windows Mobile OS, iOS, Windows Phone, and Android. Portable handheld devices may include cellular phones, smartphones, tablets, personal digital assistants (PDAs), etc. Wearable devices may include head-mounted displays (such as smart glasses) and other devices. Gaming systems may include various handheld gaming devices, internet-enabled gaming devices, etc. Client devices can run a variety of different applications, such as various Internet-related applications, communication applications (e.g., email applications), short message service (SMS) applications, and can use various communication protocols.

[0033] Network 110 can be any type of network well known to those skilled in the art, and can use any of a variety of available protocols (including, but not limited to, TCP / IP, SNA, IPX, etc.) to support data communication. By way of example only, one or more networks 110 can be a local area network (LAN), an Ethernet-based network, a token ring network, a wide area network (WAN), the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a blockchain network, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., Bluetooth, Wi-Fi), and / or any combination of these and / or other networks.

[0034] Server 120 may include one or more general-purpose computers, special-purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-range servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and / or combination. Server 120 may include one or more virtual machines running a virtual operating system, or other computing architectures involving virtualization (e.g., one or more flexible pools of logical storage devices that can be virtualized to maintain virtual storage devices for servers). In various embodiments, server 120 may run one or more services or software applications that provide the functionality described below.

[0035] The computing unit in server 120 can run one or more operating systems, including any of the aforementioned operating systems and any commercially available server operating system. Server 120 can also run any of a variety of additional server applications and / or middleware applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, etc.

[0036] In some implementations, server 120 may include one or more applications to analyze and merge data feeds and / or event updates received from users of client devices 101, 102, 103, 104, 105, and 106. Server 120 may also include one or more applications to display data feeds and / or real-time events via one or more display devices of client devices 101, 102, 103, 104, 105, and 106.

[0037] In some implementations, server 120 can be a server for a distributed system or a server integrated with blockchain. Server 120 can also be a cloud server, or an intelligent cloud computing server or intelligent cloud host with artificial intelligence technology. A cloud server is a host product in the cloud computing service system, designed to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0038] System 100 may also include one or more databases 130. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 130 may be used to store information such as audio files and video files. Databases 130 may reside in various locations. For example, a database used by server 120 may be local to server 120, or it may be located away from server 120 and may communicate with server 120 via a network-based or dedicated connection. Databases 130 may be of different categories. In some embodiments, the database used by server 120 may be, for example, a relational database. One or more of these databases may store, update, and retrieve data from and from the databases in response to commands.

[0039] In some embodiments, one or more of the databases 130 may also be used by an application to store application data. The databases used by the application may be different categories of databases, such as key-value stores, object stores, or regular stores supported by a file system.

[0040] Figure 1System 100 can be configured and operated in various ways to enable the application of various methods and apparatuses described in this disclosure. For example, a storage system to be tested can be deployed in client devices 101-106. Server 120 can distribute program instructions for performing test methods of the storage system according to embodiments of this disclosure to client devices 101-106 via network 110, so that client devices 101-106 can perform test methods of the storage system according to embodiments of this disclosure based on the program instructions.

[0041] Figure 2 A flowchart of a testing method 200 for a storage system according to an exemplary embodiment of the present disclosure is shown. The storage system includes multiple memories at different levels. Figure 2 As shown, method 200 includes steps S21-S240.

[0042] In step S210, the test path of the storage system and multiple input data for testing the storage system are obtained. The test path is a sequence of memories starting from a first memory and ending at a second memory. Each memory is divided into multiple storage areas.

[0043] In step S220, multiple input data are sequentially input into the free storage area of ​​the first memory, so that each input data is sequentially passed through the free storage area of ​​each memory in the test path and then output by the second memory.

[0044] In step S230, multiple output data from the second memory are acquired.

[0045] In step S240, the test results of the storage system are determined based on multiple input data and multiple output data.

[0046] According to embodiments of this disclosure, during testing, each memory in the storage system is divided into multiple storage areas. Multiple input data are sequentially input into the free storage area of ​​the first memory in the test path and flow along the test path through the free storage areas of each memory, thereby realizing pipelined testing of the storage system. During testing, multiple memories work collaboratively and engage in read / write interactions, thus simulating the real-world operating state of the storage system, making the test environment consistent with actual conditions, and thereby improving the accuracy of the test results.

[0047] In embodiments of this disclosure, the storage system includes multiple memories at different levels. For example, the storage system may be a multi-level cache system disposed in the processor chip, which may be a two-level cache system including L1 cache and L2 cache, or a three-level cache system including L1 cache, L2 cache and L3 cache, etc. Alternatively, the storage system may also be a storage system composed of main memory located outside the processor and cache located inside the processor (e.g., L2 cache).

[0048] In a storage system, each memory can only communicate with its adjacent memory level, and cannot communicate across levels. That is, data can only be transferred between adjacent memory levels, not across levels. For example, in a storage system with three levels of memory, data can only be transferred between the first and second levels, and between the second and third levels. The first and third levels of memory cannot communicate directly.

[0049] In the embodiments of this disclosure, the read / write bandwidth between adjacent memories is not shared. That is, a memory can perform read and write operations simultaneously.

[0050] In embodiments of this disclosure, the test path of the storage system is a sequence of memories that starts at a first memory among the plurality of memories of the storage system and ends at a second memory among the plurality of memories. The first memory and the second memory may be the same or different.

[0051] Taking a storage system with a three-level cache (L1, L2, and L3) as an example, the test path for this storage system can be L1 cache→L2 cache, L1 cache→L2 cache→L3 cache, L3 cache→L2 cache→L1 cache→L2 cache→L3 cache, L1 cache→L2 cache→L3 cache→L2 cache→L1 cache, and so on. By setting different test paths, the performance of different memory locations within the storage system can be tested, thereby achieving a comprehensive test of the storage system and facilitating the identification of fault locations.

[0052] According to some embodiments, when the storage system is a multi-level cache system, the test path can be set to include all the multiple memories in the multi-level cache system. The first memory and the second memory are set to be the same, and both are either the lowest-level memory or the highest-level memory among the multiple memories. For example, in a three-level cache system including L1 cache, L2 cache, and L3 cache, the test path can be set to L3 cache (lowest-level memory) → L2 cache → L1 cache → L2 cache → L3 cache or L1 cache (highest-level memory) → L2 cache → L3 cache → L2 cache → L1 cache. This allows input data to flow back and forth between the low-level caches and high-level caches of the multi-level cache system, thereby testing the overall performance of the multi-level cache system.

[0053] In embodiments of this disclosure, multiple input data used to test the storage system constitute an input data sequence, which is sequentially input into the first memory according to the order in the sequence. For example, the input data sequence consisting of multiple input data can be data1, data2, data3, ..., dataN. Accordingly, during the test, data1 can be input into the free storage area of ​​the first memory at time t1, data2 can be input into the free storage area of ​​the first memory at time t2, and so on.

[0054] In embodiments of this disclosure, each of the plurality of memories is divided into a plurality of storage areas. The number of storage areas in different memories may be the same or different.

[0055] According to some embodiments, the number of memory regions can be flexibly determined based on the current test path. Accordingly, method 200 also includes steps S250-S270.

[0056] In step S250, for any memory in the test path, the number of times that memory appears in the test path is determined. For example, in the test path L3 cache→L2 cache→L1 cache→L2cache→L3 cache, the memory L1 cache appears 1 time, while the memories L2 cache and L3 cache both appear 2 times.

[0057] In step S260, the number of storage areas for the memory is determined based on the number of times the memory appears in the test path. The number of storage areas is positively correlated with the number of times the memory appears in the test path. That is, the more times the memory appears in the test path, the more storage areas need to be allocated for it.

[0058] According to some embodiments, the ratio of the number of storage areas in each memory in the storage path is equal to the ratio of the number of times each memory appears in the test path. For example, in the test path L3 cache→L2 cache→L1 cache→L2 cache→L3 cache, memory L1 cache appears once, while memory L2 cache and L3 cache both appear twice. Accordingly, the number of storage areas in memory L1 cache, L2 cache, and L3 cache can be set to a ratio of 1:2:2. For example, L1 cache can be set to include 8 storage areas, and L2 cache and L3 cache can each include 16 storage areas.

[0059] In step S270, the memory is divided into the aforementioned number of storage areas. It should be noted that the size of each storage area can be the same or different.

[0060] According to steps S250-S270 above, dividing the memory into regions based on the number of times the memory appears in the test path can match the number of memory storage areas with the amount of data transferred during the test, thereby improving test efficiency.

[0061] In step S220, multiple input data are sequentially input into the free storage area of ​​the first memory (i.e., the starting point of the test path), so that each input data is sequentially passed through the free storage areas of each memory in the test path and then output by the second memory (i.e., the ending point of the test path).

[0062] It should be noted that the free storage area in memory refers to the storage area with an available capacity greater than or equal to the current input data.

[0063] In the embodiments of this disclosure, multiple input data are sequentially input into the free storage area of ​​the first memory at different times. The multiple input data flow through the test path and are finally output by the second memory. Taking the test path L3cache→L2 cache→L1 cache as an example, input data data1 is input into the free storage area of ​​the L3 cache at time t1. At time t2, the L3 cache writes data1 into the free storage area of ​​the L2 cache, and simultaneously, input data data2 is input into the free storage area of ​​the L3 cache. At time t3, the L2 cache writes data1 into the free storage area of ​​the L1 cache, and simultaneously, the L3 cache writes data2 into the free storage area of ​​the L2 cache, and input data data3 is input into the free storage area of ​​the L3 cache; and so on.

[0064] In step S230, multiple output data from the second memory are acquired. Each output data corresponds to a different input data, and the multiple output data can form an output data sequence.

[0065] It is understandable that due to a storage system failure, the value of some output data may be incorrect; that is, the output data is not the same as the corresponding input data.

[0066] In step S240, the test results of the storage system are determined based on multiple input data and multiple output data.

[0067] According to some embodiments, in step S240, the correctness of the storage system can be verified by determining whether multiple input data and multiple output data are the same.

[0068] According to some embodiments, multiple input data are arranged in the order they are input into the first memory to form an input data sequence. Multiple output data are arranged in the order they are output from the second memory to form an output data sequence. If the output data sequence is exactly the same as the input data sequence, the storage system can correctly store the data. Accordingly, the storage system is determined to have passed the correctness verification. Conversely, if the output data sequence is different from the input data sequence, the storage system cannot correctly store the data. Accordingly, the storage system is determined to have failed the correctness verification.

[0069] It is understandable that a storage system that fails the correctness verification cannot perform basic data storage functions, and therefore is deemed to have failed the test and should not be put into production or actual application.

[0070] According to some embodiments, step S240 may include steps S241 and S242.

[0071] In step S241, in response to the fact that multiple input data and multiple output data are the same, the data volume of multiple input data, the input time of the first input data among the multiple input data, and the output time of the last output data among the multiple output data are obtained.

[0072] In step S242, the read / write performance of the storage system is determined based on the aforementioned data volume, input time, and output time.

[0073] For storage systems, correctness is a prerequisite for read / write performance. Only when a storage system can correctly store data can its read / write performance be considered meaningful. According to the above embodiment, the fact that multiple input data points are identical to multiple output data points indicates that the storage system can correctly store the data. Under this premise, further determination of read / write performance can avoid unnecessary performance metric calculations, thereby improving testing efficiency.

[0074] According to some embodiments, in step S242, the read / write performance of the storage system can be represented by read / write bandwidth. Read / write bandwidth = data volume / (output time - input time). It can be understood that the larger the read / write bandwidth, the better the read / write performance of the storage system.

[0075] Figure 3 A schematic diagram illustrating the testing process of a secondary storage system according to an embodiment of the present disclosure is shown. Figure 3 As shown, the secondary storage system includes memories 310 and 320, and the test path is memory 310 → memory 320 → memory 310. Memory 310 is divided into storage areas 311 and 312. Memory 320 is divided into storage areas 321 and 322.

[0076] At time t1, the test data data1 is written to the free storage area 311 of memory 310.

[0077] At time t2, memory 310 writes test data data1 into the free storage area 321 of memory 320. At the same time, test data data2 is written into the free storage area 312 of memory 310.

[0078] At time t3, memory 320 writes test data data1 to the free storage area 311 of memory 310. At the same time, memory 310 writes test data data2 to the free storage area 322 of memory 320.

[0079] At time t4, memory 310 outputs test data data1. At the same time, memory 320 writes test data data2 into the free storage area 312 of memory 310.

[0080] Test data data3, data4, ..., dataN can be input into memory 310 in a similar manner to the steps described above. After circulating through the storage system, they are output by memory 310.

[0081] Figure 4A , 4B A schematic diagram illustrating the testing process of a three-level storage system according to an embodiment of the present disclosure is shown. Figure 4A , 4B As shown, this three-level storage system is a three-level cache system including L1, L2, and L3 caches. The test path is L3→L2→L1→L2→L3. L1 is divided into 8 storage areas, and L2 and L3 are each divided into 16 storage areas. Among them, the first 8 storage areas of L2, i.e. Figure 4A , 4B The eight storage areas shown in the left circular ring of L2 are used to read data from L3 and write data to L1. The last eight storage areas of L2, i.e. Figure 4A , 4B The eight storage areas shown in the right-hand ring of L2 are used for reading data from L1 and writing data to L3. Similarly, the first eight storage areas of L3, i.e. Figure 4A , 4B The eight memory areas shown in the left circular ring of L3 are used for reading external data (e.g., reading data from memory) and writing data to L2. The last eight memory areas of L3, i.e. Figure 4A , 4B The eight storage areas shown in the circular ring to the right of L3 are used to read data from L2 and output data to external memory (e.g., RAM). Storage areas marked with a "√" are free storage areas, and storage areas marked with a "+" are ready storage areas that contain data and are ready to be transferred to the next memory in the test path.

[0082] Figure 4A , 4B The arrows in the diagram indicate the data transmission directions at time i (i) and time (i+1) t(i+1) during the test. It can be understood that each arrow transmits different data. During the test, data flows between the various memories in a pipeline manner. Multiple memories work collaboratively and interact with each other for read and write operations. This simulates the real-world working state of the storage system, making the test environment consistent with actual conditions and thus improving the accuracy of the test results.

[0083] According to embodiments of this disclosure, a testing apparatus for a storage system is also provided. Figure 5 A structural block diagram of a test apparatus 500 for a storage system according to an embodiment of the present disclosure is shown. Figure 5 As shown, the device 500 includes an acquisition module 510, an input module 520, an output module 530, and a first determination module 540.

[0084] The acquisition module 510 is configured to acquire the test path of the storage system and multiple input data for testing the storage system, wherein the test path is a sequence of memories starting from a first memory in the plurality of memories and ending at a second memory in the plurality of memories, and each memory in the plurality of memories is divided into multiple storage areas.

[0085] The input module 520 is configured to sequentially input the plurality of input data into the free storage area of ​​the first memory, so that each of the plurality of input data is output by the second memory after sequentially passing through the free storage areas of each memory in the test path.

[0086] The output module 530 is configured to acquire multiple output data from the second memory.

[0087] The first determining module 540 is configured to determine the test results of the storage system based on the plurality of input data and the plurality of output data.

[0088] According to embodiments of this disclosure, during testing, each memory in the storage system is divided into multiple storage areas. Multiple input data are sequentially input into the free storage area of ​​the first memory in the test path and flow along the test path through the free storage areas of each memory, thereby realizing pipelined testing of the storage system. During testing, multiple memories work collaboratively and engage in read / write interactions, thus simulating the real-world operating state of the storage system, making the test environment consistent with actual conditions, and thereby improving the accuracy of the test results.

[0089] According to some embodiments, the apparatus 500 further includes: a second determining module configured to determine, for any memory in the test path, the number of times the memory appears in the test path; a third determining module configured to determine, based on the number of occurrences, the number of storage areas of the memory, wherein the number is positively correlated with the number of occurrences; and a partitioning module configured to partition the memory into the number of storage areas.

[0090] According to some embodiments, the first determining module 540 includes: a verification unit configured to verify the correctness of the storage system by determining whether the plurality of input data and the plurality of output data are the same.

[0091] According to some embodiments, the first determining module 540 includes: an acquisition unit configured to acquire, in response to the plurality of input data being the same as the plurality of output data, the data volume of the plurality of input data, the input time of the first input data among the plurality of input data, and the output time of the last output data among the plurality of output data; and a determining unit configured to determine the read / write performance of the storage system based on the data volume, the input time, and the output time.

[0092] According to some embodiments, the storage system is a multi-level cache system, and the test path includes the plurality of memories, wherein the first memory and the second memory are either the highest-level memory or the lowest-level memory among the plurality of memories.

[0093] It should be understood that Figure 5 The various modules and units of the apparatus 500 shown can be used with reference to Figure 2 The steps in method 200 described correspond to each other. Therefore, the operations, features, and advantages described above for method 200 also apply to apparatus 500 and its included modules and units. For the sake of brevity, some operations, features, and advantages will not be repeated here.

[0094] Although specific functions have been discussed with reference to specific modules above, it should be noted that the functions of the various modules discussed in this article can be divided into multiple modules, and / or at least some functions of multiple modules can be combined into a single module.

[0095] It should also be understood that this article can describe various technologies in the general context of software and hardware components or program modules. The above regarding... Figure 5 The described units can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these units can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these units can be implemented as hardware logic / circuit. For example, in some embodiments, one or more of modules 510-540 can be implemented together in a System on Chip (SoC). The SoC may include an integrated circuit chip (which includes a processor (e.g., a Central Processing Unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or one or more components of other circuitry) and may optionally execute received program code and / or include embedded firmware to perform functions.

[0096] According to another aspect of this disclosure, a chip is also provided, including a testing apparatus 500 for a memory system as described above. For example, the testing apparatus 500 for the memory system can be implemented as program instructions. The memory system can be a multi-level cache system in a processor chip. The processor chip performs testing on the memory system by storing, reading, and executing the aforementioned program instructions.

[0097] According to another aspect of this disclosure, an electronic device is also provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described test method 200 for the storage system.

[0098] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is also provided, wherein the computer instructions are used to cause the computer to perform the above-described test method 200 for the storage system.

[0099] According to another aspect of this disclosure, a computer program product is also provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the above-described storage system test method 200.

[0100] refer to Figure 6 The present invention describes a structural block diagram of an electronic device 600 that can serve as a server or client of the present disclosure, which is an example of a hardware device that can be applied to various aspects of the present disclosure. The electronic device is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0101] like Figure 6 As shown, device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 602 or a computer program loaded from storage unit 608 into random access memory (RAM) 603. RAM 603 may also store various programs and data required for the operation of device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0102] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, output unit 607, storage unit 608, and communication unit 609. Input unit 606 can be any type of device capable of inputting information to device 600. Input unit 606 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of the electronic device, and may include, but is not limited to, a mouse, keyboard, touchscreen, trackpad, trackball, joystick, microphone, and / or remote control. Output unit 607 can be any type of device capable of presenting information, and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. Storage unit 608 may include, but is not limited to, a hard disk and an optical disk. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and / or chipsets, such as Bluetooth devices, 802.11 devices, Wi-Fi devices, WiMAX devices, cellular communication devices, and / or the like.

[0103] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the storage system testing method 200. For example, in some embodiments, the storage system testing method 200 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the storage system testing method 200 described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the storage system test method 200 by any other suitable means (e.g., by means of firmware).

[0104] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0105] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0106] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0107] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0108] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or include such backend components, middleware components, or

[0109] A computing system is any combination of front-end components. The components of the system can be interconnected via digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include: Local Area Networks (LANs), Wide Area Networks (WANs), the Internet, and blockchain networks.

[0110] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0111] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0112] While embodiments or examples of this disclosure have been described with reference to the accompanying drawings, it should be understood that the methods, systems, and devices described above are merely exemplary embodiments or examples, and the scope of this disclosure is not limited to these embodiments or examples. Various elements in the embodiments or examples may be omitted or replaced by their equivalents. Furthermore, the steps may be performed in a different order than that described in this disclosure. Further, various elements in the embodiments or examples may be combined in various ways. Importantly, as the technology evolves, many elements described herein can be replaced by equivalents that appear after this disclosure.

Claims

1. A testing method for a storage system, wherein, The storage system includes multiple memories at different levels, and the method includes: Obtain the test path of the storage system and multiple input data for testing the storage system, wherein the test path is a memory sequence starting from the first memory of the multiple memories and ending at the second memory of the multiple memories, and each memory of the multiple memories is divided into multiple storage areas; The plurality of input data are sequentially input into the free storage area of ​​the first memory, so that each of the plurality of input data passes through the free storage area of ​​each memory in the test path and is then output by the second memory; Acquire multiple output data from the second memory; and Based on the multiple input data and the multiple output data, the test results of the storage system are determined.

2. The method according to claim 1, further comprising: For any memory in the test path, determine the number of times the memory appears in the test path; Based on the number of occurrences, the number of storage areas of the memory is determined, wherein the number is positively correlated with the number of occurrences; as well as The memory is divided into the specified number of storage areas.

3. The method according to claim 1 or 2, wherein, The determination of the test results of the storage system based on the multiple input data and the multiple output data includes: The correctness of the storage system is verified by determining whether the multiple input data and the multiple output data are the same.

4. The method according to any one of claims 1-3, wherein, The determination of the test results of the storage system based on the multiple input data and the multiple output data includes: In response to the plurality of input data being identical to the plurality of output data, the data volume of the plurality of input data, the input time of the first input data among the plurality of input data, and the output time of the last output data among the plurality of output data are obtained; and The read / write performance of the storage system is determined based on the data volume, the input time, and the output time.

5. The method according to any one of claims 1-4, wherein, The storage system is a multi-level caching system, and the test path includes the multiple memories, wherein the first memory and the second memory are either the highest-level memory or the lowest-level memory among the multiple memories.

6. A testing apparatus for a storage system, wherein, The storage system includes multiple memories at different levels, and the device includes: The acquisition module is configured to acquire the test path of the storage system and multiple input data for testing the storage system, wherein the test path is a sequence of memories starting from a first memory in the plurality of memories and ending at a second memory in the plurality of memories, and each memory in the plurality of memories is divided into multiple storage areas; The input module is configured to sequentially input the plurality of input data into the free storage area of ​​the first memory, so that each of the plurality of input data is output by the second memory after sequentially passing through the free storage areas of each memory in the test path; The output module is configured to acquire multiple output data from the second memory; and The first determining module is configured to determine the test results of the storage system based on the plurality of input data and the plurality of output data.

7. The apparatus according to claim 6, further comprising: The second determining module is configured to determine the number of times a memory appears in the test path for any memory in the test path. The third determining module is configured to determine the number of storage areas of the memory based on the number of occurrences, wherein the number is positively correlated with the number of occurrences; as well as The partitioning module is configured to divide the memory into the number of storage areas.

8. The apparatus according to claim 6 or 7, wherein, The first determining module includes: The verification unit is configured to verify the correctness of the storage system by determining whether the plurality of input data and the plurality of output data are the same.

9. The apparatus according to any one of claims 6-8, wherein, The first determining module includes: The acquisition unit is configured to, in response to the plurality of input data being identical to the plurality of output data, acquire the data volume of the plurality of input data, the input time of the first input data among the plurality of input data, and the output time of the last output data among the plurality of output data; and The determining unit is configured to determine the read / write performance of the storage system based on the data volume, the input time, and the output time.

10. The apparatus according to any one of claims 6-9, wherein, The storage system is a multi-level caching system, and the test path includes the multiple memories, wherein the first memory and the second memory are either the highest-level memory or the lowest-level memory among the multiple memories.

11. A chip comprising the means as claimed in any one of claims 6-10.

12. An electronic device, comprising: At least one processor; as well as A memory that is communicatively connected to the at least one processor; in The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

13. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

14. A computer program product comprising a computer program, wherein, The computer program, when executed by a processor, implements the method according to any one of claims 1-5.

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