A reconfigurable hybrid-base fft device supporting output pruning

Abstract

The application belongs to the technical field of FFT hardware design and application, and discloses a reconfigurable mixed-base FFT device supporting output pruning, which comprises an FFT processor supporting a calculation mode of an arbitrary 5*2^k input point number and an arbitrary 2^k output point number, at least one reconfigurable operation unit supporting base-5 and base-2 operations, a control unit supporting the calculation mode of the arbitrary 5*2^k input point number and the arbitrary 2^k output point number, a memory management unit supporting 5-point and 4-point parallel reading and writing, and an address generation unit corresponding to the memory management unit supporting 5-point and 4-point parallel reading and writing. The application is reconfigurable hardware design aiming at base-5 base-2 mixed-base algorithm and partial output pruning, supports six reconfigurable operation modules, has no delay in data reading and writing and high bandwidth, greatly reduces resource consumption while ensuring operation performance, and improves hardware utilization.

Description

Technical Field

[0001] This invention belongs to the field of FFT hardware design and application technology, and particularly relates to a reconfigurable hybrid basis FFT device that supports output pruning. Background Technology

[0002] The Fast Fourier Transform (FFT) is an acceleration of the Discrete Fourier Transform (DFT). Compared to the DFT, it is more suitable for implementation in computer systems and is therefore widely used in various digital signal processing applications. The changing requirements of various new scenarios for processing accuracy and speed have also spurred new demands for FFT algorithms and their implementation methods. The radix-2 FFT algorithm is suitable for sampling sequences with a power of 2 of sampling points, offering advantages such as simple implementation and flexible support for sampling point numbers. However, in large-point FFT operations, the radix-2 FFT algorithm's disadvantage in computational speed becomes significant. To address this issue, large-radix FFT algorithms such as the radix-4 FFT and radix-8 FFT have been proposed. These are also suitable for sampling sequences with a power of 2 of sampling points. Increasing the radix can significantly improve computational efficiency and save computation time in large-point operations. However, in many scenarios, the total number of points in the sampled sequence is not necessarily a power of 2. For such cases, simple radix-2, radix-4, and radix-8 algorithms cannot directly handle them. The input sampled sequence needs to be padded with zeros to the nearest power of 2 before performing the FFT operation, or the smaller power of 2 point FFT operation can be performed first, followed by the smaller power of 2 point DFT operation. The former greatly increases redundant computation, leading to a significant increase in computation time; while the latter's computation speed decreases significantly during the DFT stage, further extending the computation time.

[0003] Based on the aforementioned needs, hybrid radix algorithms have significant application potential in many fields. For example, in power quality monitoring, fully digital substation automation systems conforming to the IEC 61850 series standards specify multiple sampling rates, such as 80 or 200 points per cycle, or 1280 or 2560 points per cycle, resulting in sampling sequences with non-power-of-2 points. Furthermore, the zero-padding operation of traditional radix-2 FFT algorithms is not suitable for all scenarios, such as signal processing in synthetic aperture radar spotting mode. In addition, hybrid radix FFT algorithms and corresponding hardware can be applied to LTE systems, audio processing, image processing, and other fields, demonstrating a wide range of applications. However, existing hybrid radix algorithms are mostly based on radix-2 to radix-4 and radix-2 to radix-3, with fewer processors suitable for radix-5 to radix-2 hybrid radix FFTs with 5*2^k points.

[0004] In some scenarios, such as power quality harmonic analysis, seismic data acquisition systems, and narrowband analysis in some signal processing, only a portion of the results needs to be output. That is, the traditional FFT harmonic calculation method, where the number of output points equals the number of input points, results in significant redundant computation in these situations. To address this, pruning operations can be performed on the number of output points to further improve computation speed and shorten computation time.

[0005] Therefore, in many of the above scenarios, there is still a significant gap in the availability of FFT processors suitable for 5*2^k point types that support output pruning hybrid bases. There is considerable room for improvement in terms of computing speed, output point pruning mode support, and the reuse of corresponding hardware resources. Summary of the Invention

[0006] The purpose of this invention is to provide a reconfigurable hybrid-based FFT device that supports output pruning, so as to solve the above-mentioned technical problems.

[0007] To address the aforementioned technical problems, the present invention provides a specific technical solution for a reconfigurable hybrid-based FFT device that supports output pruning, as follows:

[0008] A reconfigurable hybrid radix FFT device supporting output pruning includes an FFT processor that supports any 5*2^k input points and any 2^k output points calculation mode. The FFT processor includes at least a reconfigurable operation unit that supports radix-5 and radix-2 operations, a control unit that supports any 5*2^k input points and any 2^k output points calculation mode, a memory access management unit that simultaneously supports 5-point and 4-point parallel read / write, and an address generation unit corresponding to the memory access management unit that simultaneously supports 5-point and 4-point parallel read / write.

[0009] The reconfigurable computing unit is used to perform all operations, and its operation mode and actions are all completed under the control signal instruction issued by the control unit.

[0010] The control unit determines the calculation mode based on the configured number of points and completes the control of the overall calculation, address generation, and storage access process;

[0011] The address generation unit generates the bank number and address corresponding to the operands required for each operation under the instruction of the control signal generated by the control unit.

[0012] The memory access management unit generates chip select enable, read / write control, and address data assignment operations for the corresponding memory block under the control signal instruction generated by the control unit.

[0013] Furthermore, the reconfigurable arithmetic unit includes two levels of operation and a set of eight inter-level registers. The two levels of operation include four complex multipliers and nine complex adders. After the first level of operation, a set of intermediate data is stored in the inter-level registers. When the second level of operation begins in the next cycle, the corresponding operands are read from the inter-level register set for the second level operation. The result of the second level operation is also stored in the inter-level registers. In the next cycle, the result data is read from the inter-level registers and then written to the corresponding memory address.

[0014] Furthermore, the reconfigurable computing unit can reuse the same set of hardware resources to implement radix-5 operations, radix-2 operations in a 2-way parallel-2-way cascaded manner, and output point pruning mode operations.

[0015] Furthermore, the control unit determines the calculation mode and controls the data flow of the operation through the joint control of the state machine and the counter, thus completing the entire mixed-basis FFT operation.

[0016] Furthermore, the control unit includes a state machine and a three-level counter, which jointly control the working mode and various actions of the entire hardware. The state machine contains 3 groups of 16 states: R5_L, R5_C1, R5_C2LR5, R5_SC1, and R5_C2LR2 are all radix-5 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. The whole process is a four-level pipeline. In the last radix-5 calculation state, R5_C2LR2, the second-level operation of the last radix-5 operation is completed, and the operands for the radix-2 operation of the next cycle are read in advance. R2_SC1R2, R2_C2LR2, R2_SC1, and R2_C2LP are radix-2 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. R2_SC1R2 is the first radix-2 calculation state, and the first radix-2 operation must be completed. The first-level operation of the pruning operation involves writing the last set of radix-5 operation results from the previous cycle into memory. In the last radix-2 operation state R2_C2LP, the second-level operation of the last radix-2 operation is completed, and the operands for the pruning operation of the next cycle are read in advance. P_SC1P, P_C2L, P_SC1, P_C2, and P_S are pruning operation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. P_SC1P is the first pruning operation state, which also completes the first-level operation of the first pruning operation and writes the last set of radix-2 operation results from the previous cycle into memory. P_C2 and P_S correspond to the last pruning operation states. After the calculation is completed, a calculation completion signal is given in the FINISH state.

[0017] Furthermore, the transitions between states are determined by counters. The three-level counters are used to count the current operation's level, group, and butterfly operation number. The counting thresholds for each of the three levels are determined based on the configured values ​​N, MAX_N, A, stage_num, and a_num. MAX_N is the total number of points in this operation; N = MAX_N / 5; and A is the required number of output points for this operation, A = 2. a The above information is all pre-configured content. During runtime, the software configures the corresponding information registers through the AHB bus interface to complete information initialization, and then writes the start signal to start the entire operation. The hardware then completes the entire operation in sequence according to the configured point information.

[0018] Furthermore, the address generation unit supports simultaneously generating bank numbers and addresses for 5 or 4 parallel access data storage devices, and supports simultaneously generating bank numbers and address addresses for 4-way rotation factors, thereby completing the data preparation for each operation.

[0019] Furthermore, the address generation unit includes two functional parts: a data address generation module and a rotation factor address generation module. The data storage is divided into 5 banks. The specific bank number is generated based on the three-level counter information in the control unit. Three index values ​​are used to access the lookup table: index_s comes from the last two digits of the stage counter (stage_cnt), corresponding to the outermost index of the lookup table and the range of the sub-table at the current level; index_b comes from the group counter, representing the current group offset, corresponding to the second-level index of the lookup table, i.e., the starting index of the sub-table. For radix-5 operations, the two-level index can generate the required bank number. For radix-2 operations and pruning operations, index_o is also needed, which comes from the last sub-table content retrieved in the previous step, i.e., the inner header index of the current required bank number. The combination of these three levels of indexes allows access to the lookup table. The required input data bank number is generated before each level of operation. The address generation pattern within each address is the same as the ordinary radix-2 algorithm. Every 5 adjacent data are grouped together, and their addresses are N binary numbers arranged in reverse order. Four original address generation counters are used, which increment automatically after each operation according to natural order. The initial increment step size is 1, and the step size doubles for each level increase. The initial values ​​of the four original address generation counters correspond to the group counters in the bank generation unit. Reversing each bit of the original address yields the true original data address. The output data address, i.e., the write data address, is consistent with the input data address. According to the operation data stream, the corresponding input data address is saved to the output address register. After two cycles, the bank number and address in the address register are written to the corresponding address of the corresponding bank.

[0020] Furthermore, the main body of the rotation factor address generation module is an address counter that increments by 1 in each radix-5 operation. When reading the operand in the last radix-5 operation, the current value is saved as the initial value for the rotation factor address in the radix-2 operation. In the radix-2 operation, the base address of the rotation factor address counter is the saved value of the rotation factor address from the last radix-5 operation. Two step sizes are also required: Step 1 is the same as the index_b generated by the bank number, derived from the group counter, used to record which group the current position is in, serving as the initial offset for the second layer; Step 2 is the self-offset for each operation, incrementing after each operation. The initial increment value is MAX_N / 20, and then gradually increases to half of the previous level. The sum of these three values ​​is the address of the rotation factor in the radix-2 operation mode. The bank number is constant from 0 to 3. In pruning mode, the corresponding address generation module can be bypassed.

[0021] Furthermore, the memory access management unit supports 5-way or 4-way parallel read or write operations on the data storage, and supports 4-way parallel reads on the rotation factor memory. The memory access management unit is a module that converts the bank number and address value of the address generation unit into chip select and read / write access operations for specific memories. According to the contents of the bank number lookup table, it selects the bank number group to be accessed. If there is a number corresponding to a certain RAM bank in the bank number group, the chip select signal of the corresponding bank is pulled low to select the bank, and the address value corresponding to the bank number is assigned to the read data address raddr of the RAM bank. If not, the chip select remains high. The read / write selection of the RAM bank is determined according to the load / store signal from the control unit. When the load signal is high, it is a read operation, and the we_n signal of the RAM bank is low. When the store signal is high, it is a write operation, and the we_n signal of the RAM bank is high. The chip select of the rotation factor memory is effective each time the load signal is high, and the rotation factor address value is assigned to the read data address of the corresponding bank.

[0022] The reconfigurable hybrid radix FFT device and method supporting output pruning of the present invention have the following advantages: The present invention adopts a reconfigurable hardware design for the radix-5 and radix-2 hybrid radix algorithm and partial output pruning, supports 6 reconfigurable operation modules, and provides high bandwidth with zero latency in data reading and writing. While ensuring operation performance, it significantly reduces resource overhead and improves hardware utilization. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the reconfigurable hybrid-based FFT device architecture of the present invention;

[0024] Figure 2 This is a schematic diagram of the reconfigurable computing unit structure of the present invention;

[0025] Figure 3 Input data table for the arithmetic unit element of this invention;

[0026] Figure 4 This is the controller state transition diagram of the present invention;

[0027] Figure 5 This is a schematic diagram of the three-stage control counter of the present invention;

[0028] Figure 6 This is a schematic diagram of the 20-point conflict-free memory access process of the present invention;

[0029] Figure 7 This is the conflict-free data address bank number lookup table of the present invention;

[0030] Figure 8This is a schematic diagram of the address generation unit structure of the present invention;

[0031] Figure 9 This is a schematic diagram of the conflict-free rotation factor address generation module of the present invention. Detailed Implementation

[0032] To better understand the purpose, structure, and function of this invention, the following detailed description of a reconfigurable hybrid-based FFT device supporting output pruning is provided in conjunction with the accompanying drawings.

[0033] like Figure 1 As shown, the present invention provides a reconfigurable hybrid radix FFT device supporting output pruning, comprising an FFT processor supporting any 5*2^k input points and any 2^k output points calculation mode. The FFT processor includes at least a reconfigurable operation unit supporting radix-5 and radix-2 operations, a control unit supporting any 5*2^k input points and any 2^k output points calculation mode, a memory access management unit supporting 5-point and 4-point parallel read / write operations simultaneously, and an address generation unit corresponding to the memory access management unit supporting 5-point and 4-point parallel read / write operations simultaneously.

[0034] The reconfigurable computing unit is used to perform all operations, and its operation mode and actions are all completed under the control signal instructions issued by the control unit.

[0035] The control unit determines the calculation mode based on the configured number of points and completes the control of the overall calculation, address generation, and storage access process;

[0036] The address generation unit generates the bank number and address corresponding to the operands required for each operation under the control signal instruction generated by the control unit.

[0037] The memory access management unit generates operations such as chip select enable, read / write control, and address data assignment for the corresponding memory block under the control signal instructions generated by the control unit.

[0038] The reconfigurable computing unit is implemented with optimized radix-5 operations as its core, reusing the same set of hardware resources to implement radix-2 operations. Only a few selectors and corresponding control signals need to be added to simultaneously support radix-5 operations and 2-way parallel-2-way cascaded radix-2 operations. It also supports output point pruning mode to reduce computational load and shorten computation time. For example... Figure 2As shown, the reconfigurable arithmetic unit includes four complex multipliers, nine complex adders (the positions of add / sub8 in the path are dynamically configured according to the pipeline stage), and a set of eight inter-stage registers. The complete radix-5 operation is divided into two stages, with each stage involving all four complex multipliers and nine complex adders. After the first stage operation, a set of intermediate data is stored in the inter-stage registers. When the second stage operation begins in the next cycle, the corresponding operands are read from the inter-stage register set for the second stage operation. The result of the second stage operation is also stored in the inter-stage registers. In the next cycle, the result data is read from the inter-stage registers and written to the corresponding memory address. This avoids memory read / write resource conflicts during the overall computation process.

[0039] The 2-way parallel-2-way cascaded radix-2 operation is also divided into two stages to optimize timing and shorten the critical path. Each stage uses two complex multipliers and four complex adders. After the first stage, a set of intermediate data is stored in four inter-stage registers. When the second stage begins, the corresponding operands are read from the inter-stage registers for the second stage operation. The result of the second stage is also stored in the four inter-stage registers and written to the corresponding memory address in the next cycle. This avoids memory read / write resource conflicts during the overall computation process.

[0040] In pruning mode, the operation is still divided into two levels. The first level uses two complex adders, and the second level uses one complex adder. Two inter-level registers are used to store the intermediate results of the first-level operation, while only one inter-level register is needed to store the results of the second-level operation. The results are written to the corresponding memory address in the next cycle.

[0041] The input data of each element of the reconfigurable computing unit in each computing mode is as follows: Figure 3 As shown.

[0042] The control unit, through the combined control of a state machine and counters, determines the computation mode, controls the data flow, and completes the entire mixed-basis FFT operation. The control unit includes a state machine and a three-level counter, which jointly control the overall hardware operation mode and various actions. The state machine is as follows: Figure 4As shown, there are 3 groups of 16 states. R5_L, R5_C1, R5_C2LR5, R5_SC1, and R5_C2LR2 are all radix-5 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. The whole process is a four-stage pipeline. In the last radix-5 operation state, R5_C2LR2, the second-level operation of the last radix-5 operation is completed, and the operands for the radix-2 operation of the next cycle are read in advance. R2_SC1R2, R2_C2LR2, R2_SC1, and R2_C2LP are radix-2 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. R2_SC1R2 is the first radix-2 operation state, which completes the first-level operation of the first radix-2 operation and writes the result of the last radix-5 operation of the previous cycle into memory. In the last radix-2 operation state R2_C2LP, the second-level operation of the last radix-2 operation is completed, and the operands for the pruning operation of the next cycle are read in advance. P_SC1P, P_C2L, P_SC1, P_C2, and P_S are pruning operation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. P_SC1P is the first pruning operation state, which also completes the first-level operation of the first pruning operation and writes the last set of radix-2 operation results of the previous cycle into memory. P_C2 and P_S correspond to the last pruning operation states, and after completing the calculation, a calculation completion signal is given in the FINISH state.

[0043] The transition between states is determined by counters, such as three-level counters. Figure 5 As shown, these are used to count the level number, group number, and butterfly operation number of the current operation. The counting thresholds for each of the three counters are determined by the configured N, MAX_N, A, stage_num, and a_num. MAX_N is the total number of points in this operation; N = MAX_N / 5, for example, for MAX_N = 1280, N = 256; A is the required number of output points for this operation, A = 2. a For example, if A=32, then a=5. All of the above information is pre-defined configuration information. During runtime, the software initializes the information by configuring the corresponding information registers through the AHB bus interface, then writes the start signal to initiate the entire operation. The hardware then completes the entire operation sequentially according to the configured point information.

[0044] The address generation unit supports the simultaneous generation of bank numbers and addresses for 5-point or 4-point parallel access data storage, and also supports the simultaneous generation of bank numbers and address addresses for 4-way rotation factors, thus completing the data preparation for each operation. The address generation unit comprises two functional parts: a data address generation module and a rotation factor address generation module. The data storage is divided into 5 banks. Taking 20 points as an example, the conflict-free access storage pattern is as follows: Figure 6 As shown, data with the same color block represents the same group of data accessed in parallel. This access pattern can be implemented using a lookup table, as shown in the example. Figure 7 As shown. The specific bank number is generated based on the three-level counter information in the control unit. Three index values ​​are used to access the lookup table: index_s comes from the last two digits of the stage counter (stage_cnt), corresponding to the outermost index of the lookup table, representing the current level's sub-table range; index_b comes from the group counter, representing the current group offset, corresponding to the second-level index of the lookup table, i.e., the starting index of the sub-table. For radix-5 operations, two levels of indexes are sufficient to generate the required bank number. For radix-2 operations and pruning operations, index_o is also needed, derived from the last element of the previously retrieved sub-table, which is the inner header index of the currently required bank number. Combining these three levels of indexes allows the required input data bank number to be generated before each level of operation by accessing the lookup table.

[0045] The address generation pattern within each address is more obvious, similar to the ordinary radix-2 algorithm. Every five adjacent data points form a group, and their addresses are N in reverse binary order. Therefore, a counter is generated using four original addresses, such as... Figure 8 As shown, the increments sequentially after each operation, with an initial increment step of 1. The step size doubles with each subsequent level. The initial values ​​of the four original address generation counters correspond to the group counters in the bank generation unit. Reversing each bit of the original address yields the actual original data address.

[0046] Since this invention retains the in-situ operation characteristic of the FFT algorithm, the output data address, i.e. the write data address, is consistent with the input data address. According to the operation data stream, the corresponding input data address is saved to the output address register. After two cycles, the corresponding bank address is written to the corresponding address according to the bank number and address in the address register.

[0047] Rotation factor address generation module, such as Figure 9As shown, the main component is an address counter that increments by 1 in each radix-5 operation. The current value is saved when the operand is read during the last radix-5 operation, serving as the initial value for the radix-2 twitch factor address. In the radix-2 operation, the base address of the twitch factor address counter is the saved radix-5 twitch factor address value. Two step sizes are also required: Step 1, similar to the index_b generated by the bank number, comes from the group counter and records the current group, serving as the initial offset for the second layer; Step 2 is the self-offset for each operation, incrementing after each operation with an initial increment of MAX_N / 20, gradually increasing to half the value of the previous level. The sum of these three values ​​is the address of the twitch factor in radix-2 operation mode, where the bank number is constant between 0 and 3. In pruning mode, since multiplication is not involved, there is no need to read the twitch factor; to reduce power consumption, the corresponding address generation module can be bypassed.

[0048] The memory access management unit supports 5-way or 4-way parallel read or write operations on the data memory, and 4-way parallel reads on the rotation factor memory. The memory access management unit is a module that translates the bank number and address value from the address generation unit into chip select and read / write access operations for specific memory. Based on the bank number lookup table, it selects the bank number group to be accessed. If the group contains a corresponding RAM bank number, the chip select signal for that bank is pulled low (active low) to select the bank, and the address value corresponding to that bank number is assigned to the read data address (raddr) of that RAM bank. If not, the chip select remains high. RAM bank read / write selection is determined by the load / store signal from the control unit. When load is high, it's a read operation, and the RAM bank's we_n signal is low (active low). When store is high, it's a write operation, and the RAM bank's we_n signal is high. The rotation factor memory's chip select is active each time the load signal is high, and the rotation factor address value is assigned to the read data address of the corresponding bank.

[0049] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A reconfigurable hybrid-based FFT device supporting output pruning, characterized in that, The system includes an FFT processor that supports any 5*2^k input points and any 2^k output points calculation mode. The FFT processor includes at least a reconfigurable operation unit that supports radix-5 and radix-2 operations, a control unit that supports any 5*2^k input points and any 2^k output points calculation mode, a memory access management unit that simultaneously supports 5-point and 4-point parallel read / write, and an address generation unit corresponding to the memory access management unit that simultaneously supports 5-point and 4-point parallel read / write. The reconfigurable computing unit is used to perform all operations, and its operation mode and actions are all completed under the control signal instruction issued by the control unit. The control unit determines the calculation mode based on the configured number of points and completes the control of the overall calculation, address generation, and storage access process; The address generation unit generates the bank number and address corresponding to the operands required for each operation under the instruction of the control signal generated by the control unit. The memory access management unit generates chip select enable, read / write control, and address data assignment operations for the corresponding memory block under the control signal instruction generated by the control unit. The control unit includes a state machine and a three-level counter, which jointly control the working mode and various actions of the entire hardware. The state machine contains 3 groups of 16 states: R5_L, R5_C1, R5_C2LR5, R5_SC1, and R5_C2LR2 are all radix-5 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. The whole process is a four-level pipeline. In the last radix-5 calculation state, R5_C2LR2, the second-level operation of the last radix-5 operation is completed, and the operands for the radix-2 operation in the next cycle are read in advance. R2_SC1R2, R2_C2LR2, R2_SC1, and R2_C2LP are radix-2 calculation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. R2_SC1R2 is the first radix-2 calculation state, and the first radix-2 operation must be completed. The first-level operation of the pruning operation involves writing the last set of radix-5 operation results from the previous cycle into memory. In the last radix-2 operation state R2_C2LP, the second-level operation of the last radix-2 operation is completed, and the operands for the pruning operation of the next cycle are read in advance. P_SC1P, P_C2L, P_SC1, P_C2, and P_S are pruning operation states. In each state, four operations are performed: reading the state input data, the first-level operation, the second-level operation, and writing the result data. P_SC1P is the first pruning operation state, which also completes the first-level operation of the first pruning operation and writes the last set of radix-2 operation results from the previous cycle into memory. P_C2 and P_S correspond to the last pruning operation states. After the calculation is completed, a calculation completion signal is given in the FINISH state.

2. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The reconfigurable arithmetic unit includes two levels of operation and a set of eight inter-level registers. The two levels of operation include four complex multipliers and nine complex adders. After the first level of operation, a set of intermediate data is stored in the inter-level registers. When the second level of operation begins in the next cycle, the corresponding operands are read from the inter-level register set for the second level operation. The result of the second level operation is also stored in the inter-level registers. In the next cycle, the result data is read from the inter-level registers and then written to the corresponding memory address.

3. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The reconfigurable computing unit can perform radix-5 operations, radix-2 operations in parallel and 2-way cascaded configurations, and output point pruning mode operations by reusing the same set of hardware resources.

4. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The control unit determines the calculation mode and controls the data flow to complete the entire mixed-basis FFT operation through the joint control of the state machine and the counter.

5. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The transition between states is determined by counters. The three-level counters are used to count the current operation's stage number, group number, and butterfly operation number, respectively. The counting thresholds for each of the three levels of counters are determined based on the configured values ​​N, MAX_N, A, stage_num, and a_num. MAX_N is the total number of points in this operation; N = MAX_N / 5; and A is the required number of output points for this operation; A = 2. a The above information is all pre-configured content. During runtime, the software configures the corresponding information registers through the AHB bus interface to complete information initialization, and then writes the start signal to start the entire operation. The hardware then completes the entire operation in sequence according to the configured point information.

6. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The address generation unit supports generating bank numbers and addresses for 5 or 4 parallel access data storage devices simultaneously, and supports generating bank numbers and address addresses for 4-way rotation factors simultaneously, thereby completing the data preparation for each operation.

7. The reconfigurable hybrid-based FFT device according to claim 6, characterized in that, The address generation unit comprises two functional parts: a data address generation module and a rotation factor address generation module. The data storage is divided into 5 banks. The specific bank number is generated based on the three-level counter information in the control unit. Three index values ​​are used to access the lookup table: index_s comes from the last two digits of the stage counter (stage_cnt), corresponding to the outermost index of the lookup table and the range of the sub-table at the current level; index_b comes from the group counter, representing the current group offset, corresponding to the second-level index of the lookup table, i.e., the starting index of the sub-table. For radix-5 operations, the two-level index can generate the required bank number. For radix-2 operations and pruning operations, index_o is also needed, which comes from the last element of the previously retrieved sub-table, i.e., the inner header index of the currently required bank number. The combination of these three levels of indexes allows access to the lookup table using... The formula generates the required input data bank number before each level of operation. The address generation pattern within each address is the same as the ordinary radix-2 algorithm. Every 5 adjacent data are grouped together, and their addresses are N binary numbers arranged in reverse order. Four original address generation counters are used, which increment automatically after each operation according to natural order. The initial increment step size is 1, and the step size doubles for each level increase. The initial values ​​of the four original address generation counters correspond to the group counters in the bank generation unit. Reversing each bit of the original address yields the true original data address. The output data address, i.e., the write data address, is consistent with the input data address. According to the operation data stream, the corresponding input data address is saved to the output address register. After two cycles, the bank number and address in the address register are written to the corresponding address of the corresponding bank.

8. The reconfigurable hybrid-based FFT device according to claim 7, characterized in that, The main body of the twitch factor address generation module is an address counter that increments by 1 in each radix-5 operation. When reading operands for the last radix-5 operation, the current value is saved as the initial value for the radix-2 twitch factor address. In the radix-2 operation, the base address of the twitch factor address counter is the saved radix-5 twitch factor address value. Two step sizes are also required: Step 1 is the same as the index_b generated by the bank number, derived from the group counter, used to record which group the current position is in, serving as the initial offset for the second layer; Step 2 is the self-offset for each operation, incrementing after each operation. The initial increment value is MAX_N / 20, and then gradually increases to half of the previous level. The sum of these three values ​​is the address of the twitch factor in the radix-2 operation mode. The bank number is constant from 0 to 3. In pruning mode, the corresponding address generation module can be bypassed.

9. The reconfigurable hybrid-based FFT device according to claim 1, characterized in that, The memory access management unit supports 5-way or 4-way parallel read or write operations on the data memory, and supports 4-way parallel reads on the rotation factor memory. The memory access management unit is a module that converts the bank number and address value of the address generation unit into chip select and read / write access operations for specific memories. According to the contents of the bank number lookup table, it selects the bank number group to be accessed. If there is a number corresponding to a certain RAM bank in the bank number group, the chip select signal of the corresponding bank is pulled low to select the bank, and the address value corresponding to the bank number is assigned to the read data address raddr of the RAM bank. If not, the chip select is kept high. The read / write selection of the RAM bank is determined according to the load / store signal from the control unit. When the load signal is high, it is a read operation, and the we_n signal of the RAM bank is low. When the store signal is high, it is a write operation, and the we_n signal of the RAM bank is high. The chip select of the rotation factor memory is effective every time the load signal is high, and the rotation factor address value is assigned to the read data address of the corresponding bank.

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