A method for fast extraction of interconnection inductance and resistance based on partial element equivalent circuit
By employing a fast and direct solution method based on partial equivalent circuits, combined with mesh analysis and an improved M-HODLR technique, the traditional method of moments (MoM) is improved in electromagnetic simulation of large-scale interconnect structures. This method increases computational efficiency and reduces computational resource consumption, solves the problem of poor convergence in ill-conditioned matrix iteration, and achieves efficient extraction of interconnect inductance and resistance parameters.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2023-08-21
- Publication Date
- 2026-07-21
Smart Images
Figure CN117195780B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of interconnect parameter extraction technology in high-speed integrated circuits, and particularly relates to electromagnetic modeling of three-dimensional interconnects and integrated passive devices in integrated packaging structures. Specifically, it provides a method for rapid extraction of interconnect inductance and resistance based on the equivalent circuit of partial elements. Background Technology
[0002] High-speed integrated circuit (IC) packaging technology, as a solution that enables multifunctionality, miniaturization, and low power consumption, has broad development and application potential. In the packaging structure of high-speed ICs, interconnects and integrated passive components play a crucial role in realizing the complete circuit's functionality. As signal operating frequencies gradually increase to microwave and even millimeter-wave bands, the electromagnetic wave effects of signals on interconnects become increasingly significant. High-speed signals transmitted on interconnects will experience signal integrity issues such as shape distortion, amplitude attenuation, and crosstalk noise, thus affecting the overall chip performance. At high frequencies, the current distribution within lossy conductors is highly uneven due to the skin effect and proximity effect; therefore, the structural design of interconnects and integrated passive components relies more heavily on accurate electromagnetic field simulation.
[0003] As chip integration and semiconductor process standards gradually improve, the scale of interconnect structures is becoming increasingly refined and their size increasingly large. The increase in circuit integration leads to increased interconnect density and stronger coupling between different parts. For large-scale complex interconnect structures, fine meshing is usually required. In the process of performing full-wave electromagnetic simulation on the entire circuit model to extract the interconnect parameters of the conductor target, a large number of unknowns will be introduced during numerical calculation. If the traditional method of moments is used, this problem will be difficult to solve. Based on this, the present invention provides a method for rapid extraction of interconnect inductance and resistance based on the equivalent circuit of partial elements. Summary of the Invention
[0004] The purpose of this invention is to provide a fast method for extracting interconnect inductance and resistance based on Partial Element Equivalent Circuit (PEEC), which addresses the problem of low computational efficiency caused by introducing numerous unknowns when using the PEEC method to extract interconnect parameters in electromagnetic simulations of large-scale interconnect structures. This invention employs a fast and direct solution method, enabling rapid extraction of interconnect inductance and resistance parameters for passive lossy conductors in high-speed circuits.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] A method for rapidly extracting interconnect inductance and resistance based on partial element equivalent circuits, characterized by comprising the following steps:
[0007] S01: Mesh generation for passive lossy conductor targets;
[0008] S02: Construct the circuit model of the target and the corresponding matrix equations using the PEEC method;
[0009] S03: Improve matrix equations using mesh analysis technology;
[0010] S04: Combine the stacked off-diagonal low-rank matrix method (M-HODLR) to quickly solve the matrix equation and extract interconnect parameters.
[0011] Furthermore, the specific process of step S01 is as follows:
[0012] S011: Use a hexahedral mesh to discretize the volumetric interior of the target region;
[0013] S012: Use a quadrilateral mesh to discretize the boundary of the target region.
[0014] Furthermore, the specific process of step S02 is as follows:
[0015] S021: Solve Maxwell's equations based on the principle of volume equivalence, replace the passive lossy conductor target in space with a numerical equivalent source, determine the relationship between the volume equivalent source and the spatial field distribution, and then construct the mixed potential form of the volume integral equation based on the constitutive relation.
[0016] S022: Discretize the equivalent circuit of the passive lossy conductor target: For a uniform lossy conductor, the equivalent volume current element is discretized using the volume grid in S011 combined with the vector pulse basis function, and the equivalent surface charge element is discretized using the surface grid in step S012 combined with the scalar pulse basis function.
[0017] S023: Using the Galerkin matching method, the weight function is selected from the volume basis function formed after discretizing the equivalent volume current element in step S022. The branch potential difference equation and the node current equation of the potential node are constructed to obtain the circuit model of the passive lossy conductor target.
[0018] S024: Construct matrix equations based on the circuit model and node analysis method in step S023.
[0019] Furthermore, the specific process of step S03 is as follows:
[0020] S031: Construct independent meshes: Treat each volume element obtained by discretizing the current source, voltage source, and S022 as a branch. There is a loop current inside the branch that forms a loop. Define a loop that does not contain other branches as an independent mesh.
[0021] S032: Construct a mesh matrix based on the relationship between each branch of the circuit and the independent mesh, and establish the relationship between the loop voltage and current of the independent mesh and the branch voltage and current, thereby replacing the original unknowns and obtaining the improved matrix equation.
[0022] Furthermore, the specific process of step S04 is as follows:
[0023] S041: Based on the geometric relationship between the independent meshes in S031, the independent meshes are grouped and sorted using the binary tree method. Based on the grouping results, the system matrix in S032 is divided into a stacked M-HODLR structure.
[0024] S042: Based on the extensibility compatibility condition, determine whether each off-diagonal matrix block of M-HODLR in S041 satisfies the far-field condition. If not, perform down-segmentation on the off-diagonal matrix block and repeat the above process until the leaf layer. Then, perform full-array filling on the diagonal block matrix of the leaf layer and use the ACA low-rank compression approximation on the off-diagonal block matrix.
[0025] S043: The structure of the system matrix is restored to the M-HODLR structure divided in step S041 by using the uplink aggregation method on the matrix blocks that have been downlinked.
[0026] S044: Decompose M-HODLR and find its inverse: Decompose M-HODLR into the form of a product of multiple block diagonal matrices. Use the SMW formula to find the inverse of the block diagonal matrices in the non-leaf layer and use LU decomposition to find the inverse of the block diagonal matrices in the leaf layer.
[0027] S045: Solve the matrix equation and extract the interconnect inductance and resistance: Apply voltage excitation to the port of the passive lossy conductor target to obtain the right-hand side of the matrix equation. Based on the result of S044, solve the matrix equation to obtain the loop current. Based on the relationship between the loop current and the excitation voltage, extract the interconnect inductance and resistance of the passive lossy conductor target.
[0028] Based on the above technical solution, the beneficial effects of the present invention are as follows:
[0029] This invention provides a method for rapid extraction of interconnect inductance and resistance based on partial element equivalent circuits, which has the following advantages:
[0030] 1) This invention adopts a direct solution method, which can solve the problem that ill-conditioned matrix iteration is difficult to converge in conventional iterative methods. At the same time, it does not require repeated calculations for multi-port excitation problems, which greatly improves the efficiency of computation.
[0031] 2) This invention introduces the M-HODLR method into the analysis of on-chip structures, which effectively reduces the complexity of solving matrices, improves the efficiency of solving large-scale problems, and reduces the computational resource consumption required for solving the problem;
[0032] 3) This invention combines mesh analysis with the M-HODLR method, which reduces the number of unknowns and the dimension of the system matrix on the one hand, and overcomes the incompatibility between the natural block characteristics of the MNA equation formed by PEEC and the M-HODLR matrix on the other hand. Attached Figure Description
[0033] Figure 1 This is a flowchart illustrating the rapid extraction method for interconnect inductance and resistance based on the equivalent circuit of partial elements in this invention.
[0034] Figure 2 This is a schematic diagram of the mesh generation principle in this invention, wherein (a) is the target entity to be meshed, (b) is the hexahedral body mesh generation corresponding to the current direction, and (c) is the quadrilateral face mesh generation corresponding to the current direction.
[0035] Figure 3 This is a simplified schematic diagram of the PEEC single-π electromagnetic model in this invention.
[0036] Figure 4 This is a schematic diagram of the binary tree grouping method in the fast direct solution method of this invention.
[0037] Figure 5 This is a schematic diagram of the stacked structure of M-HODLR in the fast direct solution method of the present invention.
[0038] Figure 6 This is a schematic diagram of the 3-level matrix decomposition method of M-HODLR in the fast direct solution method of this invention.
[0039] Figure 7 This is a schematic diagram of the spiral inductor model in Embodiment 1 of the present invention.
[0040] Figure 8 This is a comparison chart showing the extraction results of the interconnect inductance and resistance of the spiral inductor model in Embodiment 1 of the present invention. Detailed Implementation
[0041] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.
[0042] Example 1
[0043] This embodiment provides a method for rapid extraction of interconnect inductance and resistance based on partial element equivalent circuits, the process of which is as follows: Figure 1 As shown, the main steps include: forming a partial equivalent circuit model of the passive lossy conductor target; constructing the circuit matrix equation based on Kirchhoff's laws; solving the matrix equation using a fast direct solution method and extracting interconnect parameters; specifically, the following steps are included:
[0044] S01: Effective mesh generation for passive lossy conductor targets;
[0045] S02: Construct the circuit model of the target and the corresponding matrix equations using the PEEC method;
[0046] S03: Improve matrix equations using mesh analysis technology;
[0047] S04: Combine the improved hierarchically off-diagonal low-rank matrix (M-HODLR) method to quickly solve the matrix equation and extract the interconnection parameters.
[0048] Furthermore, in step S01, the specific process of effectively meshing the passive lossy conductor target is as follows:
[0049] S011: Use a hexahedral mesh to discretize the volumetric interior of the target region;
[0050] S012: Use a quadrilateral mesh to discretize the boundary of the target region.
[0051] Furthermore, with Figure 2 Taking the lossy conductor block shown in (a) as an example, the specific process of meshing the target in step S01 is as follows:
[0052] like Figure 2 As shown in (b), a hexahedron is used to discretize the interior of the target region. N partition sections are taken at equal intervals along the current direction of the conductor, and the length between each section is l. Since the skin effect and proximity effect will affect the current distribution in the conductor cross section, and the current density gradually tends to the conductor surface as the frequency increases, in order to accurately simulate this non-uniform current distribution, it is necessary to perform precise partitioning on the conductor cross section.
[0053] To reflect the difference in current density across the conductor's cross-section, the width w in the direction of the outermost volume grid cross-section of the conductor is... out It is usually less than or equal to δ / 2, where δ is the skin depth of the conductor, which is related to the operating frequency f, the conductor's conductivity s, and its permeability μ.
[0054]
[0055] When using a volume mesh to partition the inner layer of a conductor, the width in the cross-sectional direction can adopt the same integrated partitioning strategy as the outer layer mesh, but this will generate a large number of unknowns; alternatively, a coarse partitioning strategy can be used, such as a proportional partitioning with a coefficient of β or a length of 2w. outWhile equidistant partitioning can reduce solution accuracy to some extent, this embodiment employs an integrated partitioning strategy.
[0056] like Figure 2 As shown in (c), quadrilaterals are used to discretize the interior of the target area. On the N partitioned sections formed during the volume partitioning process, N+1 partitioning nodes are formed by translating l / 2 along the current direction. At the partitioning nodes at the conductor edge, four quadrilaterals with a length of l / 2 are used to partition the four outer surfaces of the lossy conductor. At the partitioning nodes in the middle of the conductor, four quadrilaterals with a length of l are used to partition the four outer surfaces of the lossy conductor.
[0057] Furthermore, in step S02, the specific process of constructing the target circuit model and corresponding matrix equations using the PEEC method is as follows:
[0058] S021: Solve Maxwell's equations based on the principle of volume equivalence, replace the passive lossy conductor target in space with a numerical equivalent source, establish the relationship between the volume equivalent source and the spatial field distribution, and then construct the hybrid potential form of the volume integral equation based on the constitutive relation.
[0059] S022: Discretize the equivalent circuit of a passive lossy conductor target;
[0060] For a uniform passive lossy conductor, the equivalent volume current element is discretized using the volume grid in S011 combined with the vector pulse basis function, and the equivalent surface charge element is discretized using the surface grid in step S012 combined with the scalar pulse basis function.
[0061] S023: Using the Galerkin matching method, the weight function is selected from the volume basis function formed after discretizing the equivalent volume current element in step S022. The branch potential difference equation and the node current equation of the potential node are constructed to obtain the circuit model of the passive lossy conductor.
[0062] S024: Construct the matrix equation based on the results of step S023 and the node analysis method.
[0063] Furthermore, in step S02, the PEEC method is used to construct the target circuit model as follows: Figure 3 As shown, each volume element corresponds to a branch consisting of partial inductance and partial resistance, and each surface element corresponds to a potential node. The matrix equation constructed using the Modified Nodal Analysis (MNA) method is as follows:
[0064]
[0065] Where j is the imaginary unit; w is the operating angular frequency; Pp is a partial potential matrix, and the element Pp in the m-th row and n-th column of Pp is...mn The physical meaning is: the effect of the accumulation of static charge on the nth surface charge unit on the potential at the mth potential node; the distributed capacitance matrix between each surface charge unit can be obtained by inverting the Pp matrix; A is the correlation matrix established based on the connection relationship between the potential node and the branch. T Let A be the transpose of A; L is a partial inductance matrix, and the element in the m-th row and n-th column of L is L_m. mn The physical meaning is: the contribution of a portion of the current in the nth branch to the voltage drop across the mth branch; when m = n, it represents partial self-inductance; when m ≠ n, it represents partial mutual inductance; R is a partial resistance matrix, with off-diagonal elements being 0, and the mth diagonal element R... m The physical meaning of φ is: the partial resistance of the m-th individual unit; n I represents the voltage vector composed of the voltages at each potential node; b I represents the current vector composed of the currents in each branch; s The node current vector is 0 when the node is not connected to the excitation current source branch, and equal to the amplitude of the excitation current source otherwise.
[0066] Specifically, in step S03, the process of improving the matrix equation using mesh analysis technology is as follows:
[0067] S031: Construct independent meshes;
[0068] Each volume element obtained by discretizing the current source, voltage source, and S022 is regarded as a branch. There is a loop current inside the branch that forms a loop. A loop that does not contain other branches is defined as an independent mesh.
[0069] S032: Construct a mesh matrix based on the relationship between each branch of the circuit and the independent mesh, and establish the relationship between the loop voltage and current of the independent mesh and the branch voltage and current, thereby replacing the original unknowns and improving the matrix equation.
[0070] Furthermore, in step S03, the specific process of improving the matrix equation using mesh analysis technology is as follows:
[0071] After the volume basis functions formed by the discrete volume equivalent elements in S022, for the second equation in the MNA equations in S024:
[0072] (jwL+R)I b -A T φ n =0
[0073] Because of A T φ n The voltage drop of each branch is represented by V. b After substitution, the above equation transforms into:
[0074] (jwL+R)I b =V b
[0075] Analysis of the above equations shows that if a bias voltage is applied across the entire passive lossy conductor target, the excitation voltage V on each branch will be... b It is difficult to determine; if bias voltages are applied separately, the number of equations will increase significantly; therefore, this invention adopts the mesh analysis method, defining loops in the circuit model constructed by S023 that do not contain other branches as independent meshes, and taking the loop current I inside each independent mesh as the value. m and the loop voltage V m As an unknown quantity, replace the branch current I in the original MNA equation. b and branch voltage drop V b This method not only reduces the number of unknowns, but also avoids the problem of a significant increase in unknowns after segmenting the conductor.
[0076] Introducing a mesh matrix Where, N n N is the number of independent mesh openings. m Let be the number of branches; the mesh matrix is defined as follows:
[0077]
[0078] In the formula, i represents the i-th mesh, and j represents the j-th branch. This represents the unit direction vector of the j-th branch. This represents the unit reference direction vector for the i-th mesh.
[0079] The mesh loop voltage vector V can be obtained through the mesh matrix. m Replace the branch voltage drop vector V b Using the mesh loop current vector I m Replace branch current vector I b The matrix equation is improved using mesh analysis technology as follows:
[0080]
[0081] This method reduces the number of unknowns and improves computational efficiency. Furthermore, it replaces the naturally partitioned matrix in the MNA equations with a dense system matrix Z = M(jwL+R)M. T Alternatively, the system matrix can be solved using a fast, direct solution algorithm, laying the foundation for the next step.
[0082] Furthermore, in step S04, the specific process of solving the matrix equation and extracting the interconnection parameters using the M-HODLR fast direct solution method is as follows:
[0083] S041: Based on the geometric relationship between the independent meshes in S031, the independent meshes are grouped and sorted using the binary tree method. Based on the grouping results, the system matrix in S032 is divided into the M-HODLR form of the stacked structure.
[0084] S042: Based on the extensibility compatibility condition, determine whether each off-diagonal matrix block of M-HODLR in S041 satisfies the far-field condition. If not, perform down-segmentation on the off-diagonal matrix block and repeat the above process until the leaf layer. Then, perform full-array filling on the diagonal block matrix of the leaf layer and use the ACA low-rank compression approximation on the off-diagonal block matrix.
[0085] S043: The structure of the system matrix is restored to the M-HODLR structure divided in step S041 by using the uplink aggregation method on the matrix blocks that have been downlinked.
[0086] S044: Decompose M-HODLR and find its inverse;
[0087] The M-HODLR is decomposed into a product of multiple block diagonal matrices. The SMW formula is used to invert the block diagonal matrices of the non-leaf layer, and the LU decomposition is used to directly invert the block diagonal matrices of the leaf layer.
[0088] S045: Solve the matrix equations and extract the interconnect inductance and resistance;
[0089] Voltage excitation is applied to the port of the passive lossy conductor target to obtain the right-hand side of the matrix equation. Based on the result of S044, the matrix equation is solved to obtain the loop current. Based on the relationship between the loop current and the excitation voltage, the interconnect inductance and resistance of the passive lossy conductor target are extracted.
[0090] Furthermore, in step S04, the more specific process of solving the matrix equation and extracting the interconnection parameters using the M-HODLR fast direct solution method is as follows:
[0091] In S032, the system matrix Z = M(jwL+R)M T Before reorganizing into an M-HODLR structure, it is necessary to group the independent meshes according to their geometric relationships. The grouping algorithm uses a binary tree grouping technique, such as... Figure 4 As shown, each subdivision divides the individual meshes within a mesh group equally; based on the grouping results of the individual meshes, the system matrix is reordered and divided to reassemble it into a stacked structure of M-HODLR, as follows. Figure 5 As shown;
[0092] The original HODLR method uses ACA compression to approximate all off-diagonal block matrices. However, most off-diagonal block matrices are not formed by geometrically distant mesh group couplings. Directly using ACA compression is not only inefficient and difficult to guarantee accuracy, but also drastically increases the required computational resources. Therefore, this invention uses the M-HODLR method, utilizing the Extended Admissibility Condition (EAC) to determine whether each off-diagonal matrix block in M-HODLR is a coupling between far-field mesh groups.
[0093]
[0094] Among them, B i and B j These are the largest boxes enclosing mesh groups i and j, respectively. `diam(·)` represents the geometric diameter of the mesh group, and `dist(·,·)` represents the source mesh group (B...). i ) and test mesh group (B j The geometric distance between ) and η is a preset positive real number, i m and j n This represents a subgroup of mesh groups i and j, and the values of m and n are in the range of 1 or 2;
[0095] For matrix blocks that do not meet the extensibility compatibility condition, perform down-level partitioning, i.e., continue partitioning them using the binary tree algorithm, repeating the above process until the leaf level; for all matrix blocks that meet the extensibility compatibility condition, use ACA approximate compression storage:
[0096]
[0097] in, Let Z represent the matrix block formed by the coupling between the i-th mesh group (group i) and the j-th mesh group (group j) in the system matrix Z. The dimension of the matrix block is m×n. After ACA approximate compression storage, It is approximately in the form of a product of two matrices, where the dimension of matrix U is m×r and the dimension of matrix V is r×n, and r is much smaller than m and n;
[0098] The downlink partitioning process divides off-diagonal matrix blocks that do not meet the far-field condition. This process effectively improves the computational efficiency and accuracy of M-HODLR, but it also destroys the original M-HODLR structure. Therefore, uplink aggregation is required on the partitioned matrices, as follows:
[0099]
[0100] in, This represents the matrix block formed by the coupling between the i-th mesh group (group i) and the j-th mesh group (group j) in the l-th layer of the M-HODLR without downlink segmentation; Indicates to The matrix block formed by the coupling between the (l+1)th layer, the k1th mesh group (group k1), and the k2th mesh group (group k2) after downlink segmentation is represented by ACA compression, where group k1 and group k2 are subgroups of group i and group j, respectively.
[0101] Through the above process, the four small matrix blocks of the (l+1)th layer formed after the downlink segmentation are aggregated into the lth layer. The form of multiplying two matrices; due to aggregation and Since the matrix contains a large number of zero elements, in order to improve computational efficiency, the QR-SVD recompression method is used to compress it separately to reduce the approximate rank of the matrix.
[0102] After obtaining the compressed form of M-HODLR using the above method, it can be decomposed into a product of several diagonal matrices, such as... Figure 6 As shown; ultimately, the solution to the matrix equations in S032 can be obtained by multiplying the inverses of these block diagonal matrices by the excitation terms on the right side:
[0103]
[0104] In this method, a non-zero bias voltage V0 is applied to each port of the passive lossy conductor target to achieve voltage excitation. When a bias voltage is applied to one port, the other ports are grounded. Thus, the excitation term V on the right side can be obtained. m ; This represents the block diagonal matrix of the l-th layer; for the block diagonal matrix of the leaf layer... Its inverse matrix can be directly obtained by LU decomposition; for the block diagonal matrix of non-leaf layers, its inverse matrix can be solved using the SMW formula, i.e.:
[0105]
[0106]
[0107] in, Represents the block diagonal matrix after decomposition. The i-th diagonal block matrix in the matrix, where E represents the identity matrix. express The compressed representation is obtained by finding the block diagonal matrix. After obtaining the inverse of each diagonal block matrix, the block diagonal matrix... The inverse matrix can be obtained directly; using the SMW formula to invert the matrix can effectively reduce the dimension of the inverted matrix and improve the solution efficiency.
[0108] The loop current vector I of each individual mesh is obtained by solving the matrix equations using the fast direct solution method M-HODLR. m Then, the interconnect inductance and resistance of the passive lossy conductor target can be extracted based on the relationship between the loop current and the excitation voltage; taking a two-port network as an example, the independent mesh containing all potential nodes inside the port is defined as the total loop mesh, from I m Extract the loop current I inside the mesh. total The interconnect inductance and interconnect resistance of a passive lossy conductor target can be extracted by combining the following relationships:
[0109]
[0110] In the formula, L x For the target interconnect self-inductance, R x For the interconnect self-resistance of the target, Im(X) represents the imaginary part of X, and Re(X) represents the real part of X; multiport networks are similar, when V0 and I total When the excitation voltage and the loop current inside the total loop mesh are respectively corresponding to the excitation voltage of different ports, the calculation results represent the interconnection mutual inductance and interconnection mutual resistance between the corresponding parts of the two ports of the passive lossy conductor target.
[0111] like Figure 8 The figure shows the interconnection parameters of the free-space spiral inductor extracted using the method of this invention, where (a) is resistance and (b) is inductance. The structure of the spiral inductor is as follows. Figure 7 As shown, the proposed method was compared with MoM and FastHenry methods. The results show that the proposed method has higher accuracy in extracting the frequency-varying resistance and inductance of interconnects. Furthermore, in the extraction of parasitic parameters at a single frequency point, FastHenry took 110.4 seconds and consumed 286.36 MB of memory, while the M-HODLR method took 68.5 seconds and consumed 10.33 MB of memory, representing a 38% improvement in computational efficiency and a 96.4% reduction in memory consumption.
[0112] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.
Claims
1. A method for rapid extraction of interconnect inductance and resistance based on partial element equivalent circuits, characterized in that, Includes the following steps: S01: Mesh generation for passive lossy conductor targets; S02: Construct the circuit model of the target and the corresponding matrix equations using the PEEC method; S03: Improve the matrix equation using mesh analysis technology; the specific process is as follows: S031: Constructing independent meshes: Treat each volume element obtained by discretizing the current source, voltage source, and S02 as a branch. There is a loop current inside the branch that forms a loop. Define a loop that does not contain other branches as an independent mesh. S032: Construct a mesh matrix based on the relationship between each branch of the circuit and the independent mesh, and establish the relationship between the loop voltage and current of the independent mesh and the branch voltage and current, thereby replacing the original unknowns and obtaining the improved matrix equation. S04: Using a stacked off-diagonal low-rank matrix method to quickly solve matrix equations and extract interconnection parameters; the specific process is as follows: S041: Based on the geometric relationship between the independent meshes in S031, the independent meshes are grouped and sorted using the binary tree method. Based on the grouping results, the system matrix in S032 is divided into a stacked M-HODLR structure. S042: Based on the extensibility compatibility condition, determine whether each off-diagonal matrix block of M-HODLR in S041 satisfies the far-field condition. If not, perform down-segmentation on the off-diagonal matrix block and repeat the above process until the leaf layer. Then, perform full-array filling on the diagonal block matrix of the leaf layer and use the ACA low-rank compression approximation on the off-diagonal block matrix. S043: The structure of the system matrix is restored to the M-HODLR structure divided in step S041 by using the uplink aggregation method on the matrix blocks that have been downlinked. S044: Decompose M-HODLR and find its inverse: Decompose M-HODLR into the form of a product of multiple block diagonal matrices. Use the SMW formula to find the inverse of the block diagonal matrices in the non-leaf layer and use LU decomposition to find the inverse of the block diagonal matrices in the leaf layer. S045: Solve the matrix equation and extract the interconnect inductance and resistance: Apply voltage excitation to the port of the passive lossy conductor target to obtain the right-hand side of the matrix equation. Based on the result of S044, solve the matrix equation to obtain the loop current. Based on the relationship between the loop current and the excitation voltage, extract the interconnect inductance and resistance of the passive lossy conductor target.
2. The method for rapid extraction of interconnect inductance and resistance based on partial element equivalent circuits as described in claim 1, characterized in that, The specific process of step S01 is as follows: S011: Use a hexahedral mesh to discretize the volumetric interior of the target region; S012: Use a quadrilateral mesh to discretize the boundary of the target region.
3. The method for rapid extraction of interconnect inductance and resistance based on partial element equivalent circuits as described in claim 2, characterized in that, The specific process of step S02 is as follows: S021: Solve Maxwell's equations based on the principle of volume equivalence, replace the passive lossy conductor target in space with a numerical equivalent source, determine the relationship between the volume equivalent source and the spatial field distribution, and then construct the mixed potential form of the volume integral equation based on the constitutive relation. S022: Discretize the equivalent circuit of the passive lossy conductor target: For a uniform lossy conductor, the equivalent volume current element is discretized using the volume grid in S011 combined with the vector pulse basis function, and the equivalent surface charge element is discretized using the surface grid in step S012 combined with the scalar pulse basis function. S023: Using the Galerkin matching method, the weight function is selected from the volume basis function formed after discretizing the equivalent volume current element in step S022. The branch potential difference equation and the node current equation of the potential node are constructed to obtain the circuit model of the passive lossy conductor target. S024: Construct matrix equations based on the circuit model and node analysis method in step S023.