Bus verification method and verification intellectual property core system

Abstract

The embodiment of the application provides a bus verification method and a verification intellectual property core system, and relates to the chip technical field. The method is applied to the verification of the intellectual property core system. The verification intellectual property core system comprises a first acquisition component, a second acquisition component, a driving component and a verification component. The first acquisition component and the second acquisition component are connected with the verification component respectively. The method comprises the following steps: the driving component drives a data packet to a circuit under test; the first acquisition component acquires a first signal of the driving component sending the data packet to the circuit under test; the second acquisition component acquires a second signal of the circuit under test sending a received data packet to the driving component; the verification component acquires the first signal from the first acquisition component and acquires the second signal from the second acquisition component; and the circuit under test is verified based on the first signal and the second signal. By applying the technical scheme provided by the embodiment of the application, the time consumption of building a VIP can be reduced, the labor cost of building the VIP can be reduced, and the quality of the VIP can be improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a bus verification method and a verification intellectual property core system. Background Technology

[0002] In chip design, various interface buses serve as crucial bridges for communication between modules or dies. These interface buses vary in complexity, and the specific requirements of each chip project also differ. Bus verification requires building one or more VIPs (Verification IPs) based on the chip project's needs. The complexity of VIPs for different interface buses is generally high, and using complex VIPs incurs significant learning costs for verification personnel, greatly increasing labor costs. Furthermore, VIP construction is time-consuming, and VIP quality is difficult to guarantee. Summary of the Invention

[0003] The purpose of this application is to provide a bus verification method and a system for verifying intellectual property rights, so as to reduce the time required for VIP (Virtual Property) setup, reduce the labor cost of VIP setup, and improve VIP quality. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a bus verification method applied to an intellectual property verification system. The intellectual property verification system includes a first acquisition component, a second acquisition component, a driver component, and a verification component, wherein the first acquisition component and the second acquisition component are respectively connected to the verification component; the method includes:

[0005] The driving component drives data packets to the circuit under test;

[0006] The first acquisition component acquires the first signal of the data packet sent by the driving component to the circuit under test;

[0007] The second acquisition component acquires the second signal sent by the circuit under test to the driving component to receive the data packet;

[0008] The verification component acquires the first signal from the first acquisition component and the second signal from the second acquisition component; based on the first signal and the second signal, it verifies the circuit under test.

[0009] In some embodiments, the first signal indicates that the driving component has sent a data packet, and the second signal indicates that the circuit under test has received the data packet; the verification component includes a flow control sub-component.

[0010] The verification component verifies the circuit under test based on the first signal and the second signal, including:

[0011] After receiving the first signal, the flow control sub-component decrements the value of the preset counter by 1; after receiving the second signal, it increments the value of the preset counter by 1; and when the value of the preset counter is less than a set threshold, it outputs an error alarm.

[0012] In some embodiments, the first signal indicates whether the driving component is ready to send the data packet, and the second signal indicates whether the circuit under test is ready to receive the data packet; the verification component includes a flow control sub-component.

[0013] The verification component verifies the circuit under test based on the first signal and the second signal, including:

[0014] The flow control sub-component outputs an error alarm when the first signal and the second signal meet preset conditions;

[0015] The preset conditions are as follows:

[0016] The first signal indicates that the driving component is ready to send the data packet, and the second signal indicates that the circuit under test is not ready to receive the data packet; or

[0017] The first signal indicates that the driving component is not ready to send the data packet, and the second signal indicates that the circuit under test is ready to receive the data packet.

[0018] In some embodiments, the intellectual property verification system further includes a decision component and a selector, wherein the decision component and the second acquisition component are respectively connected to the selector, the decision component is connected to the second acquisition component, and the selector is connected to the flow control sub-component; the method further includes:

[0019] The decision component acquires the second signal acquired by the second acquisition component;

[0020] The selector selects a second signal from the second signal from the decision component and the second signal from the second acquisition component, and sends the selected second signal to the flow control subcomponent.

[0021] In some embodiments, the decision component is connected to the driving component; the method further includes:

[0022] The decision component controls the drive component to send the data packet to the circuit under test based on the second signal.

[0023] In some embodiments, the intellectual property verification system further includes a first first-in-first-out (FIFO) pipeline; the decision component is connected to the first FIFO pipeline, and the first FIFO pipeline is connected to the second acquisition component; the method further includes:

[0024] The decision component acquires the second signal acquired by the second acquisition component, including:

[0025] The second acquisition component buffers the acquired second signal into the first first-in-first-out pipe;

[0026] The decision-making component obtains the second signal from the first first-in-first-out pipeline.

[0027] In some embodiments, the intellectual property verification system further includes a first conversion component and a second conversion component, the verification component including a comparison sub-component; the comparison sub-component is connected to the first conversion component and the second conversion component respectively, the first conversion component is connected to the first acquisition component, and the second conversion component is connected to the second acquisition component; the method further includes:

[0028] The first conversion component converts the first signal acquired by the first acquisition component into first intermediate data;

[0029] The second conversion component converts the second signal acquired by the second acquisition component into second intermediate data;

[0030] The comparison subcomponent compares the first intermediate data and the second intermediate data; if the first intermediate data and the second intermediate data are inconsistent, an error alarm is output.

[0031] In some embodiments, the intellectual property verification system further includes a second FIFO pipeline; the first conversion component is connected to the second FIFO pipeline, and the second FIFO pipeline is connected to the comparison sub-component; the method further includes:

[0032] The first conversion component caches the first intermediate data in the second first-in-first-out pipeline;

[0033] The comparison sub-component obtains the first intermediate data from the second first-in-first-out pipeline.

[0034] In some embodiments, the first signal indicates a data packet that the driving component has sent, and the second signal indicates a data packet that the circuit under test has received; the verification component includes a significant capability verification sub-component;

[0035] The verification component verifies the circuit under test based on the first signal and the second signal, including:

[0036] The significant capability verification subcomponent extracts the first tag carried by the data packet from the first signal and extracts the second tag carried by the data packet from the second signal; it compares the first tag and the second tag, and if the first tag and the second tag are inconsistent, it outputs an error alarm.

[0037] In some embodiments, the method further includes:

[0038] The significant capability verification subcomponent randomly generates multiple labels;

[0039] The saliency verification subcomponent compares the first tag and the second tag. If the first tag and the second tag are inconsistent, an error alarm is output, including:

[0040] After extracting the first tag, the significant capability verification subcomponent registers the first tag among the plurality of tags as non-empty; after extracting the second tag, if the second tag among the plurality of tags is not non-empty, an error alarm is output.

[0041] In some embodiments, before the driving component drives the data packet to the circuit under test, the method further includes:

[0042] Obtain the configuration file of the intellectual property verification system;

[0043] Using the configuration file, configure each connection port, output signal, and input signal in the intellectual property verification system.

[0044] Secondly, embodiments of this application provide an intellectual property verification system, which includes a first acquisition component, a second acquisition component, a driving component, and a verification component, wherein the first acquisition component and the second acquisition component are respectively connected to the verification component;

[0045] The driving component is used to drive data packets to the circuit under test;

[0046] The first acquisition component is used to acquire the first signal of the data packet sent by the driving component to the circuit under test;

[0047] The second acquisition component is used to acquire the second signal sent by the circuit under test to the driving component to receive the data packet;

[0048] The verification component is used to acquire the first signal from the first acquisition component and the second signal from the second acquisition component; and to verify the circuit under test based on the first signal and the second signal.

[0049] In some embodiments, the first signal indicates that the driving component has sent a data packet, and the second signal indicates that the circuit under test has received the data packet; the verification component includes a flow control sub-component.

[0050] The flow control sub-component is configured to decrement the value of a preset counter by 1 after receiving the first signal; increment the value of the preset counter by 1 after receiving the second signal; and output an error alarm when the value of the preset counter is less than a set threshold.

[0051] In some embodiments, the first signal indicates whether the driving component is ready to send the data packet, and the second signal indicates whether the circuit under test is ready to receive the data packet; the verification component includes a flow control sub-component.

[0052] The flow control sub-component is used to output an error alarm when the first signal and the second signal meet preset conditions;

[0053] The preset conditions are as follows:

[0054] The first signal indicates that the driving component is ready to send the data packet, and the second signal indicates that the circuit under test is not ready to receive the data packet; or

[0055] The first signal indicates that the driving component is not ready to send the data packet, and the second signal indicates that the circuit under test is ready to receive the data packet.

[0056] In some embodiments, the intellectual property verification system further includes a decision component and a selector, wherein the decision component and the second acquisition component are respectively connected to the selector, the decision component is connected to the second acquisition component, and the selector is connected to the flow control sub-component;

[0057] The decision component is used to acquire the second signal acquired by the second acquisition component;

[0058] The selector is configured to select a second signal from the second signal from the decision component and the second signal from the second acquisition component, and send the selected second signal to the flow control subcomponent.

[0059] In some embodiments, the decision component is connected to the driving component;

[0060] The decision component is further configured to control the drive component to send the data packet to the circuit under test based on the second signal.

[0061] In some embodiments, the intellectual property verification system further includes a first first-in-first-out (FIFO) pipeline; the decision-making component is connected to the first FIFO pipeline, and the first FIFO pipeline is connected to the second acquisition component;

[0062] The second acquisition component is further configured to buffer the acquired second signal into the first first-in-first-out pipe;

[0063] The decision component is specifically used to obtain the second signal from the first first-in-first-out pipeline.

[0064] In some embodiments, the intellectual property verification system further includes a first conversion component and a second conversion component, the verification component including a comparison sub-component; the comparison sub-component is connected to the first conversion component and the second conversion component respectively, the first conversion component is connected to the first acquisition component, and the second conversion component is connected to the second acquisition component;

[0065] The first conversion component is used to convert the first signal acquired by the first acquisition component into first intermediate data;

[0066] The second conversion component is used to convert the second signal acquired by the second acquisition component into second intermediate data;

[0067] The comparison sub-component is used to compare the first intermediate data and the second intermediate data; if the first intermediate data and the second intermediate data are inconsistent, an error alarm is output.

[0068] In some embodiments, the intellectual property verification system further includes a second first-in-first-out (FIFO) pipeline; the first conversion component is connected to the second FIFO pipeline, and the second FIFO pipeline is connected to the comparison subcomponent;

[0069] The first conversion component is further configured to cache the first intermediate data in the second first-in-first-out pipeline;

[0070] The comparison sub-component is further configured to obtain the first intermediate data from the second first-in-first-out pipeline.

[0071] In some embodiments, the first signal indicates a data packet that the driving component has sent, and the second signal indicates a data packet that the circuit under test has received; the verification component includes a significant capability verification sub-component;

[0072] The significant capability verification subcomponent is used to extract a first tag carried by the data packet from the first signal and extract a second tag carried by the data packet from the second signal; compare the first tag and the second tag, and if the first tag and the second tag are inconsistent, output an error alarm.

[0073] In some embodiments, the significant capability verification subcomponent is further configured to randomly generate multiple labels;

[0074] The significant capability verification subcomponent is specifically used to register the first tag among the plurality of tags as non-empty after the first tag is extracted; and to output an error alarm if the second tag among the plurality of tags is not non-empty after the second tag is extracted.

[0075] In some embodiments, the driving component is further configured to:

[0076] Before sending data packets to the circuit under test, obtain the configuration file of the intellectual property verification kernel system;

[0077] Using the configuration file, configure each connection port, output signal, and input signal in the intellectual property verification system.

[0078] Thirdly, embodiments of this application provide an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0079] Memory, used to store computer programs;

[0080] When a processor executes a program stored in memory, it implements the steps of the method described in the first aspect above.

[0081] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0082] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform the steps of the method described in the first aspect of the above embodiments.

[0083] Beneficial effects of the embodiments in this application:

[0084] In the technical solution provided in this application, the intellectual property verification core system is a general-purpose bus verification framework. During bus verification, only simple configuration of the output signals, input signals, and active modes of the components is required to complete the corresponding bus verification using the verification components. Verification personnel do not need to learn how to build components corresponding to different interface buses, reducing VIP (Virtual Property Entity) construction time and labor costs. Furthermore, because the intellectual property verification core system adopts a general-purpose bus verification framework, its construction is not affected by the construction skills of the verification personnel, thus improving VIP quality.

[0085] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0086] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0087] Figure 1 This is a schematic diagram of the first type of flow control mechanism;

[0088] Figure 2 This is a second schematic diagram of a flow control mechanism;

[0089] Figure 3 A first structural diagram of the VIP system provided for the application embodiment;

[0090] Figure 4 A schematic diagram illustrating the significant capability verification subcomponent provided in the application embodiment for performing significant capability verification;

[0091] Figure 5 A second structural diagram of the VIP system provided in the application embodiment;

[0092] Figure 6 A third structural diagram of the VIP system provided in the application embodiment;

[0093] Figure 7 A fourth structural diagram of the VIP system provided in the application embodiment;

[0094] Figure 8 A fifth structural diagram of the VIP system provided in the application embodiment;

[0095] Figure 9 A schematic diagram of the VIP system implementation process provided in the application embodiment;

[0096] Figure 10 A sixth structural diagram of the VIP system provided in the application embodiment;

[0097] Figure 11 A flowchart illustrating a bus verification method provided in an embodiment of this application;

[0098] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0099] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0100] In chip design, various interface buses serve as crucial bridges for communication between modules or dies. These interface buses vary in complexity, and the specific requirements of each chip project also differ. Bus verification requires building one or more VIPs (Virtual Interfaces) based on the project's needs. The complexity of VIPs for different interface buses is generally high, and using complex VIPs incurs significant learning costs for verification personnel, greatly increasing labor costs. Furthermore, VIP construction is time-consuming, and VIP quality is difficult to guarantee.

[0101] In high-speed buses, flow control and outstanding capabilities are essential concepts. Flow control simply means that when the receiver cannot receive data, the transmitter will stop sending more. Outstanding capability refers to the ability to issue multiple write or read commands consecutively without waiting for a response signal. The stronger the outstanding capability, the higher the bus utilization.

[0102] In bus handshake mechanisms, two common handshake mechanisms are used to implement flow control.

[0103] The first type of flow control mechanism is as follows: Figure 1 As shown. Both the sending and receiving ends can control the information transmission rate. When the sending end has VALID enabled, it means that information such as address, data, and control signals is ready. When the receiving end has READY enabled, it means that it is ready to receive data. Transmission will only proceed according to the clock signal (such as ACLK) when both VALID and READY are enabled.

[0104] The second type of flow control mechanism is as follows: Figure 2As shown. SOP (start of packet) represents the packet header, and EOP (end of packet) represents the packet trailer. During each push phase, the sender transmits SOP, EOP, and data based on a clock signal (e.g., CLK). After receiving SOP, EOP, and data, the receiver sends back an acknowledgment signal such as DCACK or CCACK based on the clock signal (e.g., CLK). The sender then determines whether to transmit data based on the received DCACK or CCACK.

[0105] For the implementation of outsanding capabilities, a key technology is that the data sent by the sending end needs to contain a specific tag signal, and the receiving end will determine whether the data is valid based on the received tag.

[0106] To achieve the aforementioned verification of traffic control and outstanding capabilities, reduce VIP setup time and labor costs, and improve VIP quality, this application provides a VIP system, such as... Figure 3 As shown, the VIP system includes a first acquisition component 31, a second acquisition component 32, a driver component 33, and a verification component 34. The first acquisition component 31 and the second acquisition component 32 are respectively connected to the verification component 34. During bus verification, the first acquisition component 31 and the driver component 33 are connected to the input interface of the circuit under test, and the second acquisition component 32 is connected to the output interface of the circuit under test. The input interface is the interface through which the circuit under test receives signals sent by the driver component 33, and the output interface is the interface through which the circuit under test sends signals to the driver component 33.

[0107] Driver component 33 is used to drive data packets to the circuit under test;

[0108] The first acquisition component 31 is used to acquire the first signal of the driving component 33 sending a data packet to the circuit under test;

[0109] The second acquisition component 32 is used to acquire the second signal of the circuit under test sending the received data packet to the driving component 33;

[0110] Verification component 34 is used to acquire a first signal from the first acquisition component 31 and a second signal from the second acquisition component 32; and to verify the circuit under test based on the first signal and the second signal.

[0111] In the technical solution provided in this application, the intellectual property verification core system is a general-purpose bus verification framework. During bus verification, only simple configuration of the output signals, input signals, and active modes of the components is required to complete the corresponding bus verification using the verification components. Verification personnel do not need to learn how to build components corresponding to different interface buses, reducing VIP (Virtual Property Entity) construction time and labor costs. Furthermore, because the intellectual property verification core system adopts a general-purpose bus verification framework, its construction is not affected by the construction skills of the verification personnel, thus improving VIP quality.

[0112] In this embodiment, the signal types acquired by the first acquisition component 31 and the second acquisition component 32 can be configured through a configuration file. According to the configuration, the first acquisition component 31 and the second acquisition component 32 acquire corresponding signals, such as VALID, READY, SOP, EOP, and data packets. The verification component 34 performs corresponding flow control and outstanding capability verification based on the signals acquired by the first acquisition component 31 and the second acquisition component 32.

[0113] In some embodiments, the verification component 34 may include a flow control sub-component, which is used to perform flow control verification on the circuit under test based on a first signal and a second signal.

[0114] For example Figure 1 The flow control mechanism is illustrated. The first signal indicates whether the driver component is ready to send data packets, and the second signal indicates whether the circuit under test is ready to receive data packets. For example, when the first signal is VALID, it indicates that the driver component is ready to send data packets, and when the second signal is READY, it indicates that the circuit under test is ready to receive data packets.

[0115] In this case, the flow control sub-component is used to output an error alarm when the first and second signals meet preset conditions.

[0116] The preset conditions can be:

[0117] The first signal indicates that the driving component is ready to send data packets, and the second signal indicates that the circuit under test is not ready to receive data packets; or

[0118] The first signal indicates that the driving component is not ready to send data packets, while the second signal indicates that the circuit under test is ready to receive data packets.

[0119] For example Figure 2The flow control mechanism is shown. The first signal indicates that the driving component has sent a data packet, and the second signal indicates that the circuit under test has received the data packet; for example, the first signal is a PUSH signal, SOP signal, EOP signal or a data packet, and the second signal is a DCACK signal or CCACK signal, etc.

[0120] In this case, the flow control sub-component is used to decrement the value of the preset counter by 1 after receiving the first signal; increment the value of the preset counter by 1 after receiving the second signal; and output an error alarm when the value of the preset counter is less than the set threshold.

[0121] The threshold values ​​set above can be adjusted according to actual needs. For example, the threshold value can be 0, 1, or 5.

[0122] In this embodiment of the application, to implement verification of various flow controls, the verification component may include multiple flow control sub-components, with different flow control sub-components processing different signals. For example, the verification component may include two flow control sub-components: one flow control sub-component processes the verification of flow control associated with the DCACK signal, and the other flow control sub-component processes the verification of flow control associated with the CCACK signal.

[0123] In some embodiments, the verification component 34 may include a significant capability verification sub-component, which is used to perform outstanding capability verification on the circuit under test based on a first signal and a second signal.

[0124] For the realization of outstanding capability, the first signal indicates the data packet sent by the driving component 33, and the second signal indicates the data packet received by the circuit under test.

[0125] In this case, the significant capability verification subcomponent is used to extract the first tag carried by the data packet from the first signal and the second tag carried by the data packet from the second signal; compare the first tag and the second tag; if the first tag and the second tag are inconsistent, an error alarm is output.

[0126] To facilitate outstanding capability verification, the outstanding capability verification sub-component can implement outstanding capability verification using a string array. Specifically, the outstanding capability verification sub-component randomly generates multiple tags; after extracting the first tag, it registers the first tag among the multiple tags as not empty (Not Empty, NE); after extracting the second tag, if the second tag among the multiple tags is not in a non-empty state, an error alarm is output.

[0127] For example, the salient capability verification subcomponent randomly generates multiple tags, such as Figure 4As shown. The driving component sends one or more data packets, each carrying a randomly generated TAG. After the salient capability verification subcomponent obtains the first signal (i.e., the data packet) from the first acquisition component, it extracts TAG1 from the first signal, as shown. Figure 4 In the context of 1111, the state of 1111 is set to NE. After the significant capability verification subcomponent obtains the second signal (i.e., the data packet) from the second acquisition component, it extracts TAG2 from the second signal. If TAG2 is not in a non-empty state, that is, if TAG2 is in an empty state (E), then... Figure 4 If 1110 is found, it indicates that the first and second tags are inconsistent, and an error alarm is output; if the TAG2 is not empty, i.e., the TAG2 is NE, then... Figure 4 If 1111 is found in the data packet, then the verification result corresponding to the data packet is determined to be: the circuit under test has successfully passed the outstanding capability verification.

[0128] Here, if the driving component sends multiple data packets, the verification results corresponding to these multiple data packets must all indicate that the circuit under test has successfully passed the outstanding capability verification in order to prove that the circuit under test has successfully passed the outstanding capability verification.

[0129] In some embodiments, the VIP system may further include a decision component 35 and a selector 36, such as Figure 5 As shown, the decision component 35 and the second acquisition component 32 are respectively connected to the selector 36, the decision component 35 is connected to the second acquisition component 32, and the selector 36 is connected to the flow control sub-component (i.e., the verification component 34).

[0130] Decision component 35 is used to acquire the second signal acquired by the second acquisition component 32;

[0131] Selector 36 is used to select a second signal from the second signal from the decision component 35 and the second signal from the second acquisition component 32, and send the selected second signal to the flow control subcomponent.

[0132] In this embodiment, both the decision component 35 and the second acquisition component 32 can be used to drive the flow control sub-component for flow control verification, such as incrementing the value of the preset counter by 1 as described above. The decision component 35 and the second acquisition component 32 driving the flow control sub-component are mutually exclusive. Selecting either the decision component 35 or the second acquisition component 32 to drive the flow control sub-component according to actual needs improves the flexibility of flow control.

[0133] In some embodiments, the decision component 35 is connected to the driving component 33, such as Figure 5 As shown. In this case, the decision component 35 can also be used to control the drive component 33 to send data packets to the circuit under test based on the second signal after it is acquired.

[0134] In this embodiment, the second signal is the response data of the circuit under test acquired by the second acquisition component 32. The decision component 35 can determine whether the driving component 33 should send request data (such as the data packet mentioned above) based on the response data. Here, the connection relationship between the decision component 35 and the second acquisition component 32 can be configured through a configuration file.

[0135] In some embodiments, to ensure that the decision component 35 obtains the second signal from the second acquisition component 32, the VIP system may further include a first first-in-first-out (FIFO) pipeline 37, such as... Figure 6 As shown, the decision component 35 is connected to the first FIFO pipeline 37, and the first FIFO pipeline 37 is connected to the second acquisition component 32. In this case, the second acquisition component 32 can also be used to buffer the acquired second signal into the first FIFO pipeline 37; the decision component 35 is specifically used to obtain the second signal from the first FIFO pipeline 37.

[0136] In some embodiments, such as Figure 7 As shown, the VIP system may also include a first conversion component 38 and a second conversion component 39, and the verification component 34 may include a comparison sub-component; the comparison sub-component is connected to the first conversion component 38 and the second conversion component 39 respectively, the first conversion component 38 is connected to the first acquisition component 31, and the second conversion component 39 is connected to the second acquisition component 32.

[0137] In this case, the first conversion component 38 is used to convert the first signal acquired by the first acquisition component 31 into first intermediate data;

[0138] The second conversion component 39 is used to convert the second signal acquired by the second acquisition component 32 into second intermediate data;

[0139] The comparison sub-component is used to compare the first intermediate data and the second intermediate data; if the first intermediate data and the second intermediate data are inconsistent, an error alarm is output.

[0140] In this embodiment, the first conversion component 38 and the second conversion component 39 are modules for implementing data format conversion, which can convert the data format of the input / output of the circuit under test into a unified data format that the comparison subcomponent can recognize. The comparison subcomponent compares the first intermediate data and the second intermediate data to determine whether the output of the circuit under test meets expectations. That is, if the first intermediate data and the second intermediate data are the same, it is determined that the output of the circuit under test meets expectations; if the first intermediate data and the second intermediate data are different, it is determined that the output of the circuit under test does not meet expectations, and an error alarm is output.

[0141] In some embodiments, such as Figure 8As shown, the VIP system may further include a second FIFO pipeline 310; a first conversion component 38 is connected to the second FIFO pipeline 310, and the second FIFO pipeline 310 is connected to a comparison sub-component. In this case, the first conversion component 38 may also be used to cache the first intermediate data in the second FIFO pipeline; the comparison sub-component may also be used to obtain the first intermediate data from the second FIFO pipeline.

[0142] In this embodiment, after the first conversion component 38 converts the first signal into first intermediate data, it caches the first intermediate data in the second FIFO pipeline 310. Then, the comparison sub-component actively retrieves the first intermediate data (i.e., request data) from the second FIFO pipeline 310. Conversely, after the second conversion component 39 converts the second signal into second intermediate data, it can actively send the second intermediate data to the comparison sub-component, which passively receives the second intermediate data (i.e., response data). Since the first intermediate data is retrieved earlier and the second intermediate data is retrieved later, the comparison sub-component can improve the accuracy and timeliness of data comparison by actively retrieving the first intermediate data and passively retrieving the second intermediate data.

[0143] In this embodiment, both the second conversion component 39 and the first FIFO channel 37 are connected to the second acquisition component 32. The VIP system may also include a selector 311, with the second conversion component 39 and the first FIFO channel 37 connected to it, and the selector 311 connected to the second acquisition component 32. In this case, the selector 311 can choose to store the second signal in the first FIFO channel 37 or send the second signal to the second conversion component 39. The specific structure can be configured according to actual needs.

[0144] In this embodiment, before bus verification, i.e., before the driving component drives the data packet to the circuit under test, the VIP system can obtain its configuration file. Using the configuration file, the various connection ports, output signals, and input signals in the verification intellectual property system are configured. For example, the configuration file may include necessary parameters such as input signals, output signals, the name of the VIP, the driving method of the flow control subcomponent, the connection between the comparison subcomponent and the second first-in-first-out pipeline, and the input pins selected by each selector. Figure 9 The VIP system implementation process is shown below. The VIP system converts the configuration file into a script in a format such as JSON. Running this script configures the necessary parameters into the VIP system's basic component library, resulting in a general bus verification framework. The basic component library includes all the components mentioned above.

[0145] In the technical solution provided in this application, the intellectual property verification core system is a general-purpose bus verification framework. During bus verification, only simple configuration of the output signals, input signals, and active modes of the components is required to complete the corresponding bus verification using the verification components. Verification personnel do not need to learn how to build components corresponding to different interface buses, reducing VIP (Virtual Property Entity) construction time and labor costs. Furthermore, because the intellectual property verification core system adopts a general-purpose bus verification framework, its construction is not affected by the construction skills of the verification personnel, thus improving VIP quality.

[0146] In this embodiment of the application, the VIP system may also include other components, such as a reset component, which can be pre-configured in the basic component library according to actual needs.

[0147] The following is combined Figure 10 The VIP system architecture shown below provides a detailed description of the VIP system provided in this application embodiment. The VIP system includes a first universal bus proxy component (UNB_AGT1) and a second universal bus proxy component (UNB_AGT2). UNB_AGT1 and UNB_AGT2 are two virtual verification environments.

[0148] UNB_AGT1 includes a reset component 1 (RESET_HANDEL1), a first acquisition component (UNB_Mon1), flow control sub-components (UNB_CRD1, UNB_CRD2), a driver component (UNB_DRV), a first conversion component (UNB_FMT1), selectors (MUX1, MUX2), a decision component (UNB_SQR), and a significant capability verification sub-component (UNB_TAG).

[0149] UNB_AGT2 includes a reset component 2 (RESET_HANDEL2), a second acquisition component (UNB_Mon2), a selector (MUX3), a second conversion component (UNB_FMT2), and a first first-in-first-out pipeline (FIFO1).

[0150] The VIP system may also include a second first-in-first-out pipeline (FIFO2) and a comparator sub-component (UNB_SCB).

[0151] The connection relationships of the above components can be found in [reference]. Figure 10 As shown. UNB_CRD2 and MUX2 can be enabled according to actual needs. For example, when flow control verification is required based on both DCACK and CCACK signals, UNB_CRD2 and MUX2 should be enabled; when flow control verification is based only on DCACK or only on CCACK signals, UNB_CRD2 and MUX2 should not be enabled.

[0152] Before configuring each component based on the configuration file, RESET_HANDEL1 and RESET_HANDEL2 can be enabled to reset each component. After configuring each component based on the configuration file, the timing component (UNB_SEQ) inputs sequence data to UNB_SQR and transmits it to the Bus Functional Model (BFM) in UNB_DRV (used to complete the timing functions of the underlying bus), thereby enabling UNB_DRV to drive data packets to the circuit under test according to the timing sequence. Subsequently, the components exchange data to complete the verification of the aforementioned flow control and outstanding capabilities.

[0153] This description is relatively simple; please refer to the relevant descriptions above for details.

[0154] The technical solution provided in this application saves time in building verification platforms such as VIPs. It can automatically generate verification platforms using configuration files. The generated verification platform integrates traffic control-related components and Outstanding functional components, which can avoid the problem of difficulty in guaranteeing the quality of the verification platform due to the experience and ability of verification personnel.

[0155] Corresponding to the aforementioned VIP system, this application embodiment also provides a bus verification method, such as... Figure 11 As shown, this method is applied to an intellectual property verification system. The intellectual property verification system includes a first acquisition component, a second acquisition component, a driver component, and a verification component. The first and second acquisition components are respectively connected to the verification component. The method includes the following steps:

[0156] Step S111: The driving component sends a data packet to the circuit under test;

[0157] Step S112: The first acquisition component acquires the first signal of the driving component sending data packets to the circuit under test;

[0158] Step S113: The second acquisition component acquires the second signal sent by the circuit under test to the driving component to receive the data packet;

[0159] Step S114: The verification component obtains a first signal from the first acquisition component and a second signal from the second acquisition component; based on the first signal and the second signal, the circuit under test is verified.

[0160] In the technical solution provided in this application, the intellectual property verification core system is a general-purpose bus verification framework. During bus verification, only simple configuration of the output signals, input signals, and active modes of the components is required to complete the corresponding bus verification using the verification components. Verification personnel do not need to learn how to build components corresponding to different interface buses, reducing VIP (Virtual Property Entity) construction time and labor costs. Furthermore, because the intellectual property verification core system adopts a general-purpose bus verification framework, its construction is not affected by the construction skills of the verification personnel, thus improving VIP quality.

[0161] In some embodiments, a first signal indicates that the driving component has sent a data packet, and a second signal indicates that the circuit under test has received a data packet; the verification component includes a flow control sub-component.

[0162] The verification component verifies the circuit under test based on the first and second signals, and may include:

[0163] After receiving the first signal, the flow control sub-component decrements the value of the preset counter by 1; after receiving the second signal, it increments the value of the preset counter by 1; when the value of the preset counter is less than the set threshold, it outputs an error alarm.

[0164] In some embodiments, a first signal indicates whether the driving component is ready to send data packets, and a second signal indicates whether the circuit under test is ready to receive data packets; the verification component includes a flow control sub-component.

[0165] The verification component verifies the circuit under test based on the first and second signals, and may include:

[0166] When the first and second signals meet preset conditions, the flow control sub-component outputs an error alarm;

[0167] The preset conditions are as follows:

[0168] The first signal indicates that the driving component is ready to send data packets, and the second signal indicates that the circuit under test is not ready to receive data packets; or

[0169] The first signal indicates that the driving component is not ready to send data packets, while the second signal indicates that the circuit under test is ready to receive data packets.

[0170] In some embodiments, the intellectual property verification system may further include a decision component and a selector, wherein the decision component and a second acquisition component are respectively connected to the selector, the decision component is connected to the second acquisition component, and the selector is connected to the flow control sub-component; the above bus verification method may further include:

[0171] The decision component acquires the second signal acquired by the second acquisition component;

[0172] The selector selects a second signal from the second signal from the decision component and the second signal from the second acquisition component, and sends the selected second signal to the flow control subcomponent.

[0173] In some embodiments, the decision component is connected to the driving component; the bus verification method described above may further include:

[0174] Based on the second signal, the decision component controls the drive component to send data packets to the circuit under test.

[0175] In some embodiments, the intellectual property verification kernel system may further include a first first-in-first-out pipeline; the decision component is connected to the first first-in-first-out pipeline, and the first first-in-first-out pipeline is connected to a second acquisition component.

[0176] The decision component may acquire the second signal acquired by the second acquisition component, which may include:

[0177] The second acquisition component buffers the acquired second signal into the first first-in-first-out pipe;

[0178] The decision-making component obtains the second signal from the first in-first-out pipeline.

[0179] In some embodiments, the intellectual property verification system may further include a first conversion component and a second conversion component, the verification component including a comparison sub-component; the comparison sub-component is connected to the first conversion component and the second conversion component respectively, the first conversion component is connected to a first acquisition component, and the second conversion component is connected to a second acquisition component; the above bus verification method may further include:

[0180] The first conversion component converts the first signal acquired by the first acquisition component into first intermediate data;

[0181] The second conversion component converts the second signal acquired by the second acquisition component into second intermediate data;

[0182] The comparison sub-component compares the first intermediate data and the second intermediate data; if the first intermediate data and the second intermediate data are inconsistent, an error alarm is output.

[0183] In some embodiments, the intellectual property verification system may further include a second FIFO pipeline; a first conversion component is connected to the second FIFO pipeline, and the second FIFO pipeline is connected to a comparison subcomponent; the above bus verification method may further include:

[0184] The first conversion component caches the first intermediate data into the second first-in-first-out pipeline;

[0185] The comparison sub-component retrieves the first intermediate data from the second FIFO pipeline.

[0186] In some embodiments, a first signal indicates a data packet that the driving component has sent, and a second signal indicates a data packet that the circuit under test has received; the verification component includes a significant capability verification sub-component.

[0187] The verification component verifies the circuit under test based on the first and second signals, and may include:

[0188] The significant capability verification subcomponent extracts the first tag carried by the data packet from the first signal and the second tag carried by the data packet from the second signal; it compares the first tag and the second tag, and if the first tag and the second tag are inconsistent, it outputs an error alarm.

[0189] In some embodiments, the bus verification method described above may further include:

[0190] The significant capability verification subcomponent randomly generates multiple tags;

[0191] The salient capability verification subcomponent compares the first tag and the second tag. If the first tag and the second tag are inconsistent, an error alert is output, including:

[0192] After extracting the first tag, the significant capability verification subcomponent registers the first tag among multiple tags as non-empty; after extracting the second tag, if the second tag among multiple tags is not non-empty, an error alarm is output.

[0193] In some embodiments, before the driving component drives the data packet to the circuit under test, the bus verification method described above may further include:

[0194] Obtain the configuration file for the intellectual property verification system;

[0195] Configure the various connection ports, output signals, and input signals in the intellectual property verification system using configuration files.

[0196] Corresponding to the bus verification method described above, this application also provides an electronic device, such as... Figure 12 As shown, it includes a processor 121, a communication interface 122, a memory 123 and a communication bus 124, wherein the processor 121, the communication interface 122 and the memory 123 communicate with each other through the communication bus 124.

[0197] Memory 123 is used to store computer programs;

[0198] When the processor 121 executes the program stored in the memory 123, it implements any of the above-mentioned bus verification methods.

[0199] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0200] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0201] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0202] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0203] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements any of the above-described bus verification methods.

[0204] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute any of the above-described bus verification methods.

[0205] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0206] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0207] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of methods, electronic devices, storage media, and program products are basically similar to the system embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the system embodiments.

[0208] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A bus verification method, characterized in that, An intellectual property verification system is applied, the intellectual property verification system comprising a first acquisition component, a second acquisition component, a driving component, and a verification component, wherein the first acquisition component and the second acquisition component are respectively connected to the verification component; the method includes: The driving component drives data packets to the circuit under test; The first acquisition component acquires the first signal of the data packet sent by the driving component to the circuit under test; The second acquisition component acquires the second signal sent by the circuit under test to the driving component to receive the data packet; The verification component acquires the first signal from the first acquisition component and the second signal from the second acquisition component; based on the first signal and the second signal, it verifies the circuit under test.

2. The method according to claim 1, characterized in that, The first signal indicates that the driving component has sent a data packet, and the second signal indicates that the circuit under test has received the data packet; the verification component includes a flow control sub-component; The verification component verifies the circuit under test based on the first signal and the second signal, including: After receiving the first signal, the flow control sub-component decrements the value of the preset counter by 1. After receiving the second signal, the value of the preset counter is incremented by 1; when the value of the preset counter is less than the set threshold, an error alarm is output.

3. The method according to claim 1, characterized in that, The first signal indicates whether the driving component is ready to send the data packet, and the second signal indicates whether the circuit under test is ready to receive the data packet; the verification component includes a flow control sub-component. The verification component verifies the circuit under test based on the first signal and the second signal, including: The flow control sub-component outputs an error alarm when the first signal and the second signal meet preset conditions; The preset conditions are as follows: The first signal indicates that the driving component is ready to send the data packet, and the second signal indicates that the circuit under test is not ready to receive the data packet; or The first signal indicates that the driving component is not ready to send the data packet, and the second signal indicates that the circuit under test is ready to receive the data packet.

4. The method according to claim 2 or 3, characterized in that, The intellectual property verification system further includes a decision component and a selector. The decision component and the second acquisition component are respectively connected to the selector. The decision component is connected to the second acquisition component, and the selector is connected to the flow control sub-component. The method further includes: The decision component acquires the second signal acquired by the second acquisition component; The selector selects a second signal from the second signal from the decision component and the second signal from the second acquisition component, and sends the selected second signal to the flow control subcomponent.

5. The method according to claim 4, characterized in that, The decision component is connected to the driving component; the method further includes: The decision component controls the drive component to send the data packet to the circuit under test based on the second signal.

6. The method according to claim 4, characterized in that, The intellectual property verification system further includes a first first-in-first-out (FIFO) pipeline; the decision-making component is connected to the first FIFO pipeline, and the first FIFO pipeline is connected to the second acquisition component. The decision component acquires the second signal acquired by the second acquisition component, including: The second acquisition component buffers the acquired second signal into the first first-in-first-out pipe; The decision-making component obtains the second signal from the first first-in-first-out pipeline.

7. The method according to claim 1, characterized in that, The intellectual property verification system further includes a first conversion component and a second conversion component, the verification component including a comparison sub-component; the comparison sub-component is connected to the first conversion component and the second conversion component respectively, the first conversion component is connected to the first acquisition component, and the second conversion component is connected to the second acquisition component; the method further includes: The first conversion component converts the first signal acquired by the first acquisition component into first intermediate data; The second conversion component converts the second signal acquired by the second acquisition component into second intermediate data; The comparison subcomponent compares the first intermediate data and the second intermediate data; if the first intermediate data and the second intermediate data are inconsistent, an error alarm is output.

8. The method according to claim 7, characterized in that, The intellectual property verification system further includes a second FIFO pipeline; the first conversion component is connected to the second FIFO pipeline, and the second FIFO pipeline is connected to the comparison sub-component; the method further includes: The first conversion component caches the first intermediate data in the second first-in-first-out pipeline; The comparison sub-component obtains the first intermediate data from the second first-in-first-out pipeline.

9. The method according to claim 1, characterized in that, The first signal indicates a data packet that the driving component has sent, and the second signal indicates a data packet that the circuit under test has received; the verification component includes a significant capability verification sub-component; The verification component verifies the circuit under test based on the first signal and the second signal, including: The significant capability verification subcomponent extracts the first tag carried by the data packet from the first signal and extracts the second tag carried by the data packet from the second signal; it compares the first tag and the second tag, and if the first tag and the second tag are inconsistent, it outputs an error alarm.

10. The method according to claim 9, characterized in that, The method further includes: The significant capability verification subcomponent randomly generates multiple labels; The saliency verification subcomponent compares the first tag and the second tag. If the first tag and the second tag are inconsistent, an error alarm is output, including: After extracting the first tag, the significant capability verification subcomponent registers the first tag among the plurality of tags as non-empty; after extracting the second tag, if the second tag among the plurality of tags is not non-empty, an error alarm is output.

11. The method according to claim 1, characterized in that, Before the driving component drives the data packet to the circuit under test, the method further includes: Obtain the configuration file of the intellectual property verification system; Using the configuration file, configure each connection port, output signal, and input signal in the intellectual property verification system.

12. A system for verifying intellectual property rights, characterized in that, The intellectual property verification system includes a first acquisition component, a second acquisition component, a driving component, and a verification component, wherein the first acquisition component and the second acquisition component are respectively connected to the verification component; The driving component is used to drive data packets to the circuit under test; The first acquisition component is used to acquire the first signal of the data packet sent by the driving component to the circuit under test; The second acquisition component is used to acquire the second signal sent by the circuit under test to the driving component to receive the data packet; The verification component is used to acquire the first signal from the first acquisition component and the second signal from the second acquisition component; and to verify the circuit under test based on the first signal and the second signal.

13. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method described in any one of claims 1-11.

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