Optical computing chip

Abstract

Embodiments of the present application provide an optical computing chip, which comprises a coherent coupling VCSEL array layer, a buffer layer and a photodetector layer stacked in sequence; wherein: the coherent coupling VCSEL array layer is used for converting a first electrical signal into a first optical signal and outputting; the buffer layer is used for propagating the first optical signal, and the first optical signals are coupled with each other during the propagation process to form an output signal; and the photodetector layer is used for acquiring an output optical intensity of the output signal and converting the output optical intensity into a second electrical signal for output. The optical computing chip of the embodiments of the present application does not need to realize coherent coupling through additional coherent laser sources for optical injection phase locking, and can realize chip-level integration of the entire optical computing system based on the coherent coupling VCSEL array layer, thereby promoting VCSEL-based optical computing applications.

Description

Technical Field

[0001] This application relates to the field of optical computing technology, and in particular to an optical computing chip. Background Technology

[0002] With the rapid development of artificial intelligence (AI), the computing speed of electronic chips based on the von Neumann architecture is gradually becoming insufficient to meet the demands of AI computing, and electronic chips also consume a lot of energy. In order to improve computing power and save energy, people have begun to develop optical computing chips that use light as the information carrier.

[0003] Vertical-Cavity Surface-Emitting Laser (VCSEL) is a type of semiconductor laser with advantages such as small size, high speed, addressability, and arrayability, making it suitable for optical computing. However, VCSEL-based optical computing requires building large-volume optical systems, making it difficult to achieve chip-level integration of the entire optical computing system, which greatly limits its practical application.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the Invention

[0005] This application provides an optical computing chip to solve or alleviate one or more of the technical problems mentioned above.

[0006] One aspect of this application provides an optical computing chip, comprising a coherently coupled VCSEL array layer, a buffer layer, and a photodetector layer stacked sequentially; wherein: The coherently coupled VCSEL array layer is used to convert the first electrical signal into a first optical signal and output it. The buffer layer is used to propagate the first optical signal, and the first optical signal is coupled to each other during the propagation process to form an output signal; The photodetector layer is used to acquire the output light intensity of the output signal and convert the output light intensity into a second electrical signal for output.

[0007] Optionally, the coherently coupled VCSEL array layer includes multiple groups of VCSEL devices, each group of VCSEL devices includes multiple VCSEL units, the VCSEL units in the same group of VCSEL devices are coherently coupled, and the VCSEL units in different groups of VCSEL devices are not coherently coupled. In this setup, the first optical signals emitted by multiple VCSEL units in the same group of VCSEL devices are coupled to each other and are phase-locked.

[0008] Optionally, the photodetector layer includes multiple photodetectors, and the multiple photodetectors correspond one-to-one with multiple sets of VCSEL devices. Each photodetector is used to acquire the output light intensity of the corresponding VCSEL device. The output light intensity is determined based on the intensity of the first light signal emitted by each VCSEL unit, the coherence between each VCSEL unit, and the phase difference between each first light signal.

[0009] Optionally, the intensity and phase of the first optical signal emitted by each VCSEL unit are determined according to the injection current of the corresponding VCSEL unit; Correspondingly, the output light intensity is determined based on the injection current of each VCSEL unit.

[0010] Optionally, the first VCSEL unit and the second VCSEL unit are coherently coupled, the first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are mutually coupled, and the first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are phase locked.

[0011] Optionally, each set of VCSEL devices, together with its corresponding photodetector, is used to simulate the function of a neuron in a biological neural network, wherein: A set of VCSEL devices is used to simulate the weight modulation function of a synaptic structure in a neuron; wherein, a first VCSEL unit is used to generate an input signal; and a second VCSEL unit is used to apply weights to the input signal to form a corresponding output signal; Photodetectors are used to simulate the accumulation function of cell body structures in neurons.

[0012] Optionally, the first VCSEL unit is used to output a first timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a second timing optical signal, which is pre-trained timing weight information. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire the first output light intensity of the corresponding VCSEL device and accumulate it, and then convert the accumulation result into the second electrical signal output. Wherein, the first output light intensity is the intensity of the first output signal formed by the mutual coupling of the first timing optical signal and the second timing optical signal.

[0013] Optionally, the first VCSEL unit is further configured to output a third timing optical signal, which is obtained by timing encoding multiple second electrical signals generated by multiple photodetectors. The second VCSEL unit is used to output a fourth timing optical signal, which is pre-trained timing weight information. The weight information corresponding to each group of VCSEL devices is different. The photodetector is used to acquire and accumulate the second output light intensity of the corresponding VCSEL device, and convert the accumulation result into the third electrical signal and output it. Wherein, the second output light intensity is the intensity of the second output signal formed by the mutual coupling of the third timing optical signal and the fourth timing optical signal.

[0014] Optionally, each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, and a third VCSEL unit; The first electrical signal includes a first electrical signal and a first second electrical signal; The first VCSEL unit is used to output a fifth timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a sixth timing optical signal, which is obtained by conversion based on the first two electrical signals; The third VCSEL unit is used to output the seventh timing optical signal, which is the weight information of the timing sequence pre-trained. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the third output light intensity of the corresponding VCSEL device, and convert the accumulation result into the second electrical signal and output it. The third output light intensity is the intensity of the third output signal formed by the mutual coupling of the fifth, sixth, and seventh time-series optical signals.

[0015] Optionally, each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, a third VCSEL unit, and a fourth VCSEL unit; The first electrical signal includes a first electrical signal, a first second electrical signal, and a first third electrical signal; The first VCSEL unit is used to output an eighth timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a ninth timing optical signal, which is obtained by conversion based on the first two electrical signals; The third VCSEL unit is used to output the tenth timing optical signal, which is obtained by conversion based on the first three electrical signals. The fourth VCSEL unit is used to output the eleventh timing optical signal, which is the weight information of the timing sequence pre-trained. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the fourth output light intensity of the corresponding VCSEL device, and convert the accumulation result into the second electrical signal and output it. The fourth output light intensity is the intensity of the fourth output signal formed by the mutual coupling of the eighth, ninth, tenth, and eleventh time-series optical signals.

[0016] The optical computing chip of this application embodiment has the following advantages: The optical computing chip of this application embodiment adopts a three-dimensional vertical architecture, consisting of a coherently coupled VCSEL array layer, a buffer layer, and a photodetector layer stacked sequentially. Specifically: the coherently coupled VCSEL array layer converts electrical signals into mutually coupled optical signals to perform optical computation using the principle of optical coherence; the buffer layer propagates the optical signals, which couple to form an output signal during propagation; the photodetector layer collects the output light intensity and converts the intensity data into an electrical signal for output. It is understood that the optical computing chip of this application embodiment uses the coherently coupled VCSEL array layer as the computing unit, and the emitted optical signals can couple to perform optical computation without requiring an additional coherent laser source for phase-locked optical injection to achieve coherent coupling. This enables chip-level integration of the entire optical computing system and promotes VCSEL-based optical computing applications. Attached Figure Description

[0017] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of the claims. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0018] Figure 1 A schematic diagram of the longitudinal cross-sectional structure of the optical computing chip according to Embodiment 1 of this application is shown. Figure 2 The schematic diagram illustrates the planar arrangement of a coherently coupled VCSEL array layer composed of multiple sets of 1×2 VCSEL devices; Figure 3 The schematic diagram illustrates the planar arrangement of a coherently coupled VCSEL array layer consisting of multiple 1×3 VCSEL devices.

[0019] Explanation of reference numerals in the attached figures: 100 coherently coupled VCSEL array layers 200 buffer layers 300 photodetector layers Detailed Implementation To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0021] In the description of this application, it should be understood that the numerical labels before the steps do not indicate the order of the steps, but are only used to facilitate the description of this application and to distinguish each step, and therefore should not be construed as a limitation of this application.

[0022] First, a definition of the terminology used in this application is provided: VCSEL (Vertical-Cavity Surface-Emitting Laser): A vertical-cavity surface-emitting laser, one of the important active devices used in optical computing. It has the advantages of small size, high speed, addressability, and arrayability, and is used in optical neural network computing.

[0023] Neural network: A computational model that simulates biological neural networks, applied in fields such as pattern recognition, classification, regression, speech recognition, image processing, and natural language processing.

[0024] Optical neural network: A computational model that uses optical elements (such as lasers, waveguide devices, etc.) to simulate biological neural networks.

[0025] Neuron: The basic unit of a neural network, also known as a node or processing unit, used to accept input, perform calculations, and produce output. Each neuron can have multiple inputs and one output.

[0026] Weights: Used to adjust the importance of input signals, thereby affecting the output of neurons.

[0027] On-chip integration: Integrating multiple functional modules and components onto a single chip to perform complex computing and control tasks.

[0028] Secondly, to facilitate understanding of the technical solutions provided in the embodiments of this application by those skilled in the art, the relevant technologies are described below: With the rapid development of artificial intelligence (AI), the computing speed of current electronic chips based on the von Neumann architecture is gradually becoming insufficient to meet the demands of AI computing, and the excessive energy consumption of electronic chips may lead to a serious energy crisis. Considering both computing power and energy efficiency, optical computing chips, which use light as the information carrier, represent one of the development directions for next-generation chips.

[0029] Vertical-cavity surface-emitting lasers (VCSELs) are one of the important active devices used in optical computing. They have advantages such as small size, high speed, addressability, and arrayability, and are therefore used in optical computing.

[0030] The applicant understands that phase locking cannot be achieved between VCSEL units in VCSEL arrays of related technologies. An additional coherent laser source is required to illuminate the VCSEL array, and coherent coupling between VCSEL units is achieved through optical injection phase locking. This means that optical computing based on VCSEL arrays requires building a large-volume optical system, making it difficult to achieve chip-level integration of the entire optical computing system, which greatly restricts its practical application.

[0031] Therefore, this application provides an optical computing chip. In this technical solution, a coherently coupled VCSEL array is used as the computing unit of an optical neural network to simulate synaptic function. A vertically integrated chip architecture based on a coherently coupled VCSEL array is proposed, enabling chip-level VCSEL-based optical neural networks and expanding the potential application areas of VCSEL optical neural networks. Utilizing the high modulation rate (GHz) of VCSELs, the computing power of this optical computing chip will far exceed that of existing electronic chips, and will increase with the scale of VCSELs. Based on the passive propagation characteristics of light, the energy consumption of this optical computing chip will also be much lower than that of existing electronic chips, solving the energy problem faced by AI computing. This optical computing chip can be used in various application scenarios such as face recognition, optical computing, image classification, 6G communication, optical encryption, and autonomous driving. See below for details.

[0032] The technical solutions of this application are described below through several embodiments. It should be understood that these embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0033] Figure 1 A schematic structural diagram of an optical computing chip according to an embodiment of this application is shown.

[0034] like Figure 1As shown, the optical computing chip includes a coherently coupled VCSEL array layer 100, a buffer layer 200, and a photodetector layer 300 stacked in sequence.

[0035] The functions and working relationships of the coherently coupled VCSEL array layer 100, buffer layer 200, and photodetector layer 300 will be introduced below.

[0036] The coherently coupled VCSEL array layer 100 can be composed of multiple VCSELs. A VCSEL is a semiconductor laser that emits a beam of light in the vertical direction. A VCSEL generates light by injecting current into a semiconductor cavity, converting an electrical signal into an optical signal. Unlike ordinary VCSEL devices, coherently coupled VCSEL arrays have a special device structure. Through physical mechanisms such as anti-waveguides, air gaps, or diffraction, coherent coupling between the emitted laser beams of VCSEL units can be achieved, whereas ordinary VCSEL array units are not coherently coupled. For a coherently coupled VCSEL array, by adjusting the injection current of each unit, the phase difference and coherence of the emitted laser beams between units can be adjusted, thereby adjusting the overall laser intensity and enabling optical computation. In this embodiment, the coherently coupled VCSEL array layer is used to convert a first electrical signal into a first optical signal and output it.

[0037] The buffer layer 200 is vertically disposed above the coherently coupled VCSEL array layer 100 and is used to propagate the first optical signal generated by the coherently coupled VCSEL array layer 100 and to support the photodetector layer 300, such as... Figure 1 As shown. The buffer layer 200 allows the first optical signal to propagate over a certain distance. During this propagation, the first optical signals can interfere with and couple with each other to form a composite optical signal (output signal). For example, the buffer layer 200 can be a light-transmitting support, pillar, etc.

[0038] The photodetector layer 300 may include multiple photodetectors. A photodetector is an optoelectronic device used to detect and measure the optical characteristics of light signals, such as intensity, frequency, and wavelength. In this embodiment, the photodetector layer 300 is used to collect the light intensity data of the composite light signal (output signal) generated after the first light signal undergoes optical processing, and converts the output signal into a second electrical signal based on the light intensity data. In some embodiments, the photodetector layer can be designed with appropriate circuitry so that the photodetector layer 300 can accumulate and sum the light intensity data collected over a period of time, thereby simulating the accumulation function of the neuron cell body structure on the input signal.

[0039] The optical computing chip in this embodiment adopts a vertical chip architecture based on a coherently coupled VCSEL array layer 100: using the coherently coupled VCSEL array layer 100 as the computing unit, the emitted first optical signals can be coupled to each other for optical computing, eliminating the need for a large-volume optical system to achieve coherent coupling. This enables chip-level integration of VCSEL-based optical computing systems, promoting VCSEL-based optical computing applications. Utilizing the high modulation rate (GHz) of VCSELs, the computing power of this optical computing chip will far exceed that of existing electronic chips, and will increase with the scaling up of VCSELs. Based on the passive propagation characteristics of light, the energy consumption of this optical computing chip will also be much lower than that of existing electronic chips, solving the energy problems faced by AI computing. In optional embodiments, such as Figures 2-3 As shown, the coherently coupled VCSEL array layer 100 includes multiple groups of VCSEL devices, each group of VCSEL devices including multiple VCSEL units. VCSEL units in the same group of VCSEL devices are coherently coupled, while VCSEL units in different groups of VCSEL devices are not coherently coupled. Specifically, the first optical signals emitted by multiple VCSEL units in the same group of VCSEL devices are mutually coupled and phase-locked.

[0040] The coherently coupled VCSEL array layer 100 can be composed of several groups of VCSEL devices arranged together. A VCSEL device is a collection of VCSEL cells, and each VCSEL device includes at least two VCSEL cells. Figure 2 A 1×2 VCSEL device is shown. Figure 3 A 1×3 VCSEL device is shown. In some embodiments, each group of VCSEL devices may also consist of four or more VCSEL units. The number of VCSEL units in a group of VCSEL devices can be set according to the task to be performed, and is not limited here.

[0041] A VCSEL unit is a vertical-cavity surface-emitting laser used to output a first optical signal in the vertical direction. A coherently coupled VCSEL array is a special type of VCSEL array. Within any group of VCSEL devices, coherent coupling between multiple VCSEL units can be achieved by individually adjusting the injection current of each VCSEL unit, thereby coupling the first optical signals emitted by multiple VCSEL units together and maintaining phase lock. In this embodiment, coherent coupling of VCSEL units only occurs within one group of VCSEL devices; VCSEL units in different groups are incoherent.

[0042] In this embodiment, by dividing the coherently coupled VCSEL array into multiple groups of VCSEL devices, the VCSEL units within each VCSEL device are coherently coupled, while the VCSEL units in different groups are incoherent, enabling individual control of each VCSEL device. The coherence and phase difference of the VCSEL units in each VCSEL device can be adjusted individually as needed, allowing the first optical signals emitted by different VCSEL devices to be coupled in different ways, thereby simulating different weight adjustments to the synaptic structure of a neuron.

[0043] In optional embodiments, such as Figure 1 As shown, the photodetector layer 300 includes multiple photodetectors, each corresponding to a set of VCSEL devices. Each photodetector is used to acquire the output light intensity of the corresponding VCSEL device. The output light intensity is determined based on the intensity of the first optical signal emitted by each VCSEL unit, the coherence between each VCSEL unit, and the phase difference between each first optical signal.

[0044] In this embodiment, multiple photodetectors are set up to collect the output light intensity of multiple VCSEL devices in a one-to-one correspondence, which can simultaneously detect the optical signal data (output light intensity) generated by multiple VCSEL devices, thereby providing comprehensive data collection.

[0045] A VCSEL unit is a semiconductor laser. The phase of the first optical signal emitted by the VCSEL unit can be controlled by controlling the injection current within the semiconductor cavity. By individually controlling the current injected into each VCSEL unit, the coherence and phase difference between the VCSEL units can be controlled, i.e., the phase difference of the first optical signal emitted by the VCSEL unit. Based on the principle of optical coherence, controlling the phase difference of the first optical signal can affect the way they interfere / couple with each other, and thus affect the total far-field light intensity (output light intensity) after they are coupled together, i.e., the calculation result.

[0046] Taking a 1×2 VCSEL device as an example, this group of VCSEL devices includes two coherently coupled VCSEL units. By adjusting the injection current injected into the two VCSEL units, the coherence of the two VCSEL units can be adjusted, that is, the phase difference between the two first optical signals emitted by the two VCSEL units can be controlled, so that the two first optical signals couple with each other in different ways, thereby achieving control over the total far-field light intensity (output light intensity). For example, when the two first optical signals have the same phase (phase difference is zero), the two first optical signals can coherently superimpose, resulting in an increase in the total far-field light intensity (output light intensity). Conversely, if the phase difference between the two first optical signals is 180° (π, or an odd multiple of π), the two first optical signals will undergo destructive interference, canceling each other out, and the total far-field light intensity (output light intensity) will decrease.

[0047] The total far-field light intensity (output light intensity) I can be approximately expressed by the following formula:

[0048] in, and These represent the light intensities of the first optical signals emitted by the two VCSEL units, respectively. This represents the coherence of two VCSEL units. This represents the phase difference between the first optical signals emitted by the two VCSEL units.

[0049] As can be seen, in this embodiment of the application, the coherently coupled VCSEL array layer 100 is used as the computing unit. By adjusting the coherence of the VCSEL unit, a variety of different optical computing can be achieved to meet different application requirements.

[0050] In an optional embodiment, the intensity and phase of the first optical signal emitted by each VCSEL unit are determined based on the injection current of the corresponding VCSEL unit. Correspondingly, the output optical intensity is determined based on the injection current of each VCSEL unit.

[0051] Taking a set of 1×2 VCSEL devices as an example, the total far-field light intensity (output light intensity) I can also be approximately expressed by the following formula: , These represent the injection current of each VCSEL cell.

[0052] like Figure 3 As shown, a set of VCSEL devices consists of three coherently coupled VCSEL units. Correspondingly, the output light intensity I can be expressed by the following formula: , These represent the injection current of each VCSEL cell.

[0053] In this embodiment, the total far-field light intensity (output light intensity) can be controlled by controlling the injection current of each VCSEL unit.

[0054] In an optional embodiment, each VCSEL device includes a first VCSEL unit and a second VCSEL unit, the first VCSEL unit and the second VCSEL unit are coherently coupled, the first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are mutually coupled, and the first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are phase locked.

[0055] like Figure 2As shown, each VCSEL device group includes two VCSEL units, which are coherently coupled, and the two emitted first optical signals are mutually coupled and phase-locked. In optical neural networks, such a group of VCSEL devices can be used to simulate the function of an artificial synapse. See below for details.

[0056] In an optional embodiment, each set of VCSEL devices and the corresponding photodetector are used together to simulate the function of a neuron in a biological neural network, wherein: a set of VCSEL devices is used to simulate the weight adjustment function of a synaptic structure in a neuron; and the photodetector is used to simulate the accumulation function of the cell body structure in a neuron.

[0057] For example, the first VCSEL unit is used to generate the input signal; the second VCSEL unit is used to apply weights to the input signal to form a corresponding output signal; and the photodetector is used to collect the intensity data of the output signal and sum them up.

[0058] like Figure 2 As shown, the first VCSEL unit on the left can be used to generate the input signal x, which can be obtained by converting the first electrical signal. The second VCSEL unit on the right can generate a weighted injection signal w, which is used to apply weight w to the input signal x, and finally generate the corresponding output signal. By constructing a coherently coupled VCSEL array layer 100 containing more sets of VCSEL devices, larger-scale simulation of artificial synaptic functions can be achieved. The photodetector array in the photodetector layer 300 can be designed to acquire and integrate the signals output by the VCSEL devices; one photodetector corresponds to one set of VCSEL devices.

[0059] The following provides an example of performing optical neural network operations based on the optical computing chip provided in the embodiments of this application.

[0060] In an optional embodiment, the first VCSEL unit is used to output a first timing optical signal, which is obtained by converting the first electrical signal. The second VCSEL unit is used to output a second timing optical signal, which is pre-trained timing weight information, and the weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the first output light intensity of the corresponding VCSEL device, and convert the accumulation result into the second electrical signal output. The first output light intensity is the intensity of the first output signal formed by the mutual coupling of the first timing optical signal and the second timing optical signal.

[0061] Taking the task of AI handwritten digit recognition as an example, the goal is to recognize handwritten digits (0~9) in an image.

[0062] The input handwritten digit image is encoded into time-series current or voltage information (first electrical signal). Time-series current refers to a current signal that changes in a certain time sequence. In a set of 1×2 VCSEL devices, the first VCSEL unit is used to convert the time-series current or voltage information into a first time-series optical signal x. The time-series optical signal can be a series of light pulses that occur in a certain order or at certain time intervals. The second VCSEL unit is used to output a second time-series optical signal, which is a pre-trained time-series weighted signal. The first and second time-series optical signals propagate through a buffer layer 200 and couple with each other during propagation to form a first output signal. The first output light intensity is collected by a photodetector in the photodetector layer 300 and accumulated (integrated). The accumulated (integrated) result is converted into a second electrical signal for output. Specifically, optical computation is performed using 100 sets of VCSEL devices, each set using a different weight w, resulting in 100 different first output signals. In some embodiments, a corresponding number (0~9) can be configured for the photodetector corresponding to each group of VCSEL devices. The first output light intensity of each group of VCSEL devices is collected by 100 photodetectors and integrated. The integration result is converted into 100 second electrical signals and output. The number corresponding to the photodetector with the largest integration result is used as the recognition result.

[0063] In the above embodiments, a single round of optical neural network computation is performed by the optical computing chip to quickly obtain the recognition result of handwritten digits. To obtain more accurate recognition results, multiple rounds of optical neural network computation can be performed using the optical computing chip of this application embodiment, as detailed below.

[0064] In an optional embodiment, the first VCSEL unit is further configured to output a third timing optical signal, which is obtained by timing encoding multiple second electrical signals generated by multiple photodetectors. The second VCSEL unit is configured to output a fourth timing optical signal, which is pre-trained timing weight information, with different weight information corresponding to each group of VCSEL devices. The photodetector is configured to acquire and accumulate the second output light intensity of the corresponding VCSEL device, convert the accumulation result into the third electrical signal, and output it. The second output light intensity is the intensity of the second output signal formed by the coupling of the third and fourth timing optical signals.

[0065] Multiple second electrical signals generated in one round of calculation are sequentially encoded into a third time-series optical signal x. In a set of 1×2 VCSEL devices, the third time-series optical signal x is output through the first VCSEL unit, and a weight w is applied to the third time-series optical signal through the second VCSEL unit. Each set of VCSEL devices applies a different weight. The third and fourth time-series optical signals propagate through buffer layer 200 and couple with each other during propagation to form a second output signal. The intensity of the second output light is collected and accumulated (integrated) by the photodetector of photodetector layer 300, and the accumulated (integrated) result is converted into a third electrical signal output. For example, in the second round of calculation, 10 sets of VCSEL devices are used to sequentially encode the 100 second electrical signals from the first round into the third time-series optical signal x, with each set of VCSEL devices applying a different weight w to the third time-series optical signal x. Then, the output light intensity of the second output signal generated by each group of VCSEL devices is collected and integrated using 10 photodetectors (corresponding to digits 0-9). The integrated result is converted into 10 third electrical signals for output, and the digit corresponding to the photodetector with the largest integrated result is taken as the recognition result. This multi-round optical computation improves the accuracy of optical calculation, resulting in more accurate handwritten digit recognition. It should be noted that, depending on the complexity of the task being performed, the optical computing chip can perform multiple rounds of optical computation to obtain better results; this is not limited here.

[0066] The above embodiments describe a technical solution for simulating neuronal synaptic structures using a 1×2 VCSEL device. In some embodiments, 1×3, 1×4, and larger-scale VCSEL devices can also be used to simulate more complex synaptic functions, thereby addressing more complex tasks. For example, when two sets of associated input data are input simultaneously, the output signal I can be represented as: ,in This represents two input data points, and w represents the weight information. Two specific exemplary schemes will be provided below.

[0067] In an optional embodiment, each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, and a third VCSEL unit. The first electrical signal includes a first electrical signal and a first second electrical signal. The first VCSEL unit is used to output a fifth timing optical signal, which is obtained by converting the first electrical signal. The second VCSEL unit is used to output a sixth timing optical signal, which is obtained by converting the first second electrical signal. The third VCSEL unit is used to output a seventh timing optical signal, which is pre-trained timing weight information, and the weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the third output light intensity of the corresponding VCSEL device, convert the accumulation result into the second electrical signal, and output it. The third output light intensity is the intensity of the third output signal formed by the mutual coupling of the fifth, sixth, and seventh timing optical signals.

[0068] Taking image association recognition as an example, the goal is to calculate the similarity or degree of association between two or more images. For instance, if both image A and image B contain animals, the association between the two images needs to be calculated.

[0069] In this embodiment, the input image A is encoded as a first electrical signal, and the input image B is encoded as a first second electrical signal. In a set of 1×3 VCSEL devices, the first VCSEL unit is used to convert the first electrical signal into a fifth time-series optical signal x1. The second VCSEL unit is used to convert the first second electrical signal into a sixth time-series optical signal x2, and the third VCSEL unit is used to output a seventh time-series optical signal w, which is pre-trained time-series weight information. The fifth, sixth, and seventh time-series optical signals propagate through the buffer layer 200 and couple with each other during propagation to form a third output signal. The intensity of the third output light is collected by the photodetector of the photodetector layer 300 and accumulated (integrated). The accumulated (integrated) result is converted into a second electrical signal for output. The similarity between image A and image B can be determined based on the intensity of the output second electrical signal.

[0070] In an optional embodiment, each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, a third VCSEL unit, and a fourth VCSEL unit. The first electrical signal includes a first-order electrical signal, a first-second electrical signal, and a first-third electrical signal. The first VCSEL unit is used to output an eighth timing optical signal, which is obtained by converting the first-order electrical signal. The second VCSEL unit is used to output a ninth timing optical signal, which is obtained by converting the first-second electrical signal. The third VCSEL unit is used to output a tenth timing optical signal, which is obtained by converting the first-third electrical signal. The fourth VCSEL unit is used to output an eleventh timing optical signal, which is pre-trained timing weight information, and the weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the fourth output light intensity of the corresponding VCSEL device, convert the accumulated result into the second electrical signal, and output it. The fourth output light intensity is the intensity of the fourth output signal formed by the mutual coupling of the eighth, ninth, tenth, and eleventh time-series optical signals.

[0071] Taking image correlation recognition as an example, the 1×4 VCSEL device in this embodiment can be used to determine the correlation between three images. The three images are encoded into three different first electrical signals, and three VCSEL units convert these first electrical signals into different temporal optical signals (x1, x2, x3) for output. The last VCSEL unit outputs an eleventh temporal optical signal x4, which is used to apply weights. The temporal optical signals x1, x2, x3, and x4 interfere and couple with each other during propagation to form a fourth output signal. The intensity of the fourth output light is collected by the photodetector of the photodetector layer 300 and accumulated (integrated). The accumulated (integrated) result is converted into a second electrical signal for output. The similarity between the three images can be determined based on the intensity of the output second electrical signal.

[0072] Similarly, the more VCSEL units a VCSEL device has, the more complex the synaptic functions it can simulate. By constructing a coherently coupled VCSEL array with more VCSEL units, it is possible to simulate artificial synaptic functions on a larger scale, effectively improving computing power.

[0073] In the description of this specification, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0074] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0075] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0076] It should be noted that although the steps of the method in this application are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. The above drawings are merely illustrative of the processes included in the method according to exemplary embodiments of this application and are not intended to be limiting. It is readily understood that the processes shown in the above drawings do not indicate or limit the temporal order of these processes. Furthermore, it is readily understood that these processes may be performed synchronously or asynchronously in multiple modules, for example.

[0077] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An optical computing chip, characterized in that, It includes a coherently coupled VCSEL array layer, a buffer layer, and a photodetector layer stacked sequentially; wherein: The coherently coupled VCSEL array layer is used to convert the first electrical signal into a first optical signal and output it. The buffer layer is used to propagate the first optical signal, and the first optical signal is coupled to each other during the propagation process to form an output signal; The photodetector layer is used to acquire the output light intensity of the output signal and convert the output light intensity into a second electrical signal for output. The coherently coupled VCSEL array layer includes multiple groups of VCSEL devices, each group of VCSEL devices includes multiple VCSEL units, the VCSEL units in the same group of VCSEL devices are coherently coupled, and the VCSEL units in different groups of VCSEL devices are not coherently coupled. In this setup, the first optical signals emitted by multiple VCSEL units in the same group of VCSEL devices are coupled to each other and are phase-locked.

2. The optical computing chip according to claim 1, characterized in that, The photodetector layer includes multiple photodetectors, and each photodetector corresponds to a set of VCSEL devices. Each photodetector is used to acquire the output light intensity of the corresponding VCSEL device. The output light intensity is determined based on the intensity of the first light signal emitted by each VCSEL unit, the coherence between each VCSEL unit, and the phase difference between each first light signal.

3. The optical computing chip according to claim 2, characterized in that, The intensity and phase of the first optical signal emitted by each VCSEL unit are determined according to the injection current of the corresponding VCSEL unit; Correspondingly, the output light intensity is determined based on the injection current of each VCSEL unit.

4. The optical computing chip according to claim 2, characterized in that, Each VCSEL device group includes a first VCSEL unit and a second VCSEL unit. The first VCSEL unit and the second VCSEL unit are coherently coupled. The first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are mutually coupled, and the first optical signal emitted by the first VCSEL unit and the first optical signal emitted by the second VCSEL unit are phase locked.

5. The optical computing chip according to claim 4, characterized in that, Each VCSEL device, together with its corresponding photodetector, is used to simulate the function of a neuron in a biological neural network, where: A set of VCSEL devices is used to simulate the weight modulation function of a synaptic structure in a neuron; wherein, a first VCSEL unit is used to generate an input signal; and a second VCSEL unit is used to apply weights to the input signal to form a corresponding output signal; Photodetectors are used to simulate the accumulation function of cell body structures in neurons.

6. The optical computing chip according to claim 4, characterized in that, The first VCSEL unit is used to output a first timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a second timing optical signal, which is pre-trained timing weight information. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire the first output light intensity of the corresponding VCSEL device and accumulate it, and then convert the accumulation result into the second electrical signal output. Wherein, the first output light intensity is the intensity of the first output signal formed by the mutual coupling of the first timing optical signal and the second timing optical signal.

7. The optical computing chip according to claim 4, characterized in that, The first VCSEL unit is also used to output a third timing optical signal, which is obtained by timing encoding multiple second electrical signals generated by multiple photodetectors. The second VCSEL unit is used to output a fourth timing optical signal, which is pre-trained timing weight information. The weight information corresponding to each group of VCSEL devices is different. The photodetector is used to acquire and accumulate the second output light intensity of the corresponding VCSEL device, and convert the accumulation result into a third electrical signal and output it. Wherein, the second output light intensity is the intensity of the second output signal formed by the mutual coupling of the third timing optical signal and the fourth timing optical signal.

8. The optical computing chip according to claim 2, characterized in that, Each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, and a third VCSEL unit; The first electrical signal includes a first electrical signal and a first second electrical signal; The first VCSEL unit is used to output a fifth timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a sixth timing optical signal, which is obtained by conversion based on the first two electrical signals; The third VCSEL unit is used to output the seventh timing optical signal, which is the weight information of the timing sequence pre-trained. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the third output light intensity of the corresponding VCSEL device, and convert the accumulation result into the second electrical signal and output it. The third output light intensity is the intensity of the third output signal formed by the mutual coupling of the fifth, sixth, and seventh time-series optical signals.

9. The optical computing chip according to claim 2, characterized in that, Each group of VCSEL devices includes a first VCSEL unit, a second VCSEL unit, a third VCSEL unit, and a fourth VCSEL unit; The first electrical signal includes a first electrical signal, a first second electrical signal, and a first third electrical signal; The first VCSEL unit is used to output an eighth timing optical signal, which is obtained by conversion based on the first electrical signal; The second VCSEL unit is used to output a ninth timing optical signal, which is obtained by conversion based on the first two electrical signals; The third VCSEL unit is used to output the tenth timing optical signal, which is obtained by conversion based on the first three electrical signals. The fourth VCSEL unit is used to output the eleventh timing optical signal, which is the weight information of the timing sequence pre-trained. The weight information corresponding to each group of VCSEL devices is different. Each photodetector is used to acquire and accumulate the fourth output light intensity of the corresponding VCSEL device, and convert the accumulation result into the second electrical signal and output it. The fourth output light intensity is the intensity of the fourth output signal formed by the mutual coupling of the eighth, ninth, tenth, and eleventh time-series optical signals.

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