Gate drive circuit and display device

Abstract

The application discloses a gate driving circuit and a display device. The gate driving circuit comprises a plurality of cascaded gate driving units, each of which comprises a selection module receiving a selection signal and a driving circuit connected with the selection module, which provides a current-stage transfer signal and a current-stage gate driving signal according to a plurality of signals and a control voltage. The current-stage gate driving signal is output to a corresponding pixel row, which is selected when the current-stage gate driving signal is in an effective voltage level. When the selection signal indicates that the corresponding display data of the current frame and the previous frame is consistent, the selection module adjusts the control voltage according to the selection signal to make the current-stage gate driving signal in an invalid voltage level and the current-stage transfer signal in an effective voltage level. The control of the gate driving signal output by each gate driving unit can individually turn on the pixel row corresponding to at least part of the gate driving units, thereby reducing power consumption.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] A display device is a tool that transmits display data to a display panel via a transmission device and then reflects it to the human eye. Examples of display devices include liquid crystal displays (LCDs), plasma display panels (PDPs), organic light-emitting diode (OLED) displays, and electrophoretic displays (EPDs).

[0003] Taking a thin-film transistor (TFT) liquid crystal display device as an example, it includes a liquid crystal display panel and a driving circuit. The liquid crystal display panel includes multiple scan lines and multiple data lines, and two adjacent scan lines and two adjacent data lines intersect to form a pixel unit. Each pixel unit includes at least one thin-film transistor. The driving circuit includes a gate drive circuit and a source drive circuit.

[0004] The gate drive circuit sends a gate drive signal Gn to the scan line through a pull-up transistor electrically connected to the scan line, sequentially turning on the TFTs of each row. Then, the source drive circuit simultaneously charges the pixel units of an entire row to their respective required voltages to display different gray levels. However, this results in significant power consumption waste when displaying a static image or an image where only partial changes to the displayed content are needed.

[0005] In existing technologies, power consumption is typically reduced by using low-voltage charging, thickening the conductors to reduce conductor resistance, or using metal oxide thin films. However, low-voltage charging may result in incomplete charging, reducing display quality; increased conductor width leads to reduced usable space and increased capacitance between lines; and using metal oxide thin films requires high process capabilities and is difficult to implement.

[0006] Therefore, there is an urgent need for a new gate driving circuit and display device. Summary of the Invention

[0007] In view of the above problems, the purpose of this application is to provide a gate driving circuit and a display device, which controls the gate driving signal output by each gate driving unit to individually turn on at least some of the pixel rows corresponding to the gate driving units, thereby reducing power consumption.

[0008] According to one aspect of this application, a gate driving circuit is provided, comprising a plurality of cascaded gate driving units, wherein each gate driving unit comprises: a selection module for receiving a selection signal; and a driving circuit connected to the selection module, providing a current-stage transmission signal and a current-stage gate driving signal according to a plurality of input signals of the driving circuit and a control voltage, the plurality of input signals including a previous-stage transmission signal and / or a subsequent-stage transmission signal, the current-stage gate driving signal being output to a corresponding pixel row, the pixel row being selected when the current-stage gate driving signal is at an active level, and when the selection signal indicates that the display data corresponding to the pixel row is consistent in the current frame and the previous frame, the selection module adjusts the control voltage according to the selection signal to make the current-stage gate driving signal at an inactive level and the current-stage transmission signal at an active level.

[0009] Optionally, each of the gate driving units receives a selection signal corresponding to that gate driving unit; or the selection signal includes multiple data segments corresponding to each of the pixel rows, and each of the gate driving units adjusts the control voltage according to the corresponding data segment in the selection signal.

[0010] Optionally, the plurality of input signals further includes a first clock signal, the selection module includes a first switching element, the control terminal of the first switching element receives the selection signal, the first path terminal receives the first clock signal, the second path terminal is a first node, and outputs the control voltage.

[0011] Optionally, the plurality of input signals further includes a second clock signal. The driving circuit includes: an input module for adjusting the second node voltage according to the pre-stage transmission signal or the post-stage transmission signal and the second clock signal; and an output module connected to the input module at the second node. The output module includes a first output module and a second output module. The first output module is connected to the first node, the second node, and a gate drive signal output terminal to output the gate drive signal of this stage according to the control voltage and the second node voltage. The second output module is connected to the second node and a transmission signal output terminal to output the transmission signal of this stage according to the second node voltage and the first clock signal.

[0012] Optionally, the first clock signal and the second clock signal have the same period and duty cycle, and when the first clock signal is at its falling edge, the second clock signal is at its rising edge. The input module includes a second switching element and a third switching element: the control terminal of the second switching element is shorted to the first path terminal to receive the pre-stage transmitted signal, and the second path terminal is the second node; the control terminal of the third switching element receives the post-stage transmitted signal, the first path terminal is connected to the second node, and the second path terminal receives the second clock signal; the first output module includes a fourth switching element and a capacitor, the control terminal of the fourth switching element is connected to the second node, the first path terminal is connected to the first node, and the second path terminal is connected to the gate drive signal output terminal; the first terminal of the capacitor is connected to the control terminal of the fourth switching element, and the second terminal is connected to the second path terminal of the fourth switching element; the second output module includes a fifth switching element, the control terminal of the fifth switching element is connected to the second node, the first path terminal receives the first clock signal, and the second path terminal is connected to the transmitted signal output terminal.

[0013] Optionally, the plurality of input signals further includes a first timing signal, a second timing signal, a first reference signal, and a second reference signal. The gate drive circuit further includes: a pull-down module connected to the second node, which adjusts the voltages of the third node and the fourth node according to the voltage of the second node; and a stabilization module, including a first stabilization module and a second stabilization module connected to the third node and the fourth node. The first stabilization module is also connected to the pull-down module at the third node, and the second stabilization module is also connected to the pull-down module at the fourth node. The first stabilization module or the second stabilization module stabilizes the gate drive signal and the local transmission signal according to the voltage of the third node, the voltage of the fourth node, the first timing signal, the second timing signal, the first reference signal, and the second reference signal.

[0014] Optionally, the first timing signal and the second timing signal have the same period and duty cycle, and their phases are always opposite; both the first reference signal and the second reference signal are low-level reference signals; the pull-down module includes a sixth switching element and a seventh switching element; the first stabilization module includes an eighth to a thirteenth switching element; the second stabilization module includes a fourteenth to a nineteenth switching element; the control terminal of the sixth switching element is connected to the second node, the first path terminal receives the first reference signal, and the second path terminal is the third node; the control terminal of the seventh switching element is connected to the second node, and the first path terminal receives the first reference signal. The second path terminal is the fourth node; the control terminal of the eighth switching element is short-circuited with the first path terminal to receive the first timing signal, and the second path terminal is connected to the third node; the control terminal of the ninth switching element receives the first timing signal, the first path terminal receives the first reference signal, and the second path terminal is connected to the fourth node; the control terminal of the tenth switching element receives the first timing signal, the first path terminal is connected to the first node, and the second path terminal receives the first reference signal; the control terminal of the eleventh switching element is connected to the third node, the first path terminal is connected to the second node, and the second path terminal receives the second reference signal; the control terminal of the twelfth switching element is connected to the fourth node ... The third node is connected, and the first path terminal is connected to the gate drive signal output terminal; the second path terminal receives the second reference signal; the control terminal of the thirteenth switching element is connected to the third node, and the first path terminal is connected to the transmission signal output terminal; the second path terminal receives the second reference signal; the control terminal and the second path terminal of the fourteenth switching element are shorted to receive the second timing signal, and the first path terminal is connected to the fourth node; the control terminal of the fifteenth switching element receives the second timing signal, the first path terminal is connected to the third node, and the second path terminal receives the first reference signal; the control terminal of the sixteenth switching element receives the second timing signal, and the first path terminal... The first reference signal is received, and the second path terminal is connected to the first node; the control terminal of the seventeenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the second node; the control terminal of the eighteenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the gate drive signal output terminal; the control terminal of the nineteenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the transmission signal output terminal; the size of the first switching element is at least larger than the sizes of the tenth and sixteenth switching elements.

[0015] According to another aspect of this application, a display device is provided, comprising: a gate driving circuit as described in any of the preceding claims; and a selection signal generating circuit connected to the gate driving circuit to provide the selection signal to each of the gate driving units of the gate driving circuit.

[0016] Optionally, the display device further includes: a display panel including a plurality of pixels arranged in an array; and a data driving circuit connected to the selection signal generation circuit and the corresponding pixels, wherein when the selection signal indicates that the display data of the pixel row is inconsistent in the current frame and the previous frame, the data driving circuit provides a corresponding data voltage to each pixel of the pixel row.

[0017] Optionally, the selection signal generation circuit includes: a storage module for storing display data and outputting the display data corresponding to the previous frame when the selection signal generation circuit receives the display data corresponding to the current frame; and a comparison module connected to the storage module for comparing the display data corresponding to the current frame and the previous frame line by line and outputting the selection signal with the corresponding level state.

[0018] According to the gate driving circuit provided in this application, during the operation of the display device, when the selection signal indicates that the display data of the pixel row is consistent in the current frame and the previous frame, the gate driving signal of this stage is in an invalid state, and the transmission signal of this stage is in an active state. Therefore, the corresponding pixel row can be activated according to the changes in the display images of two adjacent frames, thereby reducing power consumption. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 This diagram illustrates a schematic structure of a cascaded four-stage gate drive unit in a gate drive circuit according to an embodiment of this application.

[0021] Figure 2 Show Figure 1 The timing diagram of the clock signal provided by the gate drive circuit is shown.

[0022] Figure 3 Show Figure 1 A schematic block diagram of the nth gate drive unit in the gate drive circuit shown.

[0023] Figure 4 Show Figure 3 The schematic circuit diagram of the nth stage gate drive unit is shown.

[0024] Figure 5A schematic timing diagram of the nth gate drive unit is shown during the period when the selection signal is at a preset level;

[0025] Figure 6 A schematic timing diagram of the nth stage gate drive unit is shown during the period when the selection signal is not at a preset level;

[0026] Figure 7 The simulation waveforms of multiple signals of the nth stage gate drive unit are shown when the selection signal is at an active level.

[0027] Figure 8 The simulation waveforms of multiple signals of the nth stage gate drive unit are shown when the selection signal is not at an active level.

[0028] Figure 9 The diagram shows waveforms of gate drive signals for multiple gate drive units in embodiments of this application.

[0029] Figure 10 This diagram illustrates a schematic structural block diagram of the display device provided in an embodiment of this application;

[0030] Figure 11 Show Figure 10 A schematic block diagram of the selected signal generation module; Detailed Implementation

[0031] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0032] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0033] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0034] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0035] The gate driving circuit provided in this application includes a multi-level gate driving unit. Each level of gate driving unit is electrically connected to a row of pixel units on the display panel through a corresponding scan line, thereby applying the gate driving signal to the corresponding pixel unit row by row in sequence.

[0036] Figure 1 This diagram illustrates a schematic structure of a cascaded multi-stage gate drive unit in an embodiment of this application. Figure 1 As shown, a four-stage cascaded gate drive unit is used as an example. Each stage of the gate drive unit includes multiple input ports and multiple output ports. Specifically, the input ports include:

[0037] A selection signal input port is used to receive a selection signal Syn. In some embodiments, each gate driving unit receives a selection signal corresponding to it; that is, the selection signals received by each gate driving unit are at least partially independent of each other. In the embodiments of this application, each gate driving unit receives the same selection signal, which includes multiple data segments corresponding to each pixel row, and each gate driving unit receives the selection signal for the corresponding data segment.

[0038] Multiple clock signal input ports are used to receive multiple clock signals CLK. In this embodiment, the clock signals received by each gate drive unit include a first clock signal CLK k and a second clock signal CLK k+1. CLK k and CLK k+1 are square wave signals with the same period and duty cycle, and when the first clock signal CLK k changes from high to low (i.e., when the first clock signal is at its falling edge), the second clock signal CLK k+1 changes from low to high (i.e., when the second clock signal is at its rising edge). Figure 1In the cascaded gate drive circuit shown, four clock signals CLK1 to CLK4 are provided. The first-stage gate drive unit receives clock signals CLK1 and CLK2, the second-stage gate drive unit receives clock signals CLK2 and CLK3, the third-stage gate drive unit receives clock signals CLK3 and CLK4, and the fourth-stage gate drive unit receives clock signals CLK4 and CLK1. Further, Figure 2 Show Figure 1 The timing diagram shows the clock signals (CLK1-CLK4) provided by the gate drive circuit. For example... Figure 1 The four-stage cascaded gate drive unit shown has CLK1 to CLK4 as square wave signals with a clock period of 4T and a duty cycle of 1 / 4. Here, T is a predetermined clock period, such as the minimum clock period of the system clock signal or an integer multiple thereof.

[0039] Multiple timing signal input ports are used to receive multiple timing signals. In this embodiment, the timing signals received by each gate drive unit include the same first timing signal V1 and the same second timing signal V2. The first timing signal V1 and the second timing signal V2 are, for example, both low-frequency signals. The first timing signal V1 and the second timing signal V2 have the same period and duty cycle, and the phases of the first timing signal V1 and the second timing signal V2 are always opposite (i.e., when the first timing signal V1 is high, the second timing signal V2 is low; when the first timing signal V1 is low, the second timing signal V2 is high).

[0040] Multiple reference signal input ports are used to receive multiple reference signals. In this embodiment, the reference signals received by each gate drive unit include the same first reference signal VSQ and the same second reference signal VGL, both of which are low-level reference signals.

[0041] Multiple signal input ports are provided for receiving multiple transmitted signals. Specifically, in the embodiments of this application, for the nth stage gate driving unit, the transmitted signals include the preceding stage transmitted signal Zn-2 (i.e., the transmitted signal output by the gate driving unit two stages ahead) and the following stage transmitted signal Zn+2 (i.e., the transmitted signal output by the gate driving unit two stages behind). It should be noted that, in cases such as... Figure 1In the connection configuration shown, the first and second stage gate driving units do not have gate driving units that differ by two stages forward, and the penultimate and penultimate stage gate driving units do not have gate driving units that differ by two stages backward. Therefore, in this embodiment, the first pulse signal STV1 and the second pulse signal STV2 are provided to the first and second stage gate driving units respectively by an external signal circuit (e.g., directly provided by a timing control circuit or provided via a data driving circuit) as corresponding pre-stage transmission signals; simultaneously, the third pulse signal STV3 and the fourth pulse signal STV4 are provided to the penultimate and penultimate stage gate driving units respectively by an external signal circuit (e.g., directly provided by a timing control circuit or provided via a data driving circuit) as corresponding post-stage transmission signals. However, it should be understood that in some other embodiments, STV1 and STV2 are the same, and STV3 and STV4 are the same.

[0042] In addition, for the nth stage gate drive unit, the output ports include: a gate drive signal output port for outputting the gate drive signal Gn of this stage; and a transmission signal output port for outputting the transmission signal Zn of this stage.

[0043] Figure 3 This diagram illustrates a schematic structural block diagram of the nth-stage gate driving unit in an embodiment of the present application. Figure 4 Show Figure 3 The diagram shows a schematic circuit of the nth-stage gate driving unit. The gate driving circuit of this embodiment includes multiple stages such as... Figure 3 The gate driving unit 310 shown has each stage electrically connected to a corresponding pixel row on the display panel via a corresponding scan line, thereby sequentially applying gate driving signals to the corresponding pixel row. For example... Figure 3 and Figure 4 As shown, the gate driving unit 310 includes a selection module 311 and a driving circuit 10. The driving circuit 10 includes an input module 312, a pull-down module 313, an output module 314, and a stabilization module 315.

[0044] The selection module 311 receives the selection signal Syn.

[0045] The driving circuit 10 and the selection module 311 are connected to the first node Sn. Based on multiple input signals of the driving circuit and the control voltage (i.e., the first node voltage), the driving circuit provides the transmission signal and the gate driving signal for this stage. The gate driving signal for this stage is output to the corresponding pixel row, which is selected when the gate driving signal for this stage is at an active level.

[0046] When the selection signal indicates that the display data of the pixel row is consistent in the current frame and the previous frame, the selection module adjusts the control voltage according to the selection signal to make the gate drive signal of this stage invalid and the transmission signal of this stage valid.

[0047] The connection relationships and signal relationships of each module are described in detail below.

[0048] Selection module 311 is used to adjust the control voltage (Sn point voltage) according to the selection signal Syn and the first clock signal CLK k.

[0049] The input module 312 is used to adjust the voltage of the second node (Q point) according to the pre-stage transmitted signal Zn-2, the post-stage transmitted signal Zn+2 and the second clock signal CLK k+1.

[0050] Output module 314 includes a first output module 3141 and a second output module 3142. The first output module 3141 is connected to the selection module 311 at the first node Sn and to the input module 312 at the second node Q. When the selection signal indicates that the display data of the pixel row in the current frame and the previous frame are inconsistent (i.e., the selection signal is at a preset level), the gate drive signal Gn of this stage is controlled by the voltage of the second node Q and follows the first clock signal CLK k. When the selection signal indicates that the display data of the pixel row in the current frame and the previous frame are consistent (i.e., the selection signal is not at a preset level), the gate drive signal Gn of this stage is always at an invalid level.

[0051] The second output module 3142 is connected to the input module 312 at the second node Q, and outputs the current stage transmission signal Zn according to the voltage of the second node Q and the first clock signal CLK k.

[0052] The pull-down module 313 is connected to the second node Q and also to the stabilization module 315 at the third node QB1 and the fourth node QB2, and is used to adjust the voltage of the third node QB1 and the fourth node QB2 according to the voltage at point Q and the first reference signal VSQ.

[0053] The stabilization module 315 includes a first stabilization module 3151 and a second stabilization module 3152. The first stabilization module 3151 is connected to the pull-down module 313 at the third node QB1; the second stabilization module 3152 is connected to the pull-down module 313 at the fourth node QB2, and the first stabilization module 3151 and the second stabilization module 3152 are connected to the third node QB1 and the fourth node QB2. The first stabilization module 3151 is controlled by a first timing signal V1, and the second stabilization module 3152 is controlled by a second timing signal V2. The first timing signal V1 and the second timing signal V2, which have the same period and duty cycle but are always opposite in phase, control the first stabilization module 3151 and the second stabilization module 3152 to work alternately, thereby stabilizing the current stage gate drive signal Gn, the current stage transmission signal Zn, the voltage of the first node Sn, and the voltage of the second node Q.

[0054] Furthermore, Figure 4 Show Figure 3 The diagram shows a schematic circuit of the nth-stage gate drive unit.

[0055] like Figure 4 As shown:

[0056] The selection module 311 includes a first switching element T1. The control terminal of the first switching element T1 receives the selection signal Syn, the first path terminal receives the first clock signal CLK k, and the second path terminal serves as the first node Sn and outputs a control voltage.

[0057] The input module 312 includes a second switching element T2 and a third switching element T3. The control terminal of the second switching element T2 is shorted to the first path terminal and receives the preceding stage transmission signal Zn-2. The second path terminal serves as the second node Q. The control terminal of the third switching element T3 receives the following stage transmission signal Zn+2. The first path terminal is connected to the second node Q, and the second path terminal receives the second clock signal CLK k+1.

[0058] The first output module 3141 includes a fourth switching element T4 and a capacitor C. The control terminal of the fourth switching element T4 is connected to the second node Q, the first path terminal is connected to the first node Sn, and the second path terminal is connected to the gate drive signal output terminal to output the gate drive signal Gn of this stage. The first terminal of the capacitor C is connected to the control terminal of the fourth switching element T4, and the second terminal is connected to the second path terminal of the fourth switching element T4. In some embodiments, the capacitor C is the parasitic capacitance between the control terminal and the second path terminal of the fourth switching element T4. However, it should be understood that in other embodiments, in order to improve the coupling effect of the capacitor and thus improve the pull-up effect of the Q-point voltage, an independent capacitor is also provided between the control terminal and the second path terminal of the fourth switching element T4, and the capacitor C is the sum of the parasitic capacitance between the control terminal and the second path terminal of the fourth switching element T4 and the independent capacitance.

[0059] The second output module 3142 includes a fifth switching element T5. The control terminal of the fifth switching element T5 is connected to the second node Q, the first path terminal receives the first clock signal CLK k, and the second path terminal is connected to the output terminal of the current stage's transmitted signal, outputting the current stage's transmitted signal Zn.

[0060] The pull-down module 313 includes a sixth switching element T6 and a seventh switching element T7. The control terminal of the sixth switching element T6 is connected to the second node Q, the first path terminal receives the first reference signal VSQ, and the second path terminal serves as the third node QB1. The control terminal of the seventh switching element T7 is connected to the second node Q, the first path terminal receives the first reference signal VSQ, and the second path terminal serves as the fourth node QB2.

[0061] The first stabilization module 3151 includes eighth switching elements T8 to thirteenth switching elements T13. The control terminal of the eighth switching element T8 is shorted to the first path terminal and receives the first timing signal V1; its second path terminal is connected to the third node QB1. The control terminal of the ninth switching element T9 receives the first timing signal V1; its first path terminal receives the first reference signal VSQ; its second path terminal is connected to the fourth node QB2. The control terminal of the tenth switching element T10 receives the first timing signal V1; its first path terminal is connected to the first node Sn; its second path terminal receives the first reference signal VSQ. The control terminal of the eleventh switching element T11 is connected to the third node QB1; its first path terminal is connected to the second node Q; its second path terminal receives the second reference signal VGL. The control terminal of the twelfth switching element T12 is connected to the third node QB1; its first path terminal is connected to the gate drive signal output terminal; its second path terminal receives the second reference signal VGL. The control terminal of the thirteenth switching element T13 is connected to the third node QB1; its first path terminal is connected to the transmission signal output terminal; its second path terminal receives the second reference signal VGL.

[0062] The second stabilization module 3152 includes fourteenth to nineteenth switching elements T14 to T19. The control terminal and second path terminal of the fourteenth switching element T14 are shorted to receive the second timing signal V2, and its first path terminal is connected to the fourth node QB2. The control terminal of the fifteenth switching element T15 receives the second timing signal V2, its first path terminal is connected to the third node QB1, and its second path terminal receives the first reference signal VSQ. The control terminal of the sixteenth switching element T16 receives the second timing signal V2, its first path terminal receives the first reference signal VSQ, and its second path terminal is connected to the first node Sn. The control terminal of the seventeenth switching element T17 is connected to the fourth node QB2, its first path terminal receives the second reference signal VGL, and its second path terminal is connected to the second node Q. The control terminal of the eighteenth switching element T18 is connected to the fourth node QB2, its first path terminal receives the second reference signal VGL, and its second path terminal is connected to the gate drive signal output terminal. The control terminal of the nineteenth switching element is connected to the fourth node QB2, its first path terminal receives the second reference signal VGL, and its second path terminal is connected to the signal output terminal.

[0063] Furthermore, in such Figure 4 In the illustrated embodiment, taking N-type transistors as an example where the first to nineteenth switching elements are all examples, the control terminal of each switching element is the gate, the first pass terminal is the drain, and the second pass terminal is the source. However, it should be understood that in the embodiments of this application, the first and second pass terminals of each switching element can be interchanged (i.e., the drain and source can be interchanged). Furthermore, it should also be understood that the switching elements of this application should not be limited thereto.

[0064] Figure 5 This diagram illustrates the schematic timing of the nth gate drive unit during a selected signal at a preset level. CLKk and CLKk+1 are square wave signals with the same period (e.g., 4T) and duty cycle (e.g., 1 / 4). When the first clock signal CLKk changes from high to low (i.e., when the first clock signal is at its falling edge), the second clock signal CLKk+1 changes from low to high (i.e., when the second clock signal is at its rising edge).

[0065] Combination Figure 4 and Figure 5 When the selection signal is at a preset level, the first switching element T1 is turned on, and the voltage of the first node (Sn point) follows the first clock signal CLK k. The operation process of each stage of the gate drive unit is divided into a pre-charge stage, a pull-up stage, a pull-down stage, and a stabilization stage.

[0066] Pre-charge phase: In this embodiment, the pre-stage transfer signal Zn-2 is used as the pre-charge signal. The level of the pre-stage transfer signal Zn-2, output by the gate drive unit two stages ahead, changes from low to high, and the second switching element T2 is turned on. Point Q is pre-charged through the turned-on second switching element T2. As the voltage at point Q increases, the fourth switching element T4, the fifth switching element T5, the sixth switching element T6, and the seventh switching element T7 are gradually turned on. Furthermore, with the turn-on of the sixth switching element T6 and the seventh switching element T7, the voltages of the third node QB1 and the fourth node QB2 are pulled down to the low level of the first reference signal VSQ. Therefore, the eleventh to thirteenth switching elements (T11 to T13) and the seventeenth to nineteenth switching elements (T17 to T19) are all turned off. Furthermore, during the pre-charging phase, the tenth switching element T10 and the sixteenth switching element T16 are alternately turned on under the control of the first timing signal V1 and the second timing signal V2, thereby pulling the voltage of the first node Sn down to the low level of the first reference signal VSQ.

[0067] Pull-up phase: When the level of the first clock signal CLKk changes from low to high, since the selection signal Syn is at a high level, the first switching element T1 is always on, and the voltage at the first node Sn is pulled high along with the first clock signal CLKk. Furthermore, during the pre-charge phase, point Q has already been pre-charged, meaning both the fourth switching element T4 and the fifth switching element T5 are on. Due to the bootstrap effect of capacitor C, the voltage at the second node Q is further pulled high, making the fourth switching element T4 more fully on, thus allowing the gate drive signal Gn output by the gate drive unit to be pulled high by the first clock signal CLKk through the on-state first switching element T1 and fourth switching element T4. Similarly, as the voltage at the second node Q further increases, the fifth switching element T5 is also more fully on, thus allowing the transmission signal Zn output by the gate drive unit to be pulled high by the first clock signal CLKk through the on-state fourth switching element T4.

[0068] It should be noted that in some embodiments, the parasitic capacitance between the control terminal and the second path terminal of the fourth switching element T4 is directly used as capacitor C. In some other embodiments, to improve the pull-up effect, an independent storage capacitor can be provided between the control terminal and the second path terminal of the fourth switching element T4. This independent storage capacitor and the parasitic capacitance of the fourth switching element T4 are connected in parallel to form capacitor C. Furthermore, it should be understood that the size of the first switching element T1 should be larger than that of the tenth switching element T10 and the sixteenth switching element T16 to provide greater current capability, so that the voltage of the first node Sn can be smoothly pulled up.

[0069] Pull-down phase: In this application, the subsequent stage transmission signal Zn+2 is used as the pull-down signal. When the level of the first clock signal CLKk changes from high to low, since both the fourth switch element T4 and the fifth switch element T5 are turned on during the pull-up phase, the current stage gate drive signal Gn and the current stage transmission signal Zn output by the current stage gate drive unit are quickly pulled low through the fourth switch element T4 and the fifth switch element T5, respectively. In addition, since the subsequent stage transmission signal Zn+2 output by the gate drive unit two stages behind changes from low to high, the third switch element T3 is turned on. Therefore, when the second clock signal CLKk+1 changes from high to low, the voltage of the second node Q is pulled low by the second clock signal CLKk+1 through the turned-on third switch element T3.

[0070] Stabilization Phase: During the pull-down phase, the gate drive signal Gn and the transmission signal Zn output by the nth stage gate drive unit are pulled low by the first clock signal CLK k through the fourth switch element T4 and the fifth switch element T5, respectively, while the voltage at point Q is pulled low by the second clock signal CLK k+1 through the third switch element T3. Therefore, in the subsequent time, it is necessary to keep at least the second node Q, the gate drive signal Gn, and the transmission signal Zn at a low level to obtain the ideal waveform.

[0071] However, since the first clock signal CLKk continues to generate pulses in the subsequent time, it affects the voltage of the first node Sn and the current stage transmission signal Zn. Furthermore, even during the low level period of the first clock signal CLKk, the first node Sn is parasiticly coupled and generates noise due to the parasitic capacitance between the first switching element T1 and the control terminal. Similarly, due to the parasitic capacitance between the fourth switching element T4 and the first node Sn and the control terminal, the second node Q is also parasiticly coupled and generates noise, affecting the current stage gate drive signal Gn. To eliminate these effects and obtain the ideal output waveforms of the current stage gate drive signal Gn and the current stage transmission signal Zn, this embodiment utilizes a stabilization module 315 (including an alternately operating first stabilization module 3151 and a second stabilization module 3152) for improvement.

[0072] Specifically, in the subsequent time interval, when the first timing signal V1 is high, the eighth switching element T8, the ninth switching element T9, and the tenth switching element T10 are turned on. The voltage of the third node QB1 is pulled high by the first timing signal V1 through the turned-on eighth switching element T8, and the voltages of the first node Sn and the fourth node QB2 are pulled low by the first reference signal VSQ through the turned-on ninth switching element T9. Based on the voltages of the third node QB1 and the fourth node QB2, the eleventh to thirteenth switching elements T11 are turned on, and the seventeenth to nineteenth switching elements T17 are turned off. As a result, the Q-point voltage, the gate drive signal of this stage, and the transmission signal Zn of this stage are pulled low by the second reference signal VGL through the turned-on eleventh, twelfth, and thirteenth switching elements, respectively. It should be noted that since the current capability of the first switching element T1 is stronger than that of the tenth switching element T10 and the sixteenth switching element T16, the voltage of the first node Sn will still be pulled high in the subsequent time following the first clock signal CLK k. However, since the voltage of the second node Q is stabilized at a low level at this time and the fourth switching element T4 is turned off, it will not affect the gate drive signal Gn of this stage.

[0073] Furthermore, since the phases of the first timing signal V1 and the second timing signal V2 are always opposite, the voltages of the third node QB1 and the fourth node QB2 can alternately be at a high level. In other words, the eighth to thirteenth switching elements and the fourteenth to nineteenth switching elements work alternately. This ensures the stability of the gate drive circuit while reducing the impact of threshold drift and ensuring the reliability of the gate drive circuit.

[0074] Therefore, although the Sn point voltage, Q point voltage, and the gate output signal Gn and the transmission signal Zn of this stage will change or fluctuate due to the influence of the first clock signal CLK k, the Q point voltage, the gate drive signal Gn of this stage gate drive unit and the transmission signal Zn can be kept at a low level due to the action of the eighth switch element T8 to the nineteenth switch element T19, and the Sn point voltage can be kept at a low level during the low level phase of the first clock signal CLK k.

[0075] Figure 6 This shows a schematic timing diagram of the nth stage gate drive unit during the period when the selection signal is not at a preset level. (Combined with...) Figure 4 and Figure 6During the period when the selection signal is not at a preset level, the operation of the nth stage gate drive unit is basically similar to that during the period when the selection signal is at an active level. The difference is that, since the selection signal is not at a preset level, the first switching element T1 is turned off. Therefore, the voltage at the first node Sn is never affected by the first clock signal CLK k. That is to say, even during the pull-up phase, since the first switching element T1 is turned off, the voltage at Sn is still stabilized to a low level by the first stabilization module 3151 or the second stabilization module 3152. This allows the gate transmission signal Zn of this stage to output a high level as the level of the first clock signal CLK k changes, but the gate drive signal Gn of this stage remains low.

[0076] According to the gate driving circuit provided in this application, during the operation of the display device, when the selection signal is in a preset level state, each gate driving unit follows the first clock signal to output a gate driving signal in an effective level state to its corresponding pixel row; otherwise, each gate driving unit always outputs a gate driving signal in an invalid level state, thereby controlling the gate driving signal output by each gate driving unit to individually turn on at least some of the pixel rows corresponding to the gate driving units, thereby reducing power consumption.

[0077] Furthermore, to enable corresponding pixel rows for changes in the displayed image based on the display status, in some embodiments, selection signals with corresponding level states are output to each corresponding gate driving unit according to the changes in display data between two consecutive frames for each pixel row; that is, the selection signals received by each gate driving unit are at least partially independent of each other. However, in this application, to reduce the number of signal lines and the area occupied by the gate driving circuit, the same selection signal is output to each gate driving unit according to the changes in the displayed image between two consecutive frames (i.e., the selection signal received by each gate driving unit is the same). This selection signal includes multiple data segments corresponding to each pixel row, and each gate driving unit receives the selection signal for the corresponding data segment.

[0078] For example, Figure 7 Show peace Figure 8 The diagram shows simulated waveforms of multiple signals of the nth gate drive unit when the selection signal is at an active level and when it is not.

[0079] exist Figure 7 In this example, we take the second-stage gate drive unit as an example. Figure 7 As shown, for the second-stage gate drive unit, since there is no gate drive unit two stages ahead and therefore no corresponding preceding stage transmission signal, the preceding stage transmission signal for this gate drive unit is provided by a pulse signal (stv2 in the diagram). It should be understood that the pulse width of the pulse signal Stv2 is only for example.

[0080] Furthermore, such as Figure 7 As shown, according to the timing of the selection signal Syn, the selection signal of the second-stage gate drive unit is at a preset level. Therefore, during the pull-up phase, the gate drive signal output by the second-stage gate drive unit (shown in figure xg2-1.gn) is at a high level.

[0081] exist Figure 8 In this example, we take the fourth-stage gate drive unit as an example. Figure 8 As shown, according to the timing of the selection signal Syn, the selection signal of the fourth-stage gate drive unit is at an invalid level. Therefore, during the pull-up phase, the gate drive signal output by the fourth-stage gate drive unit (shown in xg4-1.gn) is always at a low level.

[0082] Figure 9 The following diagram shows waveforms of the gate drive signals of multiple gate drive units in embodiments of this application, such as... Figure 9 As shown, each gate drive unit selects the data segment corresponding to the gate drive unit by determining the timing of the selection signal, and outputs the required gate drive signal level according to the level state of the selection signal, without affecting the level state of the transmitted signal, thus achieving high reliability and stability.

[0083] According to the gate driving circuit of this application embodiment, for each gate driving unit, when the selection signal indicates that the display data corresponding to the pixel row is consistent in the current frame and the previous frame, the gate driving signal of this stage is in an invalid level state, and the transmission signal of this stage is in an active level state. Therefore, the corresponding pixel row can be activated according to the change in the display image of two adjacent frames, thereby reducing power consumption.

[0084] This application also provides a display device. Figure 10 This application provides a schematic structural block diagram of a display device according to an embodiment; as shown. Figure 10 As shown, the display device 1 according to an embodiment of this application includes a timing control circuit 100, a data driving circuit 200, a display panel 400, a selection signal generation circuit 500, and a gate driving circuit 300 provided in this application.

[0085] In this embodiment, the selection signal generation circuit 500 provides a selection signal to the gate driving circuit 300. In some embodiments, the selection signal generation circuit provides selection signals to each gate driving unit of the gate driving circuit 300 according to display requirements. In this embodiment, the selection signal generation circuit 500 provides selection signals related to the changes in display data between two consecutive frames of the display panel.

[0086] Specifically, the timing control circuit 100 is connected to the data driving circuit 200, the gate driving circuit 300, and the selection signal generation circuit 500, respectively. Based on, for example, externally provided image data IMG and control signals Cont (including, for example, vertical synchronization signals, horizontal synchronization signals, and data enable signals), the timing control circuit 100 sends a first control signal Cont1 to the gate driving circuit 300, a second control signal Cont2 to the data driving circuit 200, and a data signal Data to the control signal generation circuit 500. The selection signal generation circuit 500 generates a selection signal Syn based on the data signal Data. The gate driving circuit 300 outputs a scan voltage VG based on the first control signal Cont1 and the selection signal Syn (i.e., according to the first control signal Cont1, the effective level of the scan signal VG is output during the period when the selection signal Syn is at a preset level). The data driving circuit 200 outputs a data voltage VD based on the second control signal Cont2, the selection signal Syn, and the data signal (i.e., according to the second control signal Cont2, the corresponding data voltage VD is output during the period when the selection signal Syn is at a preset level). The display panel 400 includes a plurality of pixel units 410 arranged in an array. Each pixel unit is connected to the data driving circuit 200 or the gate driving circuit 300 through corresponding data lines DL and scan lines GL, and displays according to the data voltage VD when the scan voltage VG is valid.

[0087] Furthermore, Figure 11 Show Figure 10 The diagram shows a schematic structural block diagram of the selection signal generation circuit. As shown, the selection signal generation circuit 500 includes a storage module 510 and a comparison module 520. The storage module 510 receives and stores the data signal Data, and when the selection signal generation unit 500 receives the data signal of the current frame of the display screen (Data p+1 in the diagram, where p is an integer), it outputs the data signal of the previous frame of the display screen (Data p in the diagram, where p is an integer). The comparison module 520 compares the data signals Data p and Data p+1 of the two frames and outputs the selection signal Syn according to the comparison result. Specifically, when Data p and Data p+1 are different, the selection signal Syn is at a preset level (e.g., high level); when Data p and Data p+1 are the same, the selection signal Syn is not at a preset level (e.g., low level).

[0088] In some embodiments, the selection signal generation circuit 500 outputs a corresponding selection signal to each gate driving unit in the gate driving circuit 300, that is, the selection signals received by each gate driving unit are at least partially different.

[0089] In this embodiment, the comparison module 520 compares the data signals corresponding to each pixel row in the two consecutive display frames line by line, and outputs the same selection signal to each gate driving unit according to the comparison result. The selection signal includes multiple data segments corresponding to each pixel row, and each gate driving unit adjusts the control voltage according to the corresponding data segment in the selection signal.

[0090] Since the display device of this application uses the gate driving circuit described above, it also has the aforementioned beneficial effects, which will not be repeated here.

[0091] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A gate driving circuit, comprising a plurality of cascaded gate driving units, wherein, Each of the gate driving units includes: The selection module receives the selection signal and provides the control voltage; and A driving circuit, connected to the selection module, provides independent local transmission signals and gate drive signals based on multiple input signals and the control voltage. The multiple input signals include pre-stage transmission signals and / or post-stage transmission signals. The gate drive signal for this stage is output to the corresponding pixel row, which is selected when the gate drive signal for this stage is at an active level. When the selection signal indicates that the display data of the pixel row is consistent in the current frame and the previous frame, the selection module adjusts the control voltage according to the selection signal to make the gate drive signal of this stage in an invalid state and the transmission signal of this stage in an valid state. The stabilization module of the driving circuit is further configured to clamp the control voltage when the selection signal indicates that the display data of the pixel row is consistent in the current frame and the previous frame.

2. The gate driving circuit according to claim 1, wherein, Each of the gate driving units receives the selection signal corresponding to that gate driving unit; or The selection signal includes multiple data segments corresponding to each of the pixel rows, and each gate driving unit adjusts the control voltage according to the corresponding data segment in the selection signal.

3. The gate driving circuit according to claim 1, wherein, The plurality of input signals also include a first clock signal. The selection module includes a first switching element. The control terminal of the first switching element receives the selection signal, the first path terminal receives the first clock signal, and the second path terminal is a first node that outputs the control voltage.

4. The gate driving circuit according to claim 3, wherein, The plurality of input signals further includes a second clock signal, and the driving circuit includes: The input module adjusts the second node voltage based on the pre-stage transmitted signal or the post-stage transmitted signal and the second clock signal; and An output module is connected to the input module at the second node. The output module includes a first output module and a second output module. The first output module is connected to the first node, the second node, and the gate drive signal output terminal to output the gate drive signal of this stage according to the control voltage and the voltage of the second node. The second output module is connected to the second node and the transmission signal output terminal to output the transmission signal of this stage according to the voltage of the second node and the first clock signal.

5. The gate driving circuit according to claim 4, wherein, The first clock signal and the second clock signal have the same period and duty cycle, and when the first clock signal is at its falling edge, the second clock signal is at its rising edge. The input module includes a second switching element and a third switching element: the control terminal of the second switching element is shorted to the first path terminal to receive the signal transmitted by the preceding stage, and the second path terminal is the second node; the control terminal of the third switching element receives the signal transmitted by the following stage, the first path terminal is connected to the second node, and the second path terminal receives the second clock signal. The first output module includes a fourth switching element and a capacitor. The control terminal of the fourth switching element is connected to the second node, the first path terminal is connected to the first node, and the second path terminal is connected to the gate drive signal output terminal. The first terminal of the capacitor is connected to the control terminal of the fourth switching element, and the second terminal is connected to the second path terminal of the fourth switching element. The second output module includes a fifth switching element, the control terminal of which is connected to the second node, the first path terminal receives the first clock signal, and the second path terminal is connected to the signal transmission output terminal.

6. The gate driving circuit according to claim 4, wherein, The plurality of input signals further includes a first timing signal, a second timing signal, a first reference signal, and a second reference signal, and the gate driving circuit further includes: The pull-down module, connected to the second node, adjusts the voltages of the third and fourth nodes based on the voltage of the second node; and The stabilization module includes a first stabilization module and a second stabilization module connected to the third node and the fourth node. The first stabilization module is also connected to the pull-down module at the third node, and the second stabilization module is also connected to the pull-down module at the fourth node. The first stabilization module or the second stabilization module stabilizes the gate drive signal and the local transmission signal based on the third node voltage, the fourth node voltage, a first timing signal, a second timing signal, a first reference signal, and a second reference signal.

7. The gate driving circuit according to claim 6, wherein, The first timing signal and the second timing signal have the same period and duty cycle, and their phases are always opposite; both the first reference signal and the second reference signal are low-level reference signals. The pull-down module includes a sixth switch element and a seventh switch element; the first stabilization module includes an eighth to a thirteenth switch element; the second stabilization module includes a fourteenth to a nineteenth switch element; The control terminal of the sixth switching element is connected to the second node, the first path terminal receives the first reference signal, and the second path terminal is the third node; the control terminal of the seventh switching element is connected to the second node, the first path terminal receives the first reference signal, and the second path terminal is the fourth node; The control terminal and the first path terminal of the eighth switching element are shorted to receive the first timing signal, and the second path terminal is connected to the third node; the control terminal of the ninth switching element receives the first timing signal, the first path terminal receives the first reference signal, and the second path terminal is connected to the fourth node; the control terminal of the tenth switching element receives the first timing signal, the first path terminal is connected to the first node, and the second path terminal receives the first reference signal. The control terminal of the eleventh switching element is connected to the third node, the first path terminal is connected to the second node, and the second path terminal receives the second reference signal. The control terminal of the twelfth switching element is connected to the third node, the first path terminal is connected to the gate drive signal output terminal, and the second path terminal receives the second reference signal. The control terminal of the thirteenth switching element is connected to the third node, the first path terminal is connected to the signal transmission output terminal, and the second path terminal receives the second reference signal. The control terminal and the second path terminal of the fourteenth switching element are shorted to receive the second timing signal, and the first path terminal is connected to the fourth node; the control terminal of the fifteenth switching element receives the second timing signal, the first path terminal is connected to the third node, and the second path terminal receives the first reference signal. The control terminal of the sixteenth switching element receives the second timing signal, the first path terminal receives the first reference signal, and the second path terminal is connected to the first node; the control terminal of the seventeenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the second node; the control terminal of the eighteenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the gate drive signal output terminal; the control terminal of the nineteenth switching element is connected to the fourth node, the first path terminal receives the second reference signal, and the second path terminal is connected to the transmission signal output terminal. The size of the first switching element is at least larger than the size of the tenth switching element and the sixteenth switching element.

8. A display device, comprising: The gate drive circuit as described in any one of claims 1 to 7; as well as A selection signal generation circuit connected to the gate drive circuit provides the selection signal to each of the gate drive units of the gate drive circuit.

9. The display device according to claim 8, wherein, The display device further includes: The display panel includes multiple pixels arranged in an array; and A data driving circuit, connected to the selection signal generation circuit and the corresponding pixel, provides a corresponding data voltage to each pixel in the pixel row when the selection signal indicates that the display data of the pixel row is inconsistent in the current frame and the previous frame.

10. The display device according to claim 8, wherein, The selection signal generation circuit includes: A storage module is used to store display data and, when the selection signal generation circuit receives the display data corresponding to the current frame, output the display data corresponding to the previous frame; and The comparison module connected to the storage module compares the display data corresponding to the current frame and the previous frame line by line, and outputs the selection signal with the corresponding level state.

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