Display panel and driving method thereof

Abstract

The application discloses a display panel and a driving method thereof. The display panel comprises a plurality of pixel circuits arranged in an array mode, and a first scan line and a second scan line connected with the pixel circuits. The pixel circuit comprises a driving module, a biasing module, a first initialization module and a light-emitting module. The biasing module is used for turning on in response to a first scan signal in a voltage biasing stage, so as to transmit a biasing voltage to a first end or a second end of the driving module. The first initialization module is used for turning on in response to a second scan signal in a first initialization stage, so as to transmit a first initialization voltage to a first end of the light-emitting module. The frequency of the second scan signal is adjustable. The scheme can improve the screen splitting phenomenon caused by different initialization degrees of the first poles of the light-emitting modules in different regions.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and its driving method. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the display quality of display panels.

[0003] Currently, existing display panels suffer from uneven brightness, resulting in a "split-screen" visual effect that severely reduces display quality. Summary of the Invention

[0004] This invention provides a display panel and its driving method to improve the split-screen phenomenon during the display process and enhance display quality.

[0005] According to one aspect of the present invention, a display panel is provided, including a plurality of pixel circuits arranged in an array, and a first scan line and a second scan line connected to the pixel circuits. The pixel circuits include: a driving module, a bias module, a first initialization module and a light-emitting module.

[0006] The driving module is connected between the first power line and the first end of the light-emitting module, and the second end of the light-emitting module is connected to the second power line. The driving module is used to drive the light-emitting module to emit light during the display cycle.

[0007] The bias module is connected to the drive module. The bias module is used to turn on the first scan signal transmitted on the first scan line connected to its own control terminal during the voltage bias phase, so as to transmit the bias voltage to the first or second terminal of the drive module.

[0008] The first initialization module is connected to the first end of the light-emitting module. The first initialization module is used to respond to the second scan signal transmitted on the second scan line connected to its own control terminal during the first initialization phase so as to transmit the first initialization voltage to the first end of the light-emitting module.

[0009] The frequency of the second scanning signal is adjustable to eliminate the load changes caused by the first scanning signal.

[0010] Optionally, within a display cycle, the pulse width of the second scan signal is less than or equal to the pulse width of the first scan signal, and the pulse width of the second scan signal corresponds to the total time of the multi-row pixel circuit in the first initialization phase.

[0011] Optionally, within a display cycle, the number of pulses of the second scan signal is greater than or equal to the number of pulses of the first scan signal.

[0012] Optionally, within a display cycle, the first scan signal includes a plurality of first pulse signals, the second scan signal includes a plurality of second pulse signals, the start time of the second pulse signal is after the start time of the first pulse signal, or the start time of the second pulse signal is the same as the start time of the first pulse signal, and the end time of the second pulse signal is before the end time of the first pulse signal, or the end time of the second pulse signal is the same as the end time of the first pulse signal.

[0013] Optionally, the second pulse signal includes multiple sub-pulse signals, wherein the start time of the first sub-pulse signal is after the start time of the first pulse signal, or the start time of the first sub-pulse signal is the same as the start time of the first pulse signal, and the end time of the last sub-pulse signal is before the end time of the first pulse signal, or the end time of the last sub-pulse signal is the same as the end time of the first pulse signal.

[0014] Optionally, the frequency of the second scan signal is greater than the refresh rate of the display panel.

[0015] Optionally, the frequency of the first scan signal is greater than the refresh rate of the display panel.

[0016] Optionally, within a display cycle, the voltage bias phase coincides with the first initialization phase.

[0017] Optionally, the first initialization module includes a first transistor, the gate of the first transistor is connected to the second scan line, the first electrode of the first transistor is connected to the first initialization signal line, and the second electrode of the first transistor is connected to the first end of the light-emitting module. The first transistor is used to transmit the first initialization voltage on the first initialization signal line to the first end of the light-emitting module during the first initialization phase.

[0018] The bias module includes a second transistor, the gate of which is connected to the first scan line, the first terminal of which is connected to the bias voltage signal line, and the second terminal of which is connected to the first or second terminal of the driving module. The second transistor is used to transmit the bias voltage on the bias voltage signal line to the first or second terminal of the driving module during the voltage biasing phase.

[0019] Optionally, the channel type of the second transistor is different from that of the first transistor;

[0020] Optionally, the first transistor is a metal-oxide-semiconductor transistor.

[0021] Optionally, the pixel circuitry also includes:

[0022] The data writing module is connected to the first end of the driver module. The data writing module is used to transmit data voltage to the driver module during the data writing stage.

[0023] The compensation module is connected between the second terminal of the drive module and the control terminal. The compensation module is used to compensate the threshold voltage of the drive module.

[0024] The second initialization module is connected between the second initialization signal line and the second terminal of the drive module. The second initialization module is used to transmit the second initialization voltage on the second initialization signal line to the control terminal of the drive module during the second initialization phase.

[0025] A first light-emitting control module and a second light-emitting control module are connected. The first light-emitting control module is connected between the first power line and the first end of the drive module, and the second light-emitting control module is connected between the second end of the drive module and the first end of the light-emitting module.

[0026] The storage module is connected to the control terminal of the drive module and is used to store the voltage at the control terminal of the drive module.

[0027] Optionally, the driving module includes a third transistor, the data writing module includes a fourth transistor, the compensation module includes a fifth transistor, the second initialization module includes a sixth transistor, the first light-emitting control module includes a seventh transistor, the second light-emitting control module includes an eighth transistor, the light-emitting module includes a light-emitting diode, and the storage module includes a capacitor.

[0028] The gate of the fourth transistor is connected to the third scan line, the first terminal of the fourth transistor is connected to the data line, the second terminal of the fourth transistor is connected to the first terminal of the third transistor, the gate of the fifth transistor is connected to the fourth scan line, the first terminal of the fifth transistor is connected to the second terminal of the third transistor, and the second terminal of the fifth transistor is connected to the gate of the third transistor.

[0029] The gate of the sixth transistor is connected to the fifth scan line, the first terminal of the sixth transistor is connected to the second initialization signal line, and the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor.

[0030] The gates of the seventh transistor and the eighth transistor are both connected to the light-emitting control signal line. The first terminal of the seventh transistor is connected to the first power supply line. The second terminal of the seventh transistor is connected to the first terminal of the third transistor. The first terminal of the eighth transistor is connected to the second terminal of the third transistor. The second terminal of the eighth transistor is connected to the first terminal of the light-emitting diode. The second terminal of the light-emitting diode is connected to the second power supply line.

[0031] The first terminal of the capacitor is connected to the first power supply line, and the second terminal of the capacitor is connected to the gate of the third transistor.

[0032] According to another aspect of the present invention, a driving method for a display panel is provided. The display panel includes a plurality of pixel circuits arranged in an array, and a first scan line and a second scan line connected to the pixel circuits. The pixel circuits include: a driving module, a bias module, a first initialization module, and a light-emitting module. The driving module is connected between a first power line and a first end of the light-emitting module. The second end of the light-emitting module is connected to the second power line. The bias module is connected to the driving module. The first initialization module is connected to the first end of the light-emitting module.

[0033] The driving methods for the display panel include:

[0034] During the voltage bias phase of a display cycle, the bias module in the multi-row pixel circuit is controlled to simultaneously respond to the first scan signal transmitted on the first scan line and transmit the bias voltage to the first or second terminal of the corresponding drive module.

[0035] During the first initialization phase of a display cycle, the first initialization module in the multi-row pixel circuit is controlled to simultaneously respond to the second scan signal transmitted on the second scan line and transmit the first initialization voltage to the first end of the corresponding light-emitting module.

[0036] During the light-emitting phase of a display cycle, the control drive module generates a drive current to drive the light-emitting module to emit light;

[0037] The frequency of the second scan signal is adjustable to eliminate the load changes caused by the first scan signal.

[0038] Optionally, within a display cycle, the pulse width of the second scan signal is less than or equal to the pulse width of the first scan signal.

[0039] Optionally, the frequency of the second scan signal is greater than the frequency of the first scan signal.

[0040] The technical solution provided by this invention uses a second scanning signal to independently control the initialization of the first end of the light-emitting module, and uses a first scanning signal to independently control the initialization of the first or second end of the driving module, with the frequency of the second scanning signal being adjustable. Compared to solutions in related technologies, even if the pulse of the second scanning signal enters a blank phase, by adjusting the frequency of the second scanning signal, the initialization frequency and degree of the voltage at the first end of the light-emitting module are reduced. This reduces the voltage difference at the first end of the light-emitting modules corresponding to different pixel rows in the display panel during different display stages within a display cycle. This results in a smaller difference in brightness between pixels in each row when the pulse of the second scanning signal enters a blank phase and when it does not, which is beneficial for improving the uniformity of display brightness and thus mitigating the screen splitting phenomenon caused by different initialization degrees of the first electrodes of the light-emitting modules in different areas.

[0041] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of the structure of a pixel circuit in related technologies;

[0044] Figure 2 This is a schematic diagram illustrating the display result of a display panel at a certain moment in a related technology.

[0045] Figure 3 for Figure 2 A schematic diagram of the display panel at another moment;

[0046] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0048] Figure 6 A timing diagram of a first scan signal and a second scan signal provided for an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram illustrating the display result of a display panel at a certain moment, as provided in an embodiment of the present invention.

[0050] Figure 8 This is a schematic diagram illustrating the display result of a display panel at another moment, as provided in an embodiment of the present invention.

[0051] Figure 9 This is a schematic diagram illustrating the display result of another display panel provided in an embodiment of the present invention at a certain moment;

[0052] Figure 10 A timing diagram of another first scan signal and a second scan signal provided in an embodiment of the present invention;

[0053] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0054] Figure 12 A schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0055] Figure 13 A schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present invention;

[0056] Figure 14 This is a flowchart of a driving method for a display panel provided in an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0059] As described in the background section, existing display panels suffer from screen splitting, which reduces display quality. The inventors have discovered the following reasons for this problem:

[0060] Display panels use different refresh rates in different operating modes. Currently, low refresh rates are achieved by skipping frames on top of high refresh rates. A display cycle includes a write frame and a hold frame. By inserting a hold frame after the write frame and adjusting the duration of the hold frame, the refresh rate can be changed. Display panels typically include pixel circuits for driving light-emitting devices. In low-frequency displays, the first or second electrode of the driving transistor in the pixel circuit is in a biased state for a long time, causing a shift in the characteristics of the driving transistor. This results in a difference in display brightness between the hold and write frames, causing flickering. To address this issue, related technologies typically apply a voltage bias to the first or second electrode of the driving transistor to improve its threshold characteristics.

[0061] Figure 1 This is a schematic diagram of a pixel circuit in related technologies, for reference. Figure 1 The pixel circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a seventh transistor M7, and an eighth transistor M8, wherein the third transistor M3 is a driving transistor. During the initialization phase, the first transistor M1 turns on in response to the scan signal SP, transmitting the initialization voltage Vref to the first terminal of the light-emitting diode D1 to initialize the anode of D1. Simultaneously, the second transistor M2 turns on in response to the scan signal SP, transmitting the bias voltage Vcom to the first terminal of the third transistor M3 to reset the voltage at the first terminal of M3, thereby changing the bias state of the third transistor M3 and improving its threshold characteristics. This reduces the brightness difference between the hold frame and the write frame, improving the uniformity of the display brightness.

[0062] In practical applications, the scan signal SP simultaneously controls the anode initialization of LED D1 and the voltage bias of the third transistor M3. Furthermore, the scan signal SP is a high-frequency signal comprising multiple pulse signals. When the scan signal SP scans to the blank area between adjacent frames (taking one frame as an example of a display cycle), different display areas of the display panel exhibit brightness differences, resulting in a "split screen" phenomenon. For ease of understanding, a specific example will be used to illustrate this. Figure 2 This is a schematic diagram illustrating the display result of a display panel at a certain moment in related technologies. Figure 3 for Figure 2 The diagram shows the display result of the display panel at another moment. (See reference) Figures 1-3The display area A of the display panel is equipped with multiple rows of pixel circuits. The scan signal SP includes multiple pulses within one display cycle. During the effective level of the scan signal SP, the first transistor M1 and the second transistor M2 are turned on in response to the pulse signal of the scan signal, respectively, to initialize the first electrode of the light-emitting diode D1 and the first electrode of the third transistor M3. Taking the scan signal SP as having 3 pulses as an example, the pulse width is related to the scanning time of the pixel row. Here, the pulse width of the scan signal SP can correspond to multiple rows (e.g., the scanning time of 20 rows of pixel circuits). After the pixel circuits are working stably, in the same stage of one display cycle, the pixel circuits in three areas of display area A initialize the first electrode of the light-emitting diode D1 and the first electrode of the third transistor M3. That is, the 20-row pixel circuits in the first area 11, the 20-row pixel circuits in the second area 12, and the 20-row pixel circuits in the third area 13 respectively respond to the three pulses of the scan signal SP to initialize their respective light-emitting diodes D1. At this time, the load in display area A is the load corresponding to the 60-row pixel circuits.

[0063] like Figure 3 As shown, over time, a pulse of the scan signal SP enters a blank phase. During this phase, the display panel is performing a blank scan, specifically corresponding to Blank region B. Blank region B does not physically exist on the display panel; it only exists in the time dimension. That is, when a pulse of the scan signal SP enters the blank phase, only regions 21 (fourth region) and 22 (fifth region) are being scanned within display area A. At this time, the load within display area A corresponds to the load of 40 rows of pixel circuits. This results in a situation where, at a certain stage within a display cycle, pixel circuits in two regions of the display panel are being initialized, while at other stages, pixel circuits in three regions are being initialized. This leads to differences in the number of rows driven by the scanning circuits corresponding to the pixel rows and the initialization signal lines providing the initialization voltage Vref in different display stages, resulting in variations in the in-plane load. When the scanning signal SP enters the blank phase, the in-plane load is smaller, which makes the initialization of the first electrode of the LED D1 corresponding to the pixel circuit in the fourth region 21 and the fifth region 22 more complete. This results in the voltage difference between the first and second electrodes of the LED D1 in the fourth region 21 and the fifth region 22 being different from the voltage difference of the LED D1 in other regions. This causes the display brightness in the fourth region 21 and the fifth region 22 to differ from the display brightness in other regions. As a result, the display area A is divided into three parts in the fourth region 21 and the fifth region 22, presenting a three-screen effect visually.

[0064] To address the aforementioned problems, embodiments of the present invention provide a display panel. Figure 4This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 4 and Figure 5 The display panel 100 includes a plurality of pixel circuits PX arranged in an array, and a first scan line G1 and a second scan line G2 connected to the pixel circuits PX. The first scan line G1 is used to transmit a first scan signal S1, and the second scan line G2 is used to transmit a second scan signal S2. The first first scan line G1(1) is connected to the pixel circuit PX in the first pixel row, the second first scan line G1(2) is connected to the pixel circuit PX in the second pixel row, the third first scan line G1(3) is connected to the pixel circuit PX in the third pixel row, and so on, until the nth first scan line G1(n) is connected to the pixel circuit PX in the nth pixel row; the first second scan line G2(1) is connected to the pixel circuit PX in the first pixel row, the second second scan line G2(2) is connected to the pixel circuit PX in the second pixel row, the third second scan line G2(3) is connected to the pixel circuit PX in the third pixel row, and so on, until the nth second scan line G2(n) is connected to the pixel circuit PX in the nth pixel row.

[0065] The first scan line G1 and the second scan line G2 both extend along the X direction. The display panel 100 also includes a data line DL extending along the Y direction, which is used to transmit data voltage Vdata to achieve different grayscale display of the display panel 100.

[0066] The pixel circuit includes a driving module 110, a bias module 120, a first initialization module 130, and a light-emitting module 140. The driving module 110 is connected between a first power line L1 and a first terminal of the light-emitting module 140, and the second terminal of the light-emitting module 140 is connected to a second power line L2. The driving module 110 drives the light-emitting module 140 to emit light during the display cycle. The bias module 120 is connected to the driving module 110. During the voltage bias phase, the bias module 120 responds to the first scan signal S1 transmitted on the first scan line G1 connected to its own control terminal and conducts to transmit the bias voltage Vcom to the first terminal D or the second terminal S of the driving module 110. The first initialization module 130 is connected to the first terminal of the light-emitting module 140. During the first initialization phase, the first initialization module 130 responds to the second scan signal S2 transmitted on the second scan line G2 connected to its own control terminal and conducts to transmit the first initialization voltage Vref1 to the first terminal of the light-emitting module 140. The frequency of the second scan signal S2 is adjustable to eliminate load changes caused by the first scan signal.

[0067] Optionally, within a display cycle, the pulse width of the second scan signal S2 is less than or equal to the pulse width of the first scan signal S1, and the pulse width of the second scan signal S2 corresponds to the total time of the multi-row pixel circuit in the first initialization phase.

[0068] Specifically, the first power line L1 is used to transmit the first power supply voltage VDD, and the second power line L2 is used to transmit the second power supply voltage VSS. The first power supply voltage VDD can be greater than the second power supply voltage VSS. When the connection path between the first power line L1 and the second power line L2 is open, the driving module 110 drives the light-emitting module 140 to emit light. The operation of this pixel circuit includes at least a first initialization stage, a voltage bias stage, and an emission stage. In the first initialization stage, the first initialization module 130 is turned on in response to the second scan signal S2, transmitting the first initialization voltage Vref1 to the first terminal of the light-emitting module 140 to initialize the potential of the first terminal of the light-emitting module 140. In the voltage bias stage, the bias module 120 is turned on in response to the first scan signal S1, transmitting the bias voltage Vcom to the first terminal D of the driving module 110 to reset the potential of the first terminal D of the driving module 110, thereby adjusting the threshold characteristics of the driving module 110. In the emission stage, the connection path between the first power line L1 and the second power line L2 is controlled to be open, so that the driving module 110 can drive the light-emitting module 120 to emit light.

[0069] In related technologies, the first initialization module 130 and the bias module 120 share a single scan signal. However, in this embodiment, the first initialization module 130 and the bias module 120 are connected to different scan lines for independent control. Furthermore, the pulse width of the second scan signal S2 is set to be smaller than the pulse width of the first scan signal S1 to reduce the number of rows in the pixel circuit PX corresponding to the pulse width of the second scan signal S2. Figure 6 A timing diagram of a first scan signal and a second scan signal provided in an embodiment of the present invention, with reference to... Figure 6 Within one display cycle, the first scan signal S1 includes multiple first pulse signals, and the second scan signal S2 includes multiple second pulse signals. The start time of the second pulse signal is after the start time of the first pulse signal, or the start time of the second pulse signal is the same as the start time of the first pulse signal, and the end time of the second pulse signal is before the end time of the first pulse signal, or the end time of the second pulse signal is the same as the end time of the first pulse signal. Taking both the first scan signal S1 and the second scan signal S2 as 3-pulse signals as an example, within one display cycle, the pulse width of the second scan signal S2 is W1, the pulse width of the first scan signal S1 is W2, and W1 < W2. That is, the duration of one pulse of the second scan signal S2 corresponds to the total initialization time of the light-emitting module 140 of fewer pixel rows.

[0070] Figure 7 This is a schematic diagram illustrating the display result of a display panel at a certain moment, according to an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the display result of a display panel at another moment, provided by an embodiment of the present invention. Figures 6 to 8 For example, by adjusting the pulse width of the second scan signal S2, the pulse width of the second scan signal S2 corresponds to the scanning time of 5 rows of pixel circuits PX. That is, the first region 11 includes 5 rows of pixel circuits PX, the second region 12 includes 5 rows of pixel circuits PX, and the third region 13 also includes 5 rows of pixel circuits PX. In this way, under normal circumstances, within one display phase of one display cycle, the in-plane load is the load corresponding to 15 rows of pixel circuits. When one pulse of the second scan signal S2 scans to the blank phase, the fourth region 21 and the fifth region 22 in the display area A each include 5 rows of pixel circuits PX, that is, the in-plane load is the load corresponding to 10 rows of pixel circuits. Compared to the load difference between the 60-row and 40-row pixel circuit PX, the load difference between the 15-row and 10-pixel circuit PX is smaller, which can reduce the initialization degree of the first end of the light-emitting module 140. This reduces the voltage difference between the first and second ends of the light-emitting module 140 in different areas of the display panel 100 during different display stages in a display cycle, which helps to alleviate the uneven display caused by the different initialization degree of the light-emitting module 140 in different display areas.

[0071] In this embodiment, the pulse width of the second scan signal S2 can also be equal to the pulse width of the first scan signal S1. Since the second scan signal S2 and the first scan signal S1 are no longer associated, the pulse widths of the first scan signal S1 and the second scan signal S2 can be reduced simultaneously, achieving the same effect, which will not be elaborated further.

[0072] The technical solution provided by this invention uses a second scanning signal to independently control the initialization of the first end of the light-emitting module, and a first scanning signal to independently control the initialization of the first or second end of the driving module. Within a display cycle, the pulse width of the second scanning signal is set to be less than or equal to the pulse width of the first scanning signal. Compared with related technologies, even if the pulse of the second scanning signal enters a blank phase, the initialization degree of the voltage of the first end of the light-emitting module can be reduced by adjusting the frequency of the second scanning signal. This reduces the voltage difference of the first end of the light-emitting module corresponding to different pixel rows in the display panel under different display stages within a display cycle. This results in a smaller difference in the brightness of pixels in each row of the panel when the pulse of the second scanning signal enters a blank phase and when it does not, which is beneficial to improving the uniformity of display brightness and thus improving the screen splitting phenomenon caused by different initialization degrees of the first electrodes of the light-emitting modules in different areas.

[0073] Alternatively, in another embodiment of the present invention, the phenomenon of screen splitting can be improved by further changing the frequency of the second signal S2. Figure 9 This is a schematic diagram illustrating the display result of another display panel at a certain moment, provided in an embodiment of the present invention, in conjunction with... Figure 9 In this embodiment, within one display cycle, the number of pulses of the second scan signal S2 is greater than or equal to the number of pulses of the first scan signal S1. By increasing the number of pulses of the second scan signal S2, it is possible that at any stage or moment within the display cycle, the display area A is initialized by a fixed number of pulse signals controlling the light-emitting modules 140 of the corresponding pixel rows. Thus, within one display cycle, the load on the surface does not change, and the voltage initialization degree of the first terminal of the light-emitting modules 140 corresponding to each pixel row is the same, thereby eliminating the screen splitting phenomenon.

[0074] The technical solution provided in this embodiment increases the frequency of the second scanning signal S2 by increasing the number of pulses of the second scanning signal S2, and performs high-frequency reset on the first end of the light-emitting module 140 to improve the brightness uniformity in the display area A.

[0075] Optionally, Figure 10 A timing diagram of another first scan signal and a second scan signal provided in an embodiment of the present invention is shown below. Figure 9 and Figure 10 The frequency of the second scan signal S2 can be increased by splitting one pulse into two pulses. For example, when the first scan signal S1 and the second scan signal S2 have the same number of pulses and a pulse width of 4H, to increase the frequency of the second scan signal S2, one pulse of the second scan signal S2 can be split into two sub-pulse signals, one with a pulse width of 1H and the other with a pulse width of 2H. The start time of the first sub-pulse signal is the same as the start time of the first pulse signal of the first scan signal S1, and the end time of the second sub-pulse signal is the same as the end time of the first pulse signal.

[0076] Of course, in other embodiments, the start time of the first sub-pulse signal may be after the start time of the first pulse signal of the first scan signal S1, and the end time of the second sub-pulse signal may be before the end time of the first pulse signal, so as to further reduce the pulse width of the second scan signal S2, which is beneficial to better improve the uniformity of display brightness.

[0077] Optionally, a single pulse signal of the second scanning signal S2 can be divided into more sub-pulse signals to flexibly adjust the frequency of the second scanning signal S2 and better meet visual requirements. In this case, the start time of the first sub-pulse signal of the second scanning signal S2 is after the start time of the first pulse signal, or the start time of the first sub-pulse signal is the same as the start time of the first pulse signal, and the end time of the last sub-pulse signal is before the end time of the first pulse signal, or the end time of the last sub-pulse signal is the same as the end time of the first pulse signal.

[0078] Continue to refer to Figure 5 The pixel circuit also includes:

[0079] The data writing module 150 is connected to the first terminal D of the drive module 110. The data writing module 150 is used to transmit the data voltage Vdata to the drive module 110 during the data writing stage, so that the data voltage Vdata is written to the control terminal G of the drive module 110.

[0080] The compensation module 160 is connected between the second terminal S and the control terminal G of the drive module 110. The compensation module 160 is used to compensate the threshold voltage of the drive module 110.

[0081] The storage module 170 is connected to the control terminal G of the drive module 110, and the storage module 170 is used to store the voltage of the control terminal G of the drive module 110.

[0082] The light-emitting control module 180 is connected in series with the driving module 110 between the first power line L1 and the second power line L2.

[0083] Figure 11 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 11 The pixel circuit also includes a second initialization module 190, which is connected between the second initialization signal line and the second terminal D of the driving module 110. The second initialization module 190 is used to transmit the second initialization voltage Vref2 on the second initialization signal line to the control terminal G of the driving module 110 during the second initialization phase.

[0084] Optionally, the light-emitting control module 180 includes a first light-emitting control module 181 and a second light-emitting control module 182. The first light-emitting control module 181 is connected between the first power line L1 and the first terminal S of the drive module 110, and the second light-emitting control module 182 is connected between the second terminal D of the drive module 110 and the first terminal of the light-emitting module 140.

[0085] The first initialization module 130 includes a first transistor M1, the gate of which is connected to a second scan line, the first electrode of which is connected to a first initialization signal line, and the second electrode of which is connected to a first terminal of the light-emitting module 140. The first transistor M1 is used to transmit the first initialization voltage Vref1 on the first initialization signal line to the first terminal of the light-emitting module 140 during the first initialization phase. The bias module 120 includes a second transistor M2, the gate of which is connected to the first scan line, the first electrode of which is connected to a bias voltage signal line, and the second electrode of which is connected to a first terminal S or a second terminal D of the driving module 110. The second transistor M2 is used to transmit the bias voltage Vcom on the bias voltage signal line to the first terminal S or the second terminal D of the driving module 110 during the voltage bias phase.

[0086] The driving module 110 includes a third transistor M3, the data writing module 150 includes a fourth transistor M4, the compensation module 160 includes a fifth transistor M5, the second initialization module 190 includes a sixth transistor M6, the first light-emitting control module 181 includes a seventh transistor M7, the second light-emitting control module 182 includes an eighth transistor M8, the light-emitting module 140 includes a light-emitting diode D1, and the storage module 170 includes a capacitor C. The gate of the fourth transistor M4 is connected to the third scan line, the first terminal of the fourth transistor M4 is connected to the data line, and the second terminal of the fourth transistor M4 is connected to the first terminal of the third transistor M3. The gate of the fifth transistor M5 is connected to the fourth scan line, the first terminal of the fifth transistor M5 is connected to the second terminal of the third transistor M3, and the second terminal of the fifth transistor M5 is connected to the gate of the third transistor M3. The gate of the sixth transistor M6 is connected to the fifth scan line, the first terminal of the sixth transistor M6 is connected to the second initialization signal line, and the second terminal of the sixth transistor M6 is connected to the first terminal of the fifth transistor M5. The gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the light-emitting control signal line. The first terminal of the seventh transistor M7 is connected to the first power supply line L1, the second terminal of the seventh transistor M7 is connected to the first terminal of the third transistor M3, the first terminal of the eighth transistor M8 is connected to the second terminal of the third transistor M3, the second terminal of the eighth transistor M8 is connected to the first terminal of the light-emitting diode D1, and the second terminal of the light-emitting diode D1 is connected to the second power supply line L2. The first terminal of the capacitor C is connected to the first power supply line L1, and the second terminal of the capacitor C is connected to the gate of the third transistor M3. Here, the first terminal of the light-emitting diode D1 can be the anode, and the second terminal can be the cathode. The first transistor M1, the fifth transistor M5, and the sixth transistor M6 can be either N-type or P-type transistors, while the remaining transistors are all P-type transistors. Figure 11Only the case where the first transistor M1, the fifth transistor M5, and the sixth transistor M6 are N-type transistors is shown. For example, the first transistor M1, the fifth transistor M5, and the sixth transistor M6 are all metal-oxide transistors. The advantage of this configuration is that it can reduce the leakage current problem of the third transistor M3 and help maintain the stability of the gate voltage of the third transistor M3.

[0087] Figure 12 This is a driving timing diagram of a pixel circuit provided in an embodiment of the present invention, which can be applied to... Figure 11 The pixel circuit shown. Combined with... Figure 11 and Figure 12 The operation of the pixel circuit provided in this embodiment includes at least a second initialization stage t1, a data writing stage t2, a first initialization stage t3 (which coincides with the voltage bias stage), and a light emission stage t4.

[0088] During the second initialization phase t1, the first scan signal S1 is high, the second scan signal S2 is low, the third scan signal S3 is high, the fourth scan signal S4 is high, the fifth scan signal S5 is high, and the light emission control signal EM is high. Therefore, the fifth transistor M5 and the sixth transistor M6 are turned on. The second initialization voltage Vref2 on the second initialization signal line is transmitted to the gate of the third transistor M3 via the sixth transistor M6 and the fifth transistor M5, initializing the gate voltage of the third transistor M3 and turning it on. The second initialization voltage Vref2 is also transmitted via the sixth transistor M6 to the second terminal D and the first terminal S of the third transistor M3, initializing the second terminal D and the first terminal S of the third transistor M3.

[0089] During the data writing phase t2, the first scan signal S1 is high, the second scan signal S2 is low, the third scan signal S3 is low, the fourth scan signal S4 is high, the fifth scan signal S5 is low, and the light emission control signal EM is high. Therefore, the fourth transistor M4 and the fifth transistor M5 are turned on. The data voltage Vdata is written to the gate of the third transistor M3 via the fourth transistor M4, the third transistor M3, and the fifth transistor M5. The gate voltage of the third transistor M3 is correlated with the data voltage Vdata and the threshold voltage of the third transistor M3, achieving threshold compensation for the third transistor M3. Capacitor C stores the gate voltage of the third transistor M3.

[0090] During the first initialization phase t3, the first scan signal S1 is low, the second scan signal S2 is high, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light emission control signal EM is high. Therefore, the first transistor M1 and the second transistor M2 are turned on. The first initialization voltage Vref1 on the first initialization signal line is transmitted through the first transistor M1 to the first terminal of the light-emitting diode D1, initializing the first terminal of D1. Simultaneously, the reference voltage Vcom on the reference voltage signal line is transmitted through the second transistor M2 to the first terminal of the third transistor M3, resetting the voltage at the first terminal of the third transistor M3. This changes the bias state of the third transistor M3, ensuring that its threshold characteristics remain stable across different gray levels, thereby improving the uniformity of the driving current generated by the third transistor M3.

[0091] During the light-emitting stage t4, the first scan signal S1 is high, the second scan signal S2 is low, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light-emitting control signal EM is low. Therefore, the seventh transistor M7 and the eighth transistor M8 are turned on, the connection path between the first power line L1 and the second power line L2 is completed, and the third transistor M3 generates a driving current to drive the light-emitting diode D1 to emit light.

[0092] It should be understood that, Figure 12 The driving timing shown is the driving timing of a row of pixel circuits. In this embodiment, the pulse width of the second scan signal S2 corresponds to the total time for initializing the first electrode of the light-emitting diode D1 in multiple rows of pixel circuits. By adjusting the pulse width of the second scan signal S2, the load corresponding to the first initialization voltage Vref1 can be made smaller. Even if a certain pulse of the second scan signal S2 happens to scan a blank stage, the initialization degree of the first electrode of the light-emitting diode D1 in the corresponding pixel row can be ensured to be similar due to the small change in in-plane load. This can improve the problem of uneven display brightness caused by the large difference in the initialization degree of the first electrode of the light-emitting diode D1 in different display stages, and help to reduce the screen splitting phenomenon.

[0093] Based on the above technical solutions, optionally, the frequency of the second scanning signal S2 is greater than the refresh frequency of the display panel, and the frequency of the second scanning signal S2 is greater than the frequency of the first scanning signal S1. Figure 13 The driving timing diagram of another pixel circuit provided in this embodiment of the invention can also be applied to... Figure 11 The pixel circuit shown. A display cycle includes a write frame and a hold frame.

[0094] Within the write frame, the second initialization phase t1, the data writing phase t2, the first initialization phase t3 (coinciding with the voltage bias phase), and the light emission phase t4 are... Figure 12 The driving timing shown is the same, so it will not be described again.

[0095] During the hold frame, in phase t5 (equivalent to the first initialization phase t3 of the write frame), the first scan signal S1 is high, the second scan signal S2 is high, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light emission control signal EM is high. Therefore, the first transistor M1 is turned on, and the first initialization voltage Vref1 on the first initialization signal line is transmitted through the first transistor M1 to the first terminal of the light-emitting diode D1, initializing the first terminal of D1.

[0096] During stage t6 (equivalent to the light-emitting stage t4 within the frame), the first scan signal S1 is high, the second scan signal S2 is low, the third scan signal S3 is high, the fourth scan signal S4 is low, the fifth scan signal S5 is low, and the light-emitting control signal EM is low. Therefore, the seventh transistor M7 and the eighth transistor M8 are turned on, the connection path between the first power line L1 and the second power line L2 is completed, and the third transistor M3 generates a driving current to drive the light-emitting diode D1 to emit light.

[0097] The working process of stages t7 and t8 is the same as that of stages t5 and t6.

[0098] In this scheme, by setting the frequency of the second scan signal S2, the first electrode of the light-emitting diode D1 can be initialized in both the write frame and the hold frame, which is beneficial to improving the display effect. Since the frequency of the second scan signal S2 is increased, the number of pulses of the second scan signal S2 increases accordingly. Therefore, in the first initialization phase within a display cycle, the first electrode of the light-emitting diode D1 in more areas is initialized, resulting in a more uniform distribution of the areas where the first electrode of the light-emitting diode D1 is initialized within the display panel. Under normal circumstances, within the same display phase, because the number of rows of pixel circuits initializing the first electrode of the light-emitting diode D1 within the display panel is relatively large, the difference in the number of rows of pixel circuits initializing the first electrode of the light-emitting diode D1 within the display panel is small even when the pulse of the second scan signal S2 scans to a blank phase in another display phase. That is, the difference in the in-plane load of the display panel corresponding to the first initialization signal line is small in different display phases, which can reduce the difference in the degree of initialization of the first electrode of the light-emitting diode D1 in different areas and is beneficial to improving the screen splitting phenomenon. Furthermore, by reducing the pulse width of the second scan signal S2, the number of pixel rows that cause brightness differences can be reduced, that is, the width of the area showing brightness differences can be narrowed, thereby reducing the mura effect perceived by the human eye.

[0099] It should be noted that, in combination Figure 9 When the frequency of the second scanning signal S2 increases, by appropriately adjusting the number of pulses of the second scanning signal S2, the number of pulses of the corresponding second scanning signal S2 in the display area A can be kept constant in any display stage. Therefore, it will not cause different loads in the display area A, which helps to eliminate the screen splitting phenomenon caused by load differences in the display area A in different display stages.

[0100] Optionally, the frequency of the first scan signal S1 can also be greater than the refresh frequency of the display panel, that is, the first or second terminal of the driving module 110 is also biased by voltage within the hold frame, which is beneficial to improving the uneven display phenomenon caused by the different threshold characteristics of the driving module 110 in the hold frame and the write frame, and is beneficial to improving the display effect.

[0101] This invention also provides a method for driving a display panel, which can be used to drive the display panel provided in any embodiment of this invention. Figure 14 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, combined with... Figures 4 to 14 The display panel driving method provided in this embodiment includes:

[0102] S110, During the voltage biasing phase of a display cycle, the biasing module in the multi-row pixel circuit is controlled to simultaneously respond to the first scan signal transmitted on the first scan line and transmit the bias voltage to the first or second terminal of the corresponding driving module.

[0103] S120, in the first initialization phase within a display cycle, the first initialization module in the multi-row pixel circuit is controlled to simultaneously respond to the second scan signal transmitted on the second scan line and transmit the first initialization voltage to the first end of the corresponding light-emitting module.

[0104] The frequency of the second scan signal is adjustable to eliminate load variations caused by the first scan signal. Within one display cycle, the pulse width of the second scan signal is less than or equal to the pulse width of the first scan signal.

[0105] S130, During the light-emitting phase of a display cycle, the control drive module generates a drive current to drive the light-emitting module to emit light.

[0106] Since the display panel driving method provided in this embodiment is used to drive the display panel provided in any of the above embodiments, the display panel driving method provided in this embodiment also has the beneficial effects described in any of the above embodiments, and will not be repeated here.

[0107] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0108] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, It includes multiple pixel circuits arranged in an array, and a first scan line and a second scan line connected to the pixel circuits. The pixel circuits include: a driving module, a bias module, a first initialization module, and a light-emitting module. The driving module is connected between the first power line and the first end of the light-emitting module, and the second end of the light-emitting module is connected to the second power line. The driving module is used to drive the light-emitting module to emit light during the display cycle. The bias module is connected to the drive module. The bias module is used to turn on the first scan signal transmitted on the first scan line connected to its own control terminal during the voltage bias phase, so as to transmit the bias voltage to the first or second terminal of the drive module. The first initialization module is connected to the first end of the light-emitting module. The first initialization module is used to respond to the second scan signal transmitted on the second scan line connected to its own control terminal during the first initialization phase, so as to transmit the first initialization voltage to the first end of the light-emitting module. The frequency of the second scanning signal is adjustable to eliminate the load changes caused by the first scanning signal.

2. The display panel according to claim 1, characterized in that, Within one display cycle, the pulse width of the second scan signal is less than or equal to the pulse width of the first scan signal, and the pulse width of the second scan signal corresponds to the total time of the multiple rows of pixel circuits in the first initialization phase.

3. The display panel according to claim 2, characterized in that, Within one of the display cycles, the number of pulses of the second scan signal is greater than or equal to the number of pulses of the first scan signal.

4. The display panel according to claim 2, characterized in that, Within one of the display cycles, the first scan signal includes a plurality of first pulse signals, the second scan signal includes a plurality of second pulse signals, the start time of the second pulse signal is after the start time of the first pulse signal, or the start time of the second pulse signal is the same as the start time of the first pulse signal, and the end time of the second pulse signal is before the end time of the first pulse signal, or the end time of the second pulse signal is the same as the end time of the first pulse signal.

5. The display panel according to claim 4, characterized in that, The second pulse signal includes multiple sub-pulse signals. The start time of the first sub-pulse signal is after the start time of the first pulse signal, or the start time of the first sub-pulse signal is the same as the start time of the first pulse signal. The end time of the last sub-pulse signal is before the end time of the first pulse signal, or the end time of the last sub-pulse signal is the same as the end time of the first pulse signal.

6. The display panel according to claim 1, characterized in that, The frequency of the second scanning signal is greater than the refresh rate of the display panel.

7. The display panel according to claim 1, characterized in that, The frequency of the first scanning signal is greater than the refresh rate of the display panel.

8. The display panel according to claim 1, characterized in that, Within one of the display cycles, the voltage bias phase coincides with the first initialization phase.

9. The display panel according to claim 1, characterized in that, The first initialization module includes a first transistor, the gate of the first transistor is connected to the second scan line, the first electrode of the first transistor is connected to the first initialization signal line, and the second electrode of the first transistor is connected to the first end of the light-emitting module. The first transistor is used to transmit the first initialization voltage on the first initialization signal line to the first end of the light-emitting module during the first initialization phase. The bias module includes a second transistor, the gate of which is connected to the first scan line, the first terminal of which is connected to the bias voltage signal line, and the second terminal of which is connected to the first or second terminal of the driving module. The second transistor is used to transmit the bias voltage on the bias voltage signal line to the first or second terminal of the driving module during the voltage biasing phase.

10. The display panel according to claim 9, characterized in that, The channel type of the second transistor is different from that of the first transistor.

11. The display panel according to claim 10, characterized in that, The first transistor is a metal-oxide transistor.

12. The display panel according to any one of claims 1-11, characterized in that, The pixel circuit also includes: A data writing module is connected to the first end of the driving module, and the data writing module is used to transmit data voltage to the driving module during the data writing stage; A compensation module is connected between the second end of the drive module and the control end. The compensation module is used to compensate the threshold voltage of the drive module. The second initialization module is connected between the second initialization signal line and the second terminal of the drive module. The second initialization module is used to transmit the second initialization voltage on the second initialization signal line to the control terminal of the drive module during the second initialization phase. A first light-emitting control module and a second light-emitting control module, wherein the first light-emitting control module is connected between the first power line and the first end of the driving module, and the second light-emitting control module is connected between the second end of the driving module and the first end of the light-emitting module; A storage module is connected to the control terminal of the drive module, and the storage module is used to store the voltage of the control terminal of the drive module.

13. The display panel according to claim 12, characterized in that, The driving module includes a third transistor, the data writing module includes a fourth transistor, the compensation module includes a fifth transistor, the second initialization module includes a sixth transistor, the first light-emitting control module includes a seventh transistor, the second light-emitting control module includes an eighth transistor, the light-emitting module includes a light-emitting diode, and the storage module includes a capacitor. The gate of the fourth transistor is connected to the third scan line, the first terminal of the fourth transistor is connected to the data line, the second terminal of the fourth transistor is connected to the first terminal of the third transistor, the gate of the fifth transistor is connected to the fourth scan line, the first terminal of the fifth transistor is connected to the second terminal of the third transistor, and the second terminal of the fifth transistor is connected to the gate of the third transistor. The gate of the sixth transistor is connected to the fifth scan line, the first terminal of the sixth transistor is connected to the second initialization signal line, and the second terminal of the sixth transistor is connected to the first terminal of the fifth transistor. The gates of the seventh transistor and the eighth transistor are both connected to the light-emitting control signal line. The first terminal of the seventh transistor is connected to the first power line, the second terminal of the seventh transistor is connected to the first terminal of the third transistor, the first terminal of the eighth transistor is connected to the second terminal of the third transistor, the second terminal of the eighth transistor is connected to the first terminal of the light-emitting diode, and the second terminal of the light-emitting diode is connected to the second power line. The first terminal of the capacitor is connected to the first power line, and the second terminal of the capacitor is connected to the gate of the third transistor.

14. A driving method for a display panel, characterized in that, The display panel includes a plurality of pixel circuits arranged in an array, and a first scan line and a second scan line connected to the pixel circuits; the pixel circuit includes: a driving module, a bias module, a first initialization module and a light-emitting module, the driving module is connected between a first power line and a first end of the light-emitting module, the second end of the light-emitting module is connected to a second power line, the bias module is connected to the driving module, and the first initialization module is connected to the first end of the light-emitting module; The driving method for the display panel includes: During the voltage bias phase of a display cycle, the bias modules in the pixel circuits of multiple rows are controlled to simultaneously respond to the first scan signal transmitted on the first scan line and transmit the bias voltage to the first or second terminal of the corresponding driving module. During the first initialization phase of a display cycle, the first initialization module in the multiple rows of pixel circuits is controlled to simultaneously respond to the second scan signal transmitted on the second scan line and transmit the first initialization voltage to the first end of the corresponding light-emitting module. During the light-emitting phase of a display cycle, the driving module is controlled to generate a driving current to drive the light-emitting module to emit light; The frequency of the second scanning signal is adjustable to eliminate the load changes caused by the first scanning signal.

15. The driving method for a display panel according to claim 14, characterized in that, The frequency of the second scan signal is greater than the frequency of the first scan signal.

16. The driving method for a display panel according to claim 14, characterized in that, During one of the display cycles, the pulse width of the second scan signal is less than or equal to the pulse width of the first scan signal.

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