Pixel driving circuit and control method thereof, display panel

Abstract

The present disclosure provides a pixel driving circuit and a control method thereof and a display panel, and relates to the technical field of display. The pixel driving circuit comprises a writing unit electrically connected with a data signal end, a second node and a first control end; a driving unit electrically connected with the second node, a third node and a first node; a compensation unit electrically connected with the third node, the first node and the second control end; a storage unit electrically connected with a fourth node and the first node; a control unit electrically connected with a first voltage end, the fourth node and a reset control end, configured to write a signal of the first voltage end into the fourth node under the signal control of the reset control end; and a compensation writing unit electrically connected with the second node, the fourth node and a third control end, configured to write a signal of the second node into the fourth node under the signal control of the third control end. The problem of bright spots appearing when the display panel displays a black picture is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and its control method, and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are increasingly widely used due to their advantages such as high brightness, low power consumption, and high contrast. However, OLED display panels often exhibit bright spots when displaying black images, affecting the display quality. Summary of the Invention

[0003] The embodiments of this disclosure provide a pixel driving circuit and its control method, as well as a display panel, which improves the problem of bright spots appearing when the display panel displays a black screen.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On the one hand, a pixel driving circuit is provided, the pixel driving circuit including:

[0006] The writing unit is electrically connected to the data signal terminal, the second node, and the first control terminal, and is configured to write the signal from the data signal terminal to the second node under the signal control of the first control terminal.

[0007] A drive unit, electrically connected to the second node, the third node, and the first node, is configured to write the signal of the second node into the third node under the signal control of the first node;

[0008] The compensation unit is electrically connected to the third node, the first node, and the second control terminal, and is configured to write the signal of the third node into the first node under the signal control of the second control terminal.

[0009] A storage unit, electrically connected to the fourth node and the first node, is configured to store the voltage between the fourth node and the first node;

[0010] The control unit is electrically connected to the first voltage terminal, the fourth node, and the reset control terminal, and is configured to write the signal from the first voltage terminal to the fourth node under the signal control of the reset control terminal.

[0011] The rewriting unit is electrically connected to the second node, the fourth node, and the third control terminal, and is configured to write the signal of the second node into the fourth node under the signal control of the third control terminal.

[0012] In some embodiments, the control unit includes a ninth transistor, the first terminal of which is electrically connected to the fourth node, the second terminal of which is electrically connected to the first voltage terminal, and the control terminal of which is electrically connected to the reset control terminal.

[0013] In some embodiments, the control unit further includes a first capacitor, one of its plates being electrically connected to the first voltage terminal, and the other plate being electrically connected to the fourth node.

[0014] In some embodiments, the rewrite unit includes an eighth transistor, the first terminal of which is electrically connected to the fourth node, the second terminal of which is electrically connected to the second node, and the control terminal of which is electrically connected to the third control terminal.

[0015] In some embodiments, the storage unit includes a second capacitor, one plate of which is electrically connected to the first node, and the other plate of which is electrically connected to the fourth node.

[0016] In some embodiments, it also includes a first reset unit, a second reset unit, and a light-emitting control unit;

[0017] The first reset unit is electrically connected to the first node, the first reset terminal and the reset control terminal. The first reset unit is configured to write the signal of the first reset terminal to the first node under the signal control of the reset control terminal.

[0018] The second reset unit is electrically connected to the second reset terminal, the anode of the light-emitting device, and the first control terminal. The second reset unit is configured to write the signal of the second reset terminal into the anode of the light-emitting device under the signal control of the first control terminal.

[0019] The light-emitting control unit is electrically connected to the first voltage terminal, the second node, the third node, the anode of the light-emitting device, and the light-emitting control terminal. The light-emitting control unit is configured to conduct between the first voltage terminal and the second node and between the third node and the anode of the light-emitting device under the signal control of the light-emitting control terminal.

[0020] On the other hand, a control method for a pixel driving circuit is provided, for controlling the pixel driving circuit, wherein one working cycle of the pixel driving circuit includes a reset phase, a data writing phase, and a data interpolation phase, and the control method includes:

[0021] During the reset phase, a first reset signal is written to the first node, and a first voltage signal is written to the fourth node;

[0022] During the data writing phase, the fourth node is controlled to maintain the first voltage signal and write data signals and compensation signals to the first node.

[0023] During the data completion phase, the data signal is written to the fourth node.

[0024] In some embodiments, the pixel driving circuit further includes a first reset unit, which is electrically connected to a first reset terminal and the first node. Writing a first reset signal to the first node includes controlling the first reset unit to enable conduction between the first reset terminal and the first node, so that the first reset signal of the first reset terminal is written to the first node.

[0025] The step of writing the first voltage signal to the fourth node includes: controlling the control unit to make the first voltage terminal and the fourth node conduct, so that the first voltage signal of the first voltage terminal is written to the fourth node.

[0026] In some embodiments, writing the data signal to the fourth node includes: controlling the writing unit to enable conduction between the data signal terminal and the second node, and controlling the rewriting unit to enable conduction between the second node and the fourth node, so that the data signal at the data signal terminal is written to the fourth node.

[0027] On the other hand, a display panel is provided, including:

[0028] Substrate;

[0029] Multiple light-emitting devices are disposed on the first side of the substrate;

[0030] The pixel driving circuit is disposed on the first side of the substrate and is electrically connected to at least one of the light-emitting devices. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 An example application scenario diagram of a display panel is shown;

[0033] Figure 2 A simplified structural diagram of a display panel is shown as an example;

[0034] Figure 3The circuit schematic of the pixel driving circuit in the related technology is shown;

[0035] Figure 4 A partial structural block diagram of a pixel driving circuit is shown as an example;

[0036] Figure 5 An exemplary block diagram of a pixel driving circuit is shown.

[0037] Figure 6 An exemplary circuit schematic of a pixel driving circuit is shown;

[0038] Figure 7 A partial signal timing diagram of a pixel driving circuit is shown as an example;

[0039] Figure 8 An exemplary circuit schematic of another pixel driving circuit is shown;

[0040] Figure 9 A partial signal timing diagram of another pixel driving circuit is shown as an example;

[0041] Figure 10 An exemplary block diagram of a control method for a pixel driving circuit is shown. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0043] In the embodiments of this disclosure, the terms "first," "second," "third," and "fourth" are used to distinguish identical or similar items with essentially the same function and effect, solely for the purpose of clearly describing the technical solutions of the embodiments of this disclosure, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0044] In embodiments of this disclosure, "a plurality of" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0045] In the embodiments of this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0046] In the circuits provided in the embodiments of this disclosure, nodes such as the first node, the second node, the third node, the fourth node, and the fifth node do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0047] The control electrode of each transistor is the gate electrode, the first electrode is one of the source and drain electrodes, and the second electrode is the other of the source and drain electrodes. Since the source and drain electrodes of a transistor can be structurally symmetrical, they can be structurally indistinguishable. That is, the first and second electrodes of the transistors in the embodiments of this disclosure can be structurally indistinguishable. For example, in the case of a P-type transistor, the first electrode is the source and the second electrode is the drain; for example, in the case of an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0048] Figure 1 An example application scenario diagram of a display device is shown. For example... Figure 1 As shown, some embodiments of this disclosure provide a display device 100 that can display text or images, whether moving (e.g., video) or stationary (e.g., still images). For example, the display device 100 can be a mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, camera view display (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, architectural structure, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc. Figure 1 The following is an example of a vehicle-mounted central control unit, with the display device 100 serving as an illustration.

[0049] The display device 100 includes a display panel 110, which can be an electroluminescent display panel or a photoluminescent display panel. When the display panel 110 is an electroluminescent display panel, it can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. When the display panel 110 is a photoluminescent display panel, it can be a quantum dot photoluminescent display panel.

[0050] Some embodiments of this disclosure are illustrated using an organic light-emitting diode (OLED) display panel as an example, with the display panel 110 being an organic light-emitting diode (OLED) display panel.

[0051] Figure 2 A schematic diagram of a display panel is shown, such as... Figure 2 As shown, the display panel 110 includes a substrate 111 and multiple sub-pixels P, multiple gate lines GL, and multiple data lines DL disposed on the first side of the substrate 111.

[0052] The substrate 111 can be a rigid substrate or a flexible substrate, and can be selected according to actual needs.

[0053] For example, substrate 111 is a rigid substrate. For instance, the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0054] For example, the substrate 111 can be a flexible substrate. For instance, the flexible substrate can be a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylenenaphthalate twoformic acid glycol ester) substrate, or a PI (Polyimide) substrate, etc.

[0055] The display panel 110 may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located on one, two, or three sides of the display area AA, or the non-display area NA may be arranged around the display area AA. Multiple sub-pixels P, multiple gate lines GL, and multiple data lines DL may be located within the display area AA.

[0056] For example, multiple subpixels P can be arranged in an array. For instance, multiple subpixels P arranged in an array form multiple subpixel rows and multiple subpixel columns. Multiple subpixels P in a subpixel row are arranged along a first direction X, and multiple subpixels P in a subpixel column are arranged along a second direction Y.

[0057] In this configuration, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. For example, the included angle between the first direction X and the second direction Y can be 85°, 88°, 90°, 92°, or 95°, etc.

[0058] The sub-pixel P may include a pixel driving circuit and a light-emitting device electrically connected to the pixel driving circuit. When the display panel 110 is in operation, the light-emitting device can emit light under the drive of the pixel driving circuit.

[0059] For example, a data line DL can be electrically connected to multiple pixel driving circuits in the same sub-pixel column, and a gate line GL can be electrically connected to multiple pixel driving circuits in the same sub-pixel row. In practical applications, multiple pixel driving circuits in the same sub-pixel row can be electrically connected to multiple gate lines GL. The number of gate lines GL electrically connected to multiple pixel driving circuits in the same sub-pixel row can be determined according to the structure of the pixel driving circuit.

[0060] Continue to refer to Figure 2 A scan driving circuit is also provided on one side of the substrate 111. The scan driving circuit includes multiple cascaded shift registers 112. Each shift register 112 has an output terminal, which can be electrically connected to the gate line GL. When the scan driving circuit is working, the output terminals of the multiple cascaded shift registers 112 output scan signals to the pixel driving circuit step by step through the gate line GL.

[0061] For example, the scan driving circuit is located in the non-display area NA. Of course, in actual applications, in order to reduce the bezel size of the display panel 110, at least a portion of the structure of the scan driving circuit can also be located in the display area AA.

[0062] Figure 3 A circuit diagram of a pixel driving circuit in related technologies is shown. For example... Figure 3 As shown, the pixel driving circuit in the related technology includes transistor M4, driving transistor M3, transistor M2, and capacitor C. During the data writing stage t2, the data signal Vdata is sequentially written to node n1 through transistor M4, driving transistor M3, and transistor M2, and stored in capacitor C. During the light emission stage, the data signal written to node n1 controls driving transistor M3, thereby controlling the driving circuit flowing into the OLED light-emitting device, and ultimately controlling the light emission of the OLED.

[0063] However, the path load from transistor M4 to node n1 is relatively large (for example, vias are included in the path from transistor M4 to node n1, and the resistance of the vias is relatively large), resulting in the data signal written to node n1 being smaller than the theoretical value, causing display defects. Especially when the display panel is a large-size display panel such as a foldable product or an in-vehicle product, the display defects are more obvious.

[0064] For example, the threshold voltage of driving transistor M3 is Vth = -2.5V. When the display panel shows a black screen, the data signal Vdata = 7V, and the theoretical value of the signal written to node n1 is Vdata + Vth = 7V - 2.5V = 4.5V. When the signal at node n1 is 4.5V, the driving transistor M3 can be controlled to turn off. However, in the actual process, Vdata has to pass through driving transistor M3 and transistor M2 to reach node n1. During this process, Vdata will be lost on the traces and vias, and the actual voltage value written to node n1 will be less than 4.5V. If there are process fluctuations, the trace design is too narrow, or the via etching is abnormal, etc., this voltage value will be even smaller, resulting in Vgs of driving transistor M3 < Vth, and driving transistor M3 turns on, causing the pixel to emit light. The specific manifestation is that bright spots appear when the screen is black, affecting the display quality of the screen. Such bright spots are named as the bright spots caused by "insufficient writing at point n1". In the statistical data of the bright spots of the actual product, the occupancy rate of such bright spots among all types of bright spots is 25%. [[ID=***]]

[0065] In view of this, the embodiments of the present disclosure provide a pixel driving circuit, which improves the bright spots caused by insufficient writing of the gate voltage of the driving transistor.

[0066] Figure 4 Exemplarily, a partial structural block diagram of a pixel driving circuit is shown. As Figure 4 shown, the pixel driving circuit includes a writing unit 10, a driving unit 20, a compensation unit 30, a storage unit 40, a control unit 50, and a supplementary writing unit 50.

[0067] The writing unit 10 is electrically connected to the data signal terminal Vdata, the second node N2, and the first control terminal G1. The writing unit 10 is configured to write the signal of the data signal terminal Vdata to the second node N2 under the control of the signal of the first control terminal G1.

[0068] The data signal terminal Vdata can be electrically connected to the data line DL to receive the data signal in the data line DL. The first control terminal G1 can be electrically connected to one of the gate lines GL, so that the first control terminal G1 receives the scanning signal output by the shift register 112 through the gate line GL.

[0069] For example, when the signal of the first control terminal G1 is a low-level signal, the data signal terminal Vdata and the second node N2 are turned on through the writing unit 10, so that the data signal of the data signal terminal Vdata is written to the second node N2.

[0070] Figure 6 An exemplary circuit schematic of a pixel driving circuit is shown. For example, as shown... Figure 6 As shown, the write unit 10 includes a fourth transistor T4. The first terminal of the fourth transistor T4 is electrically connected to the second node N2, the second terminal of the fourth transistor T4 is electrically connected to the data signal terminal Vdata, and the control terminal of the fourth transistor T4 is electrically connected to the first control terminal G1. The fourth transistor T4 is a P-type transistor, and when the first control terminal G1 is a low-level signal, the fourth transistor T4 is turned on.

[0071] The driving unit 20 is electrically connected to the second node N2, the third node N3, and the first node N1. The driving unit 20 is configured to write the signal of the second node N2 to the third node N3 under the signal control of the first node N1.

[0072] For example, when the signal of the first node N1 is a low-level signal, the second node N2 and the third node N3 are turned on through the driving unit 20, so that the signal of the second node N2 is written into the third node N3.

[0073] For example, continue to refer to Figure 6 The driving unit 20 includes a driving transistor T3. The first terminal of the driving transistor T3 is electrically connected to the third node N3, the second terminal of the driving transistor T3 is electrically connected to the second node N2, and the control terminal of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is a P-type transistor, and it is turned on when the first node N1 is at a low level.

[0074] The compensation unit 30 is electrically connected to the third node N3, the first node N1, and the second control terminal G2. The compensation unit 30 is configured to write the signal of the third node N3 into the first node N1 under the signal control of the second control terminal G2.

[0075] For example, when the second control terminal G2 is a low-level signal, the third node N3 and the first node N1 are connected through the compensation unit 30 so that the signal of the third node N3 is written into the first node N1.

[0076] For example, continue to refer to Figure 6The compensation unit 30 includes a second transistor T2. The first terminal of the second transistor T2 is electrically connected to the first node N1, the second terminal of the second transistor T2 is electrically connected to the third node N3, and the control terminal of the second transistor T2 is electrically connected to the second control terminal G2. The second transistor T2 is a P-type transistor, and it is turned on when the second control terminal G2 is at a low level.

[0077] Storage unit 40 is electrically connected to the fourth node N4 and the first node N1. Storage unit 40 is configured to store the signal of the first node N1.

[0078] For example, continue to refer to Figure 6 The storage unit 40 includes a second capacitor C2, one of the plates of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the first node N1.

[0079] Control unit 50 is electrically connected to the first voltage terminal VDD, the fourth node N4, and the reset control terminal Reset. Control unit 50 is configured to write the signal of the first voltage terminal VDD to the fourth node N4 under the control of the signal of the reset control terminal Reset.

[0080] The signal at the first voltage terminal VDD is the first voltage signal, which can be a constant voltage signal. For example, the first voltage signal is a constant high-level signal.

[0081] For example, when the reset control terminal Reset is a low-level signal, the first voltage terminal VDD and the fourth node N4 are connected through the control unit 50, so that the first voltage signal of the first voltage terminal VDD is written into the fourth node N4.

[0082] For example, continue to refer to Figure 6 The control unit 50 includes a ninth transistor T9 and a first capacitor C1. The first terminal of the ninth transistor T9 is electrically connected to the fourth node N4, the second terminal of the ninth transistor T9 is electrically connected to the first voltage terminal VDD, and the control terminal of the ninth transistor T9 is electrically connected to the reset control terminal Reset. One plate of the first capacitor C1 is electrically connected to the first voltage terminal VDD, and the other plate of the first capacitor C1 is electrically connected to the fourth node N4. The ninth transistor T9 can be a P-type transistor. When the reset signal is low, the ninth transistor T9 is turned on.

[0083] The rewrite unit 50 is electrically connected to the second node N2, the fourth node N4, and the third control terminal DW. The rewrite unit 50 is configured to write the signal of the second node N2 to the fourth node N4 under the signal control of the third control terminal DW.

[0084] For example, when the third control terminal DW is a low-level signal, the second node N2 and the fourth node N4 are connected through the write-up unit 50 so that the signal of the second node N2 is written into the fourth node N4.

[0085] For example, continue to refer to Figure 6 The supplementary writing unit 50 includes an eighth transistor T8. The first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, the second terminal of the eighth transistor T8 is electrically connected to the second node N2, and the control terminal of the eighth transistor T8 is electrically connected to the third control terminal DW. The eighth transistor T8 can be a P-type transistor, and the eighth transistor T8 is turned on when the third control terminal DW is a low-level signal.

[0086] Figure 5 An exemplary block diagram of a pixel driving circuit is shown. For example... Figure 5 As shown, in practical applications, the pixel driving circuit may also include a first reset unit 70, a second reset unit 80, and a light-emitting control unit 9050.

[0087] The first reset unit 70 is electrically connected to the first node N1, the first reset terminal Vinit1, and the reset control terminal Reset. The first reset unit 70 is configured to write the signal of the first reset terminal Vinit1 to the first node N1 under the signal control of the reset control terminal Reset.

[0088] For example, when the reset control terminal Reset is a low-level signal, the first reset unit 70 is turned on between the first reset terminal Vinit1 and the first node N1, and the first reset signal of the first reset terminal Vinit1 is written to the first node N1 to reset the first node N1.

[0089] For example, continue to refer to Figure 6 The first reset unit 70 includes a first transistor T1. The first terminal of the first transistor T1 is electrically connected to the first node N1, the second terminal of the first transistor T1 is electrically connected to the first reset terminal Vinit1, and the control terminal of the first transistor T1 is electrically connected to the reset control terminal Reset. The first transistor T1 can be a P-type transistor, and the first transistor T1 is turned on when the reset control terminal Reset is a low-level signal.

[0090] The second reset unit 80 is electrically connected to the second reset terminal Vinit2, the anode of the OLED light-emitting device, and the first control terminal G1. The second reset unit 80 is configured to write the signal of the second reset terminal Vinit2 into the anode of the OLED light-emitting device under the signal control of the first control terminal G1.

[0091] For example, when the first control terminal G1 is a low-level signal, the second reset terminal Vinit2 and the anode of the light-emitting device OLED are connected through the second reset unit 80. The second reset signal of the second reset terminal Vinit2 is written into the anode of the light-emitting device OLED to reset the anode of the light-emitting device OLED.

[0092] For example, continue to refer to Figure 6 The second reset unit 80 includes a seventh transistor T7. The first electrode of the seventh transistor T7 is electrically connected to the anode of the light-emitting device OLED, the second electrode of the seventh transistor T7 is electrically connected to the second reset terminal Vinit2, and the control electrode of the seventh transistor T7 is electrically connected to the first control terminal G1. The seventh transistor T7 can be a P-type transistor, and the seventh transistor T7 is turned on when the first control terminal G1 is a low-level signal.

[0093] The light-emitting control unit 90 is electrically connected to the first voltage terminal VDD, the second node N2, the third node N3, the anode of the light-emitting device OLED, and the light-emitting control terminal EM. The light-emitting control unit 90 is configured to conduct between the first voltage terminal VDD and the second node N2, and to conduct between the third node N3 and the anode of the light-emitting device OLED, under the signal control of the light-emitting control terminal EM.

[0094] For example, when the light-emitting control terminal EM is a low-level signal, the first voltage terminal VDD and the second node N2, as well as the third node N3 and the anode of the light-emitting device OLED, are connected through the light-emitting control unit 90.

[0095] For example, continue to refer to Figure 6 The light-emitting control unit 90 includes a fifth transistor T5 and a sixth transistor T6. The first terminal of the fifth transistor T5 is electrically connected to the second node N2, the second terminal of the fifth transistor T5 is electrically connected to the first voltage terminal VDD, and the control terminal of the fifth transistor T5 is electrically connected to the light-emitting control terminal EM. The first terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting device OLED, the second terminal of the sixth transistor T6 is electrically connected to the third node N3, and the control terminal of the sixth transistor T6 is electrically connected to the light-emitting control terminal EM. Both the fifth transistor T5 and the sixth transistor T6 can be P-type transistors. When the light-emitting control terminal EM is at a low level, both the fifth transistor T5 and the sixth transistor T6 are turned on.

[0096] This disclosure also provides a control method for a pixel driving circuit, used to control the aforementioned pixel driving circuit. The operation of the pixel driving circuit may include multiple working cycles, each working cycle being one image frame. Figure 7 An exemplary timing diagram of a pixel driving circuit is shown. For example... Figure 7As shown, a working cycle includes a reset phase t1, a data writing phase t2, a data rewriting phase t3, and a light emission phase t5.

[0097] Figure 10 An exemplary block diagram of a control method for a pixel driving circuit is shown. Figure 10 As shown, the control method of the pixel driving circuit includes the following steps.

[0098] Step S100: During the reset phase, write a first reset signal to the first node and a first voltage signal to the fourth node.

[0099] Writing a first reset signal to the first node N1 can overwrite the signal written to the first node N1 in the previous working cycle, thereby resetting the first node N1.

[0100] In some implementations, when the pixel driving circuit further includes a first reset unit 70, step S100, writing a first reset signal to the first node, includes the following sub-steps.

[0101] Step S110: Control the first reset unit 70 to make the first reset terminal Vinit1 and the first node N1 conduct, so that the first reset signal of the first reset terminal Vinit1 is written into the first node N1.

[0102] For example, such as Figure 6 and Figure 7 As shown, the first reset unit 70 includes a first transistor T1. The first terminal of the first transistor T1 is electrically connected to the first node N1, the second terminal of the first transistor T1 is electrically connected to the first reset terminal Vinit1, and the control terminal of the first transistor T1 is electrically connected to the reset control terminal Reset. When the first transistor T1 is a P-type transistor, a low-level signal is applied to the reset control terminal Reset, and the first transistor T1 is turned on, thereby writing the first reset signal of the first reset terminal Vinit1 into the first node N1.

[0103] Writing the first voltage signal to the fourth node N4 allows the first voltage signal to be stored in the storage unit 40.

[0104] In some implementations, step 100, writing a first voltage signal to the fourth node, includes the following sub-steps.

[0105] Step S120: Control the control unit 50 to make the first voltage terminal VDD and the fourth node N4 conduct, so that the first voltage signal of the first voltage terminal VDD is written into the fourth node N4.

[0106] For example, continue to refer to Figure 6The control unit 50 includes a ninth transistor T9. The first terminal of the ninth transistor T9 is electrically connected to the fourth node N4, the second terminal of the ninth transistor T9 is electrically connected to the first voltage terminal VDD, and the control terminal of the ninth transistor T9 is electrically connected to the reset control terminal Reset. When the ninth transistor T9 is a P-type transistor, the reset control terminal Reset is a low-level signal, and the ninth transistor T9 is turned on, so that the first voltage signal of the first voltage terminal VDD is written to the fourth node N4.

[0107] like Figure 6 and Figure 7 As shown, in actual application, during the reset phase t1, the reset control terminal Reset is a low-level signal, while the light emission control terminal EM, the first control terminal G1, the second control terminal G2, and the third control terminal DW are all high-level signals. The first transistor T1 and the ninth transistor T9 are turned on, and the other transistors are turned off.

[0108] Step S200: During the data writing phase, control the fourth node to maintain the first voltage signal and write the data signal and compensation signal to the first node.

[0109] The compensation signal can be the threshold voltage Vth of the driving transistor T3.

[0110] For example, such as Figure 6 and Figure 7 As shown, during the data writing stage t2, the first control terminal G1 and the second control terminal G2 are low-level signals, while the light-emitting control terminal EM, the reset control terminal Reset, and the third control terminal DW are high-level signals. The fourth transistor T4, the driving transistor T3, and the second transistor T2 are turned on, and the other transistors are turned off. The data signal is written to the first node N1 sequentially through the fourth transistor T4, the driving transistor T3, and the second transistor T2. Let the data signal be Vdata, and the Vgs of the driving transistor T3 be the level V1 of the first node N1 minus the level V2 of the second node N2, i.e., Vgs = V1 - V2. When the first node N1 no longer writes signals, Vgs = Vth. Since Vgs = V1 - V2, V1 = Vgs + V2, or V1 = Vth + Vdata.

[0111] During the data writing phase t2, the voltage level V4 of the fourth node N4 remains at the first voltage signal VDD. Therefore, the voltage across the memory cell 40 is V4-V1 = VDD-Vth-Vdata. For example, the memory cell 40 includes a second capacitor C2, and the voltage across the second capacitor C2 is VDD-Vth-Vdata.

[0112] For example, continue to refer to Figure 6 and Figure 7The control unit 50 may further include a first capacitor C1, one plate of which is electrically connected to the first voltage terminal VDD, and the other plate of which is electrically connected to the fourth node N4. During the data writing phase t2, the reset control terminal Reset is at a high level, the ninth transistor T9 is turned off, and the fourth node N4 maintains the first voltage signal VDD under the action of the first capacitor C1.

[0113] For example, refer to Figure 8 and Figure 9 The control unit 50 includes a ninth transistor T9 but does not include a first capacitor C1. During the data writing phase t2, the reset control terminal Reset is at a low level, the ninth transistor T9 is turned on, and the first voltage signal VDD at the first voltage terminal VDD is written to the fourth node N4 through the ninth transistor T9, so that the fourth node N4 holds the first voltage signal VDD.

[0114] Step S300: During the data completion phase, write data signals to the fourth node.

[0115] When the fourth node N4 writes the data signal Vdata, the voltage level V4 of the fourth node N4 is Vdata. Since the voltage V4-V1 between the two plates of the second capacitor C2 cannot change abruptly, it remains at VDD-Vth-Vdata for a certain period of time. Therefore, the voltage level of the first node N1 is V1 = V4 - (VDD-Vth-Vdata) = Vdata - (VDD-Vth-Vdata) = 2Vdata + Vth - VDD.

[0116] For example, with VDD = 4.6V, Vth = -2.5V, and Vdata = 7V when displaying a black screen, V1 = 2 * 7 - 2.5 - 4.6 = 6.9V. However, in related technologies, the highest voltage level of the first node N1 is Vdata + Vth = 7 - 2.5 = 4.5V. When the first node N1 experiences insufficient write operation, its voltage level will be less than 4.5V.

[0117] Therefore, in this embodiment of the present disclosure, when displaying a black screen, the level V1 of the first node N1 is higher than that of the first node N1 in the related art, which reduces the probability of the driving transistor T3 being turned on, thereby preventing bright spots from appearing when displaying a black screen.

[0118] In some implementations, writing a data signal to the fourth node N4 includes the following sub-steps.

[0119] Step S310: Control the writing unit 10 to make the data signal terminal Vdata and the second node N2 conduct, and control the rewriting unit 50 to make the second node N2 and the fourth node N4 conduct, so that the data signal of the data signal terminal Vdata is written to the fourth node N4.

[0120] For example, continue to refer to Figure 6 and Figure 8 The write unit 10 includes a fourth transistor T4, and the rewrite unit 50 includes an eighth transistor T8. During the data rewrite stage t3, the first control terminal G1 and the third control terminal DW are low-level signals, and the fourth transistor T4 and the eighth transistor T8 are turned on, so that the data signal is written to the fourth node N4 sequentially through the fourth transistor T4 and the eighth transistor T8.

[0121] like Figures 6 to 9 As shown, during the light-emitting stage t5, the light-emitting control terminal EM is a low-level signal, while other signal terminals are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on. When the driving transistor T3 is turned on, a driving current is formed between the first voltage terminal VDD and the second voltage terminal VSS to drive the OLED light-emitting device to emit light. When a black screen is displayed, the driving transistor T3 is turned off.

[0122] In this embodiment of the present disclosure, when the driving transistor T3 is turned on, the driving current is I1.

[0123]

[0124] In related technologies, when the driving transistor T3 is turned on, the driving current is I2.

[0125]

[0126] Therefore, I1 = 4 * I2, meaning that the screen brightness is higher in this embodiment.

[0127] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel driving circuit, wherein one operating cycle of the pixel driving circuit includes a reset phase, a data writing phase, and a data supplementation phase, characterized in that, include: The writing unit is electrically connected to the data signal terminal, the second node, and the first control terminal, and is configured to write the signal from the data signal terminal to the second node under the signal control of the first control terminal. A drive unit, electrically connected to the second node, the third node, and the first node, is configured to write the signal of the second node into the third node under the signal control of the first node; The compensation unit is electrically connected to the third node, the first node, and the second control terminal, and is configured to write the signal of the third node into the first node under the signal control of the second control terminal. A storage unit, electrically connected to the fourth node and the first node, is configured to store the voltage between the fourth node and the first node; The control unit is electrically connected to the first voltage terminal, the fourth node, and the reset control terminal, and is configured to write the signal from the first voltage terminal to the fourth node under the signal control of the reset control terminal. The rewriting unit is electrically connected to the second node, the fourth node, and the third control terminal, and is configured to write the signal of the second node into the fourth node under the signal control of the third control terminal. During the reset phase, a first reset signal is written to the first node, and a first voltage signal is written to the fourth node; During the data writing phase, the fourth node is controlled to maintain the first voltage signal and write data signals and compensation signals to the first node. During the data completion phase, the data signal is written to the fourth node.

2. The pixel driving circuit according to claim 1, characterized in that, The control unit includes a ninth transistor, the first terminal of which is electrically connected to the fourth node, the second terminal of which is electrically connected to the first voltage terminal, and the control terminal of which is electrically connected to the reset control terminal.

3. The pixel driving circuit according to claim 2, characterized in that, The control unit further includes a first capacitor, one of the plates of which is electrically connected to the first voltage terminal, and the other plate of which is electrically connected to the fourth node.

4. The pixel driving circuit according to claim 1, characterized in that, The rewrite unit includes an eighth transistor, the first terminal of which is electrically connected to the fourth node, the second terminal of which is electrically connected to the second node, and the control terminal of which is electrically connected to the third control terminal.

5. The pixel driving circuit according to claim 1, characterized in that, The storage unit includes a second capacitor, one of the plates of which is electrically connected to the first node, and the other plate of which is electrically connected to the fourth node.

6. The pixel driving circuit according to any one of claims 1 to 5, characterized in that, It also includes a first reset unit, a second reset unit, and a light-emitting control unit; The first reset unit is electrically connected to the first node, the first reset terminal and the reset control terminal. The first reset unit is configured to write the signal of the first reset terminal to the first node under the signal control of the reset control terminal. The second reset unit is electrically connected to the second reset terminal, the anode of the light-emitting device, and the first control terminal. The second reset unit is configured to write the signal of the second reset terminal into the anode of the light-emitting device under the signal control of the first control terminal. The light-emitting control unit is electrically connected to the first voltage terminal, the second node, the third node, the anode of the light-emitting device, and the light-emitting control terminal. The light-emitting control unit is configured to conduct between the first voltage terminal and the second node and between the third node and the anode of the light-emitting device under the signal control of the light-emitting control terminal.

7. A control method for a pixel driving circuit, used to control the pixel driving circuit as described in any one of claims 1 to 6, characterized in that, One operating cycle of the pixel driving circuit includes a reset phase, a data writing phase, and a data supplementation phase. The control method includes: During the reset phase, a first reset signal is written to the first node, and a first voltage signal is written to the fourth node; During the data writing phase, the fourth node is controlled to maintain the first voltage signal and write data signals and compensation signals to the first node. During the data completion phase, the data signal is written to the fourth node.

8. The control method for the pixel driving circuit according to claim 7, characterized in that, The pixel driving circuit further includes a first reset unit, which is electrically connected to a first reset terminal and the first node. Writing a first reset signal to the first node includes controlling the first reset unit to make the first reset terminal and the first node conduct, so that the first reset signal of the first reset terminal is written to the first node. The step of writing the first voltage signal to the fourth node includes: controlling the control unit to make the first voltage terminal and the fourth node conduct, so that the first voltage signal of the first voltage terminal is written to the fourth node.

9. The control method for the pixel driving circuit according to claim 7, characterized in that, The step of writing the data signal to the fourth node includes: controlling the writing unit to enable conduction between the data signal terminal and the second node, and controlling the rewriting unit to enable conduction between the second node and the fourth node, so that the data signal at the data signal terminal is written to the fourth node.

10. A display panel, characterized in that, include: Substrate; Multiple light-emitting devices are disposed on the first side of the substrate; The pixel driving circuit according to any one of claims 1 to 6 is disposed on a first side of the substrate and electrically connected to at least one of the light-emitting devices.

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