Pixel circuit, driving method thereof and display device

Abstract

The application discloses a pixel circuit, a driving method thereof and a display device. The pixel circuit comprises a voltage control module, a current control module and a light emitting module. The voltage control module comprises a first driving module, a coupling module, a first voltage writing module and a reset module. The reset module is connected between a first power line and a control end of the current control module, and is used for resetting the voltage of the control end of the current control module. The technical scheme provided by the embodiment of the application can save the number of power lines and signal lines, is beneficial to saving the layout space, and is further beneficial to improving PPI.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a pixel circuit, its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the display effect of display devices.

[0003] Display devices typically include pixel circuits and light-emitting elements. Pixel circuits usually use analog pulse width modulation (PWM) to control the light-emitting elements. However, existing pixel circuits involve a variety of signals and have complex circuit structures, making it impossible to achieve high PPI. Summary of the Invention

[0004] This invention provides a pixel circuit, its driving method, and a display device to simplify the pixel circuit structure and improve PPI.

[0005] According to one aspect of the present invention, a pixel circuit is provided, comprising: a voltage control module, a current control module, and a light-emitting module;

[0006] The voltage control module includes a first driving module, a coupling module, a first voltage writing module, and a reset module. The first voltage writing module transmits a fixed-level voltage to the control terminal of the first driving module. The coupling module couples a first data voltage and a frequency sweep signal to the control terminal of the first driving module. The first driving module is connected between a first power line and the control terminal of the current control module, and controls the voltage at the control terminal of the current control module according to the first data voltage and the frequency sweep signal to control the light emission time of the light-emitting module.

[0007] The current control module and the light-emitting module are connected between the second power line and the third power line, and the reset module is used to reset the control terminal voltage of the current control module.

[0008] Optionally, the voltage transmitted on the first power line is a switching voltage;

[0009] Preferably, the reset module is connected between the first power line and the control terminal of the current control module.

[0010] Optionally, the operation of the pixel circuit includes at least a voltage writing stage, a reset stage, and a voltage normalization stage, wherein the reset stage is after the voltage writing stage and before the voltage normalization stage;

[0011] Preferably, the first power line is configured such that at least during the reset phase, the voltage transmitted transitions from a first power supply voltage to a reset voltage, and after the reset phase ends, it transitions from the reset voltage back to the first power supply voltage.

[0012] Preferably, the reset module is used to transmit the reset voltage to the control terminal of the current control module during the reset phase.

[0013] Optionally, the first end of the first voltage writing module is connected to the first power line, and the second end of the first voltage writing module is connected to the control terminal of the first drive module. The first voltage writing module is used to write the first power supply voltage transmitted on the first power line to the control terminal of the first drive module during the voltage writing stage.

[0014] Optionally, the voltage control module further includes a first compensation module, a first end of which is connected to a first end of the first drive module, and a second end of which is connected to a control end of the first drive module. The first compensation module is used to compensate the threshold voltage of the first drive module during the voltage writing stage.

[0015] The first end of the first voltage writing module is connected to the first initialization signal line, and the second end of the first voltage writing module is connected to the control terminal of the first driving module. The first voltage writing module is used to write the first initialization voltage transmitted on the first initialization signal line to the control terminal of the first driving module.

[0016] Preferably, the first driving module includes a first transistor; and / or the first voltage writing module includes a second transistor; and / or the first compensation module includes a third transistor; and / or the reset module includes a fourth transistor.

[0017] Preferably, the first terminal of the first transistor is connected to the first power supply line, the second terminal of the first transistor is connected to the control terminal of the current control module, the gate of the first transistor is connected to the coupling module, the gate of the second transistor is connected to the first scan signal line, the first terminal of the second transistor is connected to the first initialization signal line, the second terminal of the second transistor is connected to the gate of the first transistor, the gate of the third transistor is connected to the second scan signal line, the first terminal of the third transistor is connected to the second terminal of the first transistor, the second terminal of the third transistor is connected to the gate of the first transistor, the gate of the fourth transistor is connected to the reset signal line, the first terminal of the fourth transistor is connected to the first terminal of the first transistor, and the second terminal of the fourth transistor is connected to the control terminal of the current control module.

[0018] Preferably, the first scan signal line is multiplexed as the first initialization signal line.

[0019] Optionally, the first end of the coupling module is used to input the first data voltage and the frequency sweep signal, and the second end of the coupling module is connected to the control end of the first drive module;

[0020] Preferably, the coupling module includes a first capacitor, a first end of the first capacitor is connected to a first data line, a second end of the first capacitor is connected to the control terminal of the first driving module, and the first data voltage and the sweep frequency signal share the first data line.

[0021] Optionally, the current control module includes a first light-emitting control module and a first storage module. The control terminal of the first light-emitting control module is connected to the first terminal of the first driving module as the control terminal of the current control module. The first storage module is connected to the control terminal of the first light-emitting control module.

[0022] The current control module further includes a second driving module, a second voltage writing module, a second storage module, and a second light-emitting control module. The first end of the first light-emitting control module is connected to the second power supply voltage transmitted on the second power line. The second end of the first light-emitting control module is connected to the first end of the second driving module. The second end of the second driving module is connected to the light-emitting module through the second light-emitting control module.

[0023] The second voltage writing module is used to write the second data voltage transmitted on the second data line to the control terminal of the second driving module during the voltage writing stage. The second storage module is connected to the control terminal of the second driving module.

[0024] Preferably, the current control module further includes an initialization module, which is used to write the second initialization voltage transmitted by the second initialization signal line to the control terminal of the second drive module;

[0025] Preferably, the current control module further includes a second compensation module, which is connected between the control terminal and the second terminal of the second drive module.

[0026] Preferably, the light-emitting module includes a light-emitting diode;

[0027] Preferably, the first light-emitting control module includes a fifth transistor, the second driving module includes a sixth transistor, the second voltage writing module includes a seventh transistor, the initialization module includes an eighth transistor, the second compensation module includes a ninth transistor, the second light-emitting control module includes a tenth transistor, the first storage module includes a second capacitor, and the second storage module includes a third capacitor.

[0028] The gate of the fifth transistor is connected to the first terminal of the first driving module, the first electrode of the fifth transistor is connected to the second power line, the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor, the second electrode of the sixth transistor is connected to the first electrode of the tenth transistor, the second electrode of the tenth transistor is connected to the first electrode of the light-emitting diode, the second electrode of the light-emitting diode is connected to the third power line, and the gate of the tenth transistor is connected to the first light-emitting control signal line.

[0029] The gates of the seventh transistor and the ninth transistor are both connected to the first scan signal line. The first terminal of the seventh transistor is connected to the second data line. The second terminal of the seventh transistor is connected to the first terminal of the sixth transistor. The first terminal of the ninth transistor is connected to the gate of the sixth transistor. The second terminal of the ninth transistor is connected to the second terminal of the sixth transistor. The gate of the eighth transistor is connected to the third scan signal line. The first terminal of the eighth transistor is connected to the second initialization signal line. The second terminal of the eighth transistor is connected to the gate of the sixth transistor.

[0030] The first terminal of the second capacitor and the first terminal of the third capacitor are both connected to the first terminal of the fifth transistor, the second terminal of the second capacitor is connected to the gate of the fifth transistor, and the second terminal of the third capacitor is connected to the gate of the sixth transistor.

[0031] Preferably, the first initialization signal line is multiplexed as the second initialization signal line;

[0032] Preferably, the third scan signal line is multiplexed as the second initialization signal line.

[0033] Optionally, the pixel circuit further includes a third voltage writing module, which is connected between the first power line and the second end of the first driving module, and is used to transmit the voltage transmitted on the first power line to the second end of the first driving module.

[0034] Preferably, the third voltage writing module includes an eleventh transistor and a twelfth transistor. The gate of the eleventh transistor is connected to the second scan signal line, the first electrode of the eleventh transistor is connected to the first power supply line, and the second electrode of the eleventh transistor is connected to the second terminal of the first driving module. The gate of the twelfth transistor is connected to the second light emission control signal line, the first electrode of the twelfth transistor is connected to the first power supply line, and the second electrode of the twelfth transistor is connected to the second terminal of the first driving module.

[0035] Preferably, the reset module is connected between the second end and the first end of the first drive module.

[0036] According to another aspect of the present invention, a driving method for a pixel circuit is provided. The pixel circuit includes a voltage control module, a current control module, and a light-emitting module. The voltage control module includes a first driving module, a coupling module, a first voltage writing module, and a reset module. The coupling module and the first voltage writing module are both connected to the control terminal of the first driving module. The first driving module is connected between a first power line and the control terminal of the current control module. The current control module and the light-emitting module are connected between a second power line and a third power line. The reset module is connected to the control terminal of the current control module.

[0037] The driving method for the pixel circuit includes:

[0038] During the voltage writing phase, the first voltage writing module is controlled to write a fixed level voltage to the control terminal of the first driving module, and the first data voltage is controlled to be written to the coupling module.

[0039] During the reset phase, the reset module is controlled to reset the voltage at the control terminal of the current control module;

[0040] During the voltage normalization stage, a control sweep signal is written to the coupling module so that the coupling module couples the first data voltage to the control terminal of the first drive module.

[0041] During the light-emitting phase, the current control module drives the light-emitting module to emit light, and controls the voltage of the control terminal of the first driving module through the frequency sweep signal and the first data voltage, thereby controlling the voltage of the control terminal of the current control module to control the light-emitting time of the light-emitting module.

[0042] Optionally, the first voltage writing module is connected between the first initialization signal line and the control terminal of the first driving module, and the control terminal of the first voltage writing module is connected to the first scan signal line. The voltage control module further includes a first compensation module, which is connected between the first terminal and the control terminal of the first driving module. The control terminal of the first compensation module is connected to the second scan signal line, and the control terminal of the reset module is connected to the reset signal line. The current control module includes a first light emission control module, a first storage module, a second driving module, a second voltage writing module, a second storage module, an initialization module, a second compensation module, and a second light emission control module. The control terminal of the first light emission control module serves as the control terminal of the current control module and is connected to the first terminal of the first driving module. The first storage module is connected to the control terminal of the first light emission control module. The circuit is as follows: the first light-emitting control module is connected between the second power line and the first end of the second driving module; the control ends of the second voltage writing module and the second compensation module are both connected to the first scan signal line; the second voltage writing module is connected between the second data line and the first end of the second driving module; the second compensation module is connected between the control end and the second end of the second driving module; the initialization module is connected between the second initialization signal line and the control end of the second driving module; the control end of the initialization module is connected to the third scan signal line; the control end of the second light-emitting control module is connected to the first light-emitting control signal line; and the second light-emitting control module is connected between the second end of the second driving module and the light-emitting module. The voltage writing stage includes an initialization stage, a first voltage writing stage, and a second voltage writing stage.

[0043] During the initialization phase, the third scan signal transmitted by the third scan signal line controls the initialization module to be turned on;

[0044] During the second voltage writing stage, the first scan signal transmitted by the first scan signal line controls the second voltage writing module, the second compensation module and the first voltage writing module to be turned on.

[0045] During the first voltage writing stage, the second scan signal transmitted by the second scan signal line controls the first compensation module to turn on, and the first data voltage is written to the first end of the coupling module.

[0046] During the reset phase, the first power supply voltage jumps to the reset voltage, and the reset signal transmitted by the reset signal line controls the reset module to turn on;

[0047] During the light-emitting phase, the first light-emitting control signal transmitted by the first light-emitting control signal line controls the second light-emitting control module to turn on.

[0048] Optionally, the voltage transmitted on the first power line is a switching voltage, and the reset module is connected between the first power line and the control terminal of the current control module.

[0049] During the reset phase, the step of controlling the reset module to reset the voltage at the control terminal of the current control module includes:

[0050] During the reset phase, the voltage transmitted on the first power line is controlled to switch from the first power supply voltage to the reset voltage, and the reset module is controlled to write the reset voltage to the control terminal of the current control module.

[0051] Preferably, during the voltage normalization stage, while writing the frequency sweep signal to the coupling module, the reset voltage is also controlled to jump to the first power supply voltage.

[0052] According to another aspect of the present invention, a display device is provided, including the pixel circuit provided in any embodiment of the present invention.

[0053] The technical solution provided in this embodiment of the invention indirectly writes the first data voltage to the control terminal of the first driving module through a coupling module. This eliminates the need to set the conduction state of the first driving module based on the magnitude of the first data voltage. There is no voltage requirement between the first data voltage and the power supply voltage (e.g., the first power supply voltage) connected to the second terminal of the first driving module; the first power supply voltage can be flexibly set. Therefore, it reduces the pixel voltage range, thereby reducing the bias voltage on the device and improving the reliability of the pixel circuit. Furthermore, this embodiment eliminates the need for a voltage writing control module or unit, resulting in a simple pixel circuit structure, saving layout space, and thus improving PPI.

[0054] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0057] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0060] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0061] Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0062] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0063] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0064] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0065] Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0066] Figure 11 A timing control waveform diagram of a pixel circuit provided in an embodiment of the present invention;

[0067] Figure 12 A timing control waveform diagram of another pixel circuit provided in an embodiment of the present invention;

[0068] Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0069] Figure 14 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention;

[0070] Figure 15 A timing control waveform diagram of another pixel circuit provided in an embodiment of the present invention;

[0071] Figure 16 A flowchart illustrating a pixel circuit driving method provided in an embodiment of the present invention;

[0072] Figure 17 A flowchart of another pixel circuit driving method provided in an embodiment of the present invention;

[0073] Figure 18This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0074] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0075] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or modules is not necessarily limited to those steps or modules explicitly listed, but may include other steps or modules not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0076] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, with reference to... Figure 1 The pixel circuit provided in this embodiment includes a voltage control module 10, a current control module 20, and a light-emitting module 30. The voltage control module 10 includes a first driving module 101, a coupling module 102, a first voltage writing module 103, and a reset module 104. The first voltage writing module 103 is used to transmit a fixed-level voltage to the control terminal of the first driving module 101. The coupling module 102 is used to couple the first data voltage Vdata_t and the sweep frequency signal SWEEP to the control terminal G1 of the first driving module 101. The first driving module 101 is connected between the first power line and the control terminal of the L1 current control module 20, and is used to control the voltage of the control terminal of the current control module 20 according to the first data voltage Vdata_t and the sweep frequency signal SWEEP, so as to control the light-emitting time of the light-emitting module 30.

[0077] The current control module 20 and the light-emitting module 30 are connected between the second power line L2 and the third power line L3. The reset module 104 is used to reset the control terminal voltage of the current control module 20.

[0078] Specifically, the current control module 20 and the light-emitting module 30 are connected between the second power line L2 and the third power line L3. The second power line L2 is used to transmit the second power supply voltage VDDA, and the third power line L3 is used to transmit the third power supply voltage VSS. The current control module 20 generates a driving current when the discharge path between the second power line L2 and the third power line L3 is open, driving the light-emitting module 30 to emit light. The first terminal N1 of the first driving module 101 is connected to the control terminal of the current control module 20, and its second terminal N2 is connected to the voltage transmitted on the first power line L1. The first driving module 101 controls the voltage of its first terminal N1 according to the first data voltage Vdata_t written to the gate G1 and the sweep frequency signal SWEEP, thereby controlling the voltage of the control terminal of the current control module 20. The current control module 20 controls the conduction state of the discharge path between the second power line L2 and the third power line L3 according to the voltage of its control terminal, thereby achieving the purpose of controlling the light-emitting time of the light-emitting module 30.

[0079] Here, the reset module 104 can be connected to a second voltage V2 to reset the potential of the control terminal of the current control module 20. In this embodiment, the second voltage V2 can be provided by a power supply line. For example, the second voltage V2 can be the voltage provided on the first power supply line L1, or it can be a voltage with a fixed level provided by other power supply lines.

[0080] Furthermore, in this embodiment, since the first data voltage Vdata_t is first written to the first terminal of the coupling module 102, and the second terminal of the coupling module 102 is a constant voltage (which can be a fixed voltage written by the first voltage writing module 103 as the first voltage V1, or other voltages that can turn off the first driving module 101), there is a voltage difference between the two terminals of the coupling module 102. When the sweep signal SWEEP performs signal scanning, since the level of the sweep signal SWEEP changes, under the coupling effect of the coupling module 102, the voltage change at its first terminal is coupled to the second terminal (this coupled voltage will not turn on the first driving module 101). Therefore, the voltage at the second terminal of the coupling module 102 is related to the first data voltage Vdata_t. That is, the first data voltage Vdata_t is written to the control terminal G1 of the first driving module 101. Here, since the first data voltage Vdata_t is written to the control terminal G1 of the first driving module 101 through the coupling module 102, there is no requirement for the magnitude of the first power supply voltage VDDW transmitted on the first power line L1 connected to the second terminal N2 of the first driving module 101. Therefore, after the first data voltage Vdata_t is written to the control terminal G1 of the first driving module 101, the first driving module 101 remains in the off state and will not affect the voltage state of the first terminal N1 of the first driving module 101. Consequently, when controlling the conduction state of the first driving module 101, it is not necessary to set the magnitude of the first power supply voltage VDDW according to the first data voltage Vdata_t. In other words, the first power supply voltage VDDW does not need to change according to the change of the first data voltage Vdata_t, which helps to reduce the voltage difference between the pixel voltage (here, the voltage difference refers to the voltage difference between the maximum and minimum values ​​of other voltage signals besides the data voltage in the pixel circuit). As a result, the bias voltage on each device is smaller, which can improve the reliability of the pixel circuit.

[0081] Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 2 Based on the above technical solution, preferably, in this embodiment, the voltage transmitted on the first power line L1 is a switching voltage. For example, in this embodiment, the first power line L1 can be configured such that at least during the reset phase, the voltage transmitted switches from the first power supply voltage VDDW to the reset voltage VREF, and after the reset phase ends, it switches from the reset voltage VREF back to the first power supply voltage VDDW.

[0082] In this embodiment, the voltages transmitted on the first power line L1 and the second power line L2 are different. The second power supply voltage VDDA transmitted on the second power line L2 is a fixed voltage used to provide power to the current control module 20. Here, the reset module 104 can be connected to the first power line L1. During the reset phase, the voltage transmitted on the first power line L1 is the reset voltage VREF, which is the second voltage V2. This reset voltage VREF is transmitted to the control terminal of the current control module 20 through the reset module 104, thereby resetting the voltage at the control terminal of the current control module 20. After the reset phase ends, the voltage transmitted on the first power line L1 jumps to the first power supply voltage VDDW. That is, different voltages are transmitted through the first power line L1 at different stages to achieve different functions of the pixel circuit, reducing the number of signal lines, simplifying the circuit structure, saving layout space, and achieving high PPI. Here, the first power supply voltage VDDW and the reset voltage VREF are two voltages of unequal magnitude.

[0083] The pixel circuit provided in this embodiment of the invention, on the one hand, distinguishes the voltages transmitted on the first power line and the second power line, and sets the voltage transmitted on the first power line as a switching voltage. For example, during the reset phase, the first power line is configured to transmit the reset voltage, and after the reset phase ends, the first power supply voltage is transmitted. This saves the number of power lines, which is beneficial for saving layout space and thus improving PPI. On the other hand, the first data voltage is indirectly written to the control terminal of the first driving module through a coupling module, so that the conduction state of the first driving module does not need to be set according to the magnitude of the first data voltage. There is no voltage requirement between the first data voltage and the power supply voltage (e.g., the first power supply voltage) connected to the second terminal of the first driving module. The first power supply voltage can be flexibly set, thus reducing the pixel voltage span, thereby reducing the bias voltage on the device and improving the reliability of the pixel circuit.

[0084] Figure 3 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 3 Based on the above embodiments, the first end of the first voltage writing module 103 is connected to the first power line L1, and the second end of the first voltage writing module 103 is connected to the control terminal G1 of the first drive module 101. The first voltage writing module 103 is used to write the first power supply voltage VDDW to the control terminal G1 of the first drive module 101 during the first voltage writing stage.

[0085] Specifically, the fixed voltage V1 transmitted by the first voltage writing module 103 to the control terminal G1 of the first driving module 101 can be the first power supply voltage VDDW transmitted on the first power line L1. During the voltage writing stage, the first power supply voltage VDDW is transmitted on the first power line L1, the first voltage writing module 103 is turned on to transmit the first power supply voltage VDDW to the control terminal G1 of the first driving module 101, and the first driving module 101 is in a turned-off state. At the same time, the first data voltage Vdata_t is written to the first terminal of the coupling module 102, and the voltage difference across the coupling module 102 is VDDW - Vdata_t.

[0086] Continue to refer to Figure 3 The coupling module 102 includes a first capacitor C1 and a fourth capacitor C4. The first capacitor C1 is connected between the first data line DATA1 and the control terminal G1 of the first driving module 101, and the fourth capacitor C4 is connected between the sweep frequency signal line and the control terminal G1 of the first driving module 101. During the voltage writing stage, the first power supply voltage VDDW is written to the control terminal G1 of the first driving module 101 through the first voltage writing module 103. At the same time, the first data voltage Vdata_t transmitted on the first data line DATA1 is written to the first terminal of the first capacitor C1, and the voltage across the first capacitor C1 is VDDW - Vdata_t. When entering the voltage normalization stage, the voltage on the first data line DATA1 changes, and under the coupling effect of the first capacitor C1, the first data voltage Vdata_t is written to the control terminal G1 of the first driving module 101. During the light emission stage, the sweep frequency signal SWEEP transmitted on the sweep frequency signal line is coupled through the fourth capacitor C4 to adjust the voltage of the control terminal G1 of the first driving module 101. The first driving module 101 controls the voltage of the control terminal of the current control module 20 according to the voltage of its control terminal G1, so as to control the light emission time.

[0087] As a preferred embodiment provided in this example, in order to further reduce the number of signal lines, the first data voltage Vdata_t and the sweep frequency signal SWEEP can be transmitted using the same signal line. Figure 4 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 4 The coupling module includes a first capacitor C1. The first end of the first capacitor C1 serves as the first terminal of the coupling module 102 and is connected to the first data line DATA1. The second end of the first capacitor C1 serves as the second terminal of the coupling module 102 and is connected to the control terminal G1 of the first drive module 101. The first data voltage Vdata_t and the sweep frequency signal SWEEP share the first data line DATA1. This reduces the number of sweep frequency signal lines and capacitors, which helps to further reduce the footprint of the layout, thereby achieving a high PPI. The specific operation of the coupling module 102 will be described in detail in subsequent embodiments.

[0088] In this embodiment, whether the first data voltage Vdata_t and the sweep frequency signal SWEEP share the same data line or are set separately, there is no need to set a switching element for switching the first data voltage Vdata_t and the sweep frequency signal SWEEP, which helps to simplify the circuit structure and reduce the system cost.

[0089] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 6 Based on the above embodiments, the voltage control module 10 further includes a first compensation module 105. The first end of the first compensation module 105 is connected to the first end N1 of the first drive module 101, and the second end of the first compensation module 105 is connected to the control end G1 of the first drive module 101. The first compensation module 105 is used to compensate the threshold voltage of the first drive module 101 during the voltage writing stage. The first end of the first voltage writing module 103 is connected to the first initialization signal line, and the second end of the first voltage writing module 103 is connected to the control end G1 of the first drive module 101. The first voltage writing module 103 is used to write the first initialization voltage Vinit1 transmitted on the first initialization signal line to the control end G1 of the first drive module 101.

[0090] Among them, relative to Figure 4 , Figure 6 The pixel circuit shown includes a first compensation module 105, which performs threshold compensation on the first driving module 101 to improve the reliability of the current control module 20. Here, the first voltage writing module 103 transmits the first initialization voltage Vinit1 on the first initialization signal line.

[0091] Specifically, the first driving module 101 includes a first transistor M1, the first voltage writing module 103 includes a second transistor M2, the first compensation module 105 includes a third transistor M3, and the reset module 104 includes a fourth transistor M4; the first terminal of the first transistor M1 is connected to the first power supply line L1, the second terminal of the first transistor M1 is connected to the control terminal of the current control module 20, the gate of the first transistor M1 is connected to the coupling module 102, the gate of the second transistor M2 is connected to the first scan signal line S1, the first terminal of the second transistor M2 is connected to the first initialization signal line, the second terminal of the second transistor M2 is connected to the gate of the first transistor M1, the gate of the third transistor M3 is connected to the second scan signal line S2, the first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, the second terminal of the third transistor M3 is connected to the gate of the first transistor M1, the gate of the fourth transistor M4 is connected to the reset signal line Set, the first terminal of the fourth transistor M4 is connected to the first power supply line L1, and the second terminal of the fourth transistor M4 is connected to the control terminal of the current control module 20.

[0092] During the voltage writing phase, the second transistor M2 is turned on in response to the first scan signal S1 (for ease of description, this embodiment uses the same symbol to represent the signal line and its corresponding output signal), transmitting the first initialization voltage Vinit1 to the gate of the first transistor M1 to initialize the gate potential of the first transistor M1 and prevent residual voltage from the previous frame from affecting the light emission of the current frame. At this time, the first transistor M1 is in the on state. Afterwards, the third transistor M3 is turned on in response to the second scan signal S2. The first power supply voltage VDDW transmitted on the first power line L1 charges the gate of the first transistor M1 through the first transistor M1 and the third transistor M3 until the gate potential of the first transistor M1 is VDDW + Vth1, at which point the first transistor M1 is turned off, where Vth1 is the threshold voltage of the first transistor M1. Simultaneously, the first data voltage Vdata_t is written to the first terminal of the first capacitor C1 (taking the coupling module 102 including the first capacitor C1 as an example only), and the voltage difference across the first capacitor C1 is VDDW + Vth1 - Vdata_t.

[0093] After the first data voltage Vdata_t is written, the reset phase begins. The voltage transmitted on the first power line L1 changes from the first power supply voltage VDDW to the reset voltage VREF. The fourth transistor responds to the reset signal Set transmitted on the reset signal line and turns on, transmitting the reset voltage VREF to the control terminal of the current control module 20. This enables the discharge path between the internal circuit of the current control module 20 and the second power line L2 to be connected, allowing the second power supply voltage VDDA to be transmitted to the inside of the current control module 20 in preparation for subsequent light emission.

[0094] Next, the voltage normalization phase begins. The voltage transmitted on the first data line DATA1 changes from the first data voltage Vdata_t to the sweep signal SWEEP and remains at a high level, where the high level of the sweep signal SWEEP is greater than or equal to the maximum value of the first data voltage Vdata_t. The potential at the first terminal of the first capacitor C1 is pulled high. Due to the coupling effect of the first capacitor C1, the gate potential of the first transistor M1 (i.e., the potential at point G1) becomes SWEEP_H + VDDW + Vth1 - Vdata_t, where SWEEP_H is the high level of the sweep signal SWEEP. In other words, the first data voltage Vdata_t is coupled to the gate of the first transistor M1.

[0095] In this embodiment, during normal operation of the pixel circuit, a low voltage of the first data voltage Vdata_t corresponds to a high grayscale. The smaller the first data voltage Vdata_t, the higher the gate potential of the first driving transistor MD1. Given a fixed scanning frequency of the sweep signal SWEEP, the longer the light-emitting time of the light-emitting module 30, the higher the displayed grayscale. Therefore, the first data voltage Vdata_t is written into the gate G1 of the first driving transistor MD1 via coupling, and the first data voltage Vdata_t is pulled high during the voltage normalization stage. Since a low level of the first data voltage Vdata_t corresponds to a high grayscale, the usable voltage range of the first data voltage Vdata_t is large, resulting in a large number of color levels, which is beneficial for grayscale expansion.

[0096] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 7 Based on the above technical solution, optionally, the first scan signal line S1 is multiplexed as the first initialization signal line. That is, the second transistor M2 adopts a diode connection, with its first terminal connected to the first scan signal line, and the first initialization voltage Vinit1 is provided by the first scan signal line S1. This can reduce the number of first initialization signal lines, which is beneficial to further reduce the layout space occupied by the pixel circuit, thereby improving PPI. Figure 7 The working process of the pixel circuit shown can be referred to Figure 6 The relevant descriptions in the document will not be repeated here.

[0097] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 8Based on the above technical solutions, optionally, the current control module 20 includes a first light-emitting control module 201 and a first storage module 202. The control terminal of the first light-emitting control module 201 is connected to the first terminal N1 of the first driving module 101 as the control terminal of the current control module 20. The first storage module 202 is connected to the control terminal of the first light-emitting control module 201. The current control module 20 also includes a second driving module 203, a second voltage writing module 204, a second storage module 205, and a second light-emitting control module 208. The second voltage writing module 204 is connected between the second data line DATA2 and the control terminal G2 of the second driving module 203. The first terminal of the first light-emitting control module 201 is connected to the second power supply voltage VDDA transmitted on the second power line L2. The second terminal of the first light-emitting control module 201 is connected to the first terminal of the second driving module 203. The second terminal of the second driving module 203 is connected to the light-emitting module 30 through the second light-emitting control module 208.

[0098] The second voltage writing module 204 is used to write the second data voltage Vdata_I transmitted on the second data line DATA2 to the control terminal G2 of the second driving module 203 during the voltage writing stage. The second storage module 205 is connected to the control terminal G2 of the second driving module 203 to store the voltage of the control terminal G2 of the second driving module 203. The second light-emitting control module 208 and the first light-emitting control module 201 are used to control the conduction state of the discharge path between the second power line L2 and the light-emitting module 30.

[0099] Figure 9 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 9 Based on the above technical solution, the current control module 20 may optionally include an initialization module 206 and a second compensation module 207. The second compensation module 207 is connected between the control terminal G2 and the second terminal of the second drive module 203. The initialization module 206 is used to write the second initialization voltage Vinit2 transmitted by the second initialization signal line to the control terminal G2 of the second drive module 206.

[0100] Further, refer to Figure 10 The first light-emitting control module 201 includes a fifth transistor M5, the second driving module 203 includes a sixth transistor M6, the second voltage writing module 204 includes a seventh transistor M7, the initialization module 206 includes an eighth transistor M8, the second compensation module 207 includes a ninth transistor M9, the second light-emitting control module 208 includes a tenth transistor M10, the first storage module 202 includes a second capacitor C2, the second storage module 205 includes a third capacitor C3, and the light-emitting module 30 includes a light-emitting diode (LED).

[0101] In this configuration, the gate of the fifth transistor M5 is connected to the first terminal N1 of the first driving module 101, the first electrode of the fifth transistor M5 is connected to the second power line L2, the second electrode of the fifth transistor M5 is connected to the first electrode of the sixth transistor M6, the second electrode of the sixth transistor M6 is connected to the first electrode of the tenth transistor M10, the second electrode of the tenth transistor M10 is connected to the first electrode of the light-emitting diode (LED), the second electrode of the LED is connected to the third power line L3, and the gate of the tenth transistor M10 is connected to the first light-emitting control signal line EM1. The gates of the seventh transistor M7 and the ninth transistor M9 are both connected to the first scan signal line S1, the first electrode of the seventh transistor M7 is connected to the second data line DATA2, the second electrode of the seventh transistor M7 is connected to the first electrode of the sixth transistor M6, the first electrode of the ninth transistor M9 is connected to the gate of the sixth transistor M6, the second electrode of the ninth transistor M9 is connected to the second electrode of the sixth transistor M6, the gate of the eighth transistor M8 is connected to the third scan signal line S3, the first electrode of the eighth transistor M8 is connected to the second initialization signal line, and the second electrode of the eighth transistor M8 is connected to the gate of the sixth transistor M6.

[0102] The first terminals of the second capacitor C2 and the third capacitor C3 are both connected to the first terminal of the fifth transistor M5. The second terminal of the second capacitor C2 is connected to the gate of the fifth transistor M5, and the second terminal of the third capacitor C3 is connected to the gate of the sixth transistor M6.

[0103] Figure 11 A timing control waveform diagram for a pixel circuit provided in this embodiment of the invention is applicable to... Figure 10 The pixel circuit shown. Combined with... Figure 10 and Figure 11 Taking all transistors as P-type transistors as an example, the working process of the pixel circuit provided in this embodiment of the invention includes at least a voltage writing stage T1, a reset stage T2, a voltage normalization stage T3, and a light emission stage T4. The voltage writing stage T1 includes at least an initialization stage t1, a second voltage writing stage t2, and a first voltage writing stage t3.

[0104] During initialization phase t1, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a low-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, and the first light-emitting control signal line is configured to transmit a high-level first light-emitting control signal EM1. Then, the eighth transistor M8 is turned on, and the second initialization voltage Vinit2 transmitted on the second initialization signal line is written to the gate of the sixth transistor M6, thus initializing the gate potential of the sixth transistor M6.

[0105] During the second voltage writing phase t2, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a low-level first scan signal S1, and the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1. Then, the seventh transistor M7, the ninth transistor M9, and the second transistor M2 are turned on. The second data voltage Vdata_I is written to the gate of the sixth transistor M6 through the seventh transistor M7, the sixth transistor M6, and the ninth transistor M9. The gate potential of the sixth transistor M6 is Vdata_I + Vth6, and it is stored in the third capacitor C3, where Vth6 is the threshold voltage of the sixth transistor M6, achieving threshold compensation for the sixth transistor M6. Simultaneously, the first initialization voltage Vinit1 transmitted on the first initialization signal line is written to the gate of the first transistor M1 through the second transistor M2, achieving initialization of the gate potential of the first transistor.

[0106] During the first voltage writing phase t3, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a low-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, and the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1. Then, the third transistor M3 is turned on, and the first power supply voltage VDDW transmitted on the first power supply line L1 charges the gate of the first transistor M1 until the gate potential of the first transistor M1 is VDDW + Vth1. At this point, the first transistor M1 is turned off, and its gate potential stabilizes at VDDW + Vth1, achieving threshold compensation for the first transistor M1, where Vth1 is the threshold voltage of the first transistor M1. Simultaneously, the first data voltage Vdata_t transmitted on the first data line DATA1 is written to the first terminal of the first capacitor C1. At this time, the voltage difference across the first capacitor C1 is VDDW + Vth1 - Vdata_t.

[0107] In stage t4, the remaining sub-pixels undergo initialization stage t1, second voltage writing stage t2, and first voltage writing stage t3 row by row to complete the data writing of all pixel rows.

[0108] During the reset phase T2, the voltage transmitted on the first power supply line L1 changes from the first power supply voltage VDDW to the reset voltage VREF. The reset signal line is configured to transmit a low-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, and the first light emission control signal line is configured to transmit a high-level first light emission control signal EM1. Then, the fourth transistor M4 is turned on, and the reset voltage VREF transmitted on the first power supply line L1 is transmitted to the gate of the fifth transistor M5, controlling the fifth transistor M5 to turn on. This causes the second power supply voltage VDDA transmitted on the second power supply line L2 to be transmitted to the first terminal of the sixth transistor M6.

[0109] During the voltage normalization phase T3, the first data voltage Vdata_t transmitted on the first data line DATA1 transitions to the high level SWEEP-H of the sweep signal SWEEP. In this embodiment, the high level SWEEP-H of the sweep signal SWEEP is greater than or equal to the maximum value of the first data voltage Vdata_t. The voltage at the first terminal of the first capacitor C1 is pulled high to SWEEP-H, and the voltage at the second terminal of the first capacitor C1 becomes VDDW + Vth1 - Vdata_t + SWEEP-H, turning off the first transistor M1. Simultaneously, the reset voltage VREF transmitted on the first power line L1 transitions to the first power supply voltage VDDW. At this time, although the first transistor M1 is off, the fourth transistor M4 remains on because the reset voltage VREF is already stored in the second capacitor C2.

[0110] During the light-emitting stage T4, the reset signal line is configured to transmit a high-level reset signal Set, the third scan signal line is configured to transmit a high-level third scan signal S3, the second scan signal line is configured to transmit a high-level second scan signal S2, the first scan signal line is configured to transmit a high-level first scan signal S1, and the first light-emitting control signal line is configured to transmit a low-level first light-emitting control signal EM1. The tenth transistor M10 is turned on, the discharge path between the second power line L2 and the third power line L3 is opened, and the sixth transistor M6 outputs a drive current based on its gate's second data voltage Vdata_I, driving the light-emitting module 30 to emit light. The drive current can be expressed by the following formula:

[0111]

[0112] Where μ is the electron mobility of the sixth transistor M6, Cox is the channel capacitance per unit area of ​​the sixth transistor M6, W / L is the aspect ratio of the sixth transistor M6, and Vth6 is the threshold voltage of the sixth transistor M6. In this embodiment, the light-emitting module 30 may include one or more of OLED, Micro-LED, and Mini-LED.

[0113] During the light-emitting phase T4, the sweep frequency signal SWEEP gradually changes from a high level (SWEEP-H) to a low level (SWEEP-L). Due to the coupling effect of the first capacitor C1, the gate potential of the first transistor M1 changes synchronously. When the sweep frequency signal SWEEP decreases to the point that the gate potential VG1 of the first transistor M1 satisfies VG1 - VDDW = Vth1, the first transistor M1 turns on. The first power supply voltage VDDW is transmitted to the gate of the fifth transistor M5 through the first transistor M1, controlling the fifth transistor M5 to turn off. Therefore, the first terminal of the fifth transistor M5 is disconnected from the second power supply line L2, the driving current is zero, the light-emitting module 30 is turned off, and the light-emitting time is controlled.

[0114] Optionally, the technical solution provided in this embodiment can also achieve the setting of writing data once and emitting light multiple times within one frame, which helps to reduce the problem of screen flickering under low grayscale. Figure 12 The timing control waveform diagram of another pixel circuit provided in this embodiment of the invention is also applicable to... Figure 10 The pixel circuit shown.

[0115] In this embodiment, the magnitude of the driving current is determined by the magnitude of the second data voltage Vdata_I, and is independent of the threshold voltage Vth6 of the sixth transistor M6, which is beneficial to improving the color uniformity of the light-emitting module 30. The light-emitting time of the light-emitting module 30 is determined by the first data voltage Vdata_t and the sweep frequency signal SWEEP. When the sweep frequency signal SWEEP is high, the light-emitting module 130 is in the bright state. During the sweep frequency signal SWEEP scanning from high to low level, the voltage of the first electrode of the first capacitor C1 gradually decreases. Due to the coupling effect of the capacitor, the gate voltage of the first transistor M1 gradually decreases. When the gate potential VG1 of the first transistor M1 satisfies VG1-VDDW=Vth1, the first transistor M1 is turned on, and the first power supply voltage VDDW is transmitted to the gate of the fifth transistor M5, thereby turning off the fifth transistor M5, and the light-emitting module 30 is in the dark state. Figure 12As shown, within the light-emitting phase of a display frame, the sweep frequency signal SWEEP includes multiple sub-signals, each corresponding to a sub-light-emitting phase. Each sub-signal of the sweep frequency signal SWEEP repeats the above operation process, thereby increasing the slope of the sweep frequency signal SWEEP and improving the switching speed between bright and dark states of the light-emitting module 30. This helps to improve the display problem caused by the slow switching speed of the light-emitting module 30 from bright to dark states at low grayscale levels. Specifically, the sweep frequency signal SWEEP can be a sawtooth wave, triangular wave, or other oblique wave signal.

[0116] Preferably, in this embodiment, the first initialization signal line can be reused as the second initialization signal line. The first voltage writing module 103 and the initialization module 206 are both connected to the first initialization voltage Vinit1, which can save the number of second initialization signal lines and help reduce the layout space occupied by the pixel circuit to improve PPI.

[0117] Figure 13 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 13 Based on the above technical solution, optionally, the third scan signal line S3 is multiplexed as the second initialization signal line, that is, the eighth transistor M8 adopts a diode connection, and its first terminal is connected to the third scan signal line S3. The second initialization voltage Vinit2 is provided by the third scan signal line S3, which can reduce the number of second initialization signal lines, which is beneficial to further reduce the layout space occupied by the pixel circuit, thereby improving PPI. Figure 13 The working process of the pixel circuit shown can be referred to Figure 10 The relevant descriptions in the document will not be repeated here.

[0118] Figure 14 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention, with reference to... Figure 14 Based on the above technical solutions, the pixel circuit may optionally include a third voltage writing module 106, which is connected between the first power line L1 and the second end of the first driving module 101, and is used to transmit the voltage transmitted on the first power line L1 to the second end of the first driving module 101.

[0119] In this design, an open-state capacitance exists between the gate and the second electrode of the first transistor M1. When the second electrode of the first transistor M1 is directly connected to the first power line L1, this open-state capacitance is also directly connected to the first power line L1. After data writing is completed, charge flows through this open-state capacitance, affecting the charging and discharging rate of the gate of the first transistor M1. This results in reduced accuracy in controlling the light emission time and is detrimental to grayscale development. By setting a third voltage writing module 106, this open-state capacitance can be placed in a floating state after data writing, which is equivalent to having no capacitance at the gate of the first transistor M1. This avoids affecting the charging and discharging rate of the first transistor M1 and allows for better control of the light emission time of the light-emitting module 30.

[0120] Specifically, the third voltage writing module 106 includes an eleventh transistor M11 and a twelfth transistor M12. The gate of the eleventh transistor M11 is connected to the second scan signal line S2, the first terminal of the eleventh transistor M11 is connected to the first power supply line L1, and the second terminal of the eleventh transistor M11 is connected to the second terminal N2 of the first driving module 101. The gate of the twelfth transistor M12 is connected to the second light emission control signal line EM2, the first terminal of the twelfth transistor M12 is connected to the first power supply line L1, and the second terminal of the twelfth transistor M12 is connected to the second terminal N2 of the first driving module 101.

[0121] In this embodiment, the first terminal of the fourth transistor M4 can be directly connected to the first power line L1, or it can be connected to the second terminal of the twelfth transistor M12. The connection status of the fourth transistor M4 can be used to select whether the twelfth transistor M12 is turned on during the reset phase T2. Figure 15 A timing control waveform diagram for another pixel circuit provided in an embodiment of the present invention is shown below. Figure 15 Taking the connection of the first terminal of the fourth transistor M4 to the second terminal of the twelfth transistor M12 (i.e., node N2) as an example, during the reset phase T2, when the voltage transmitted on the first power line L1 changes from the first power supply voltage VDDW to the reset voltage VREF, a low-level second light-emitting control signal EM2 is transmitted on the second light-emitting control signal line to control the twelfth transistor M12 to turn on. The reset voltage VREF transmitted on the first power line L1 is transmitted to the gate of the fifth transistor M5 through the twelfth transistor M12 and the fourth transistor M4, controlling the fifth transistor M5 to turn on, thereby allowing the second power supply voltage VDDA transmitted on the second power line L2 to be transmitted to the first terminal of the sixth transistor M6. During the voltage writing phase T1 and the voltage normalization phase T3, since both the eleventh transistor M11 and the twelfth transistor M12 are turned off, there is no open-state capacitance between the gate and the second terminal of the first transistor M1 (i.e., between node G1 and node N2), which will not affect the charging and discharging rate of the first transistor M1 and can ensure the accuracy of the gate voltage of the first transistor M1.

[0122] Optionally, the present invention also provides a driving method for a pixel circuit, capable of driving the pixel circuit provided in any embodiment of the present invention. (In conjunction with...) Figure 1 The pixel circuit includes a voltage control module 10, a current control module 20, and a light-emitting module 30. The voltage control module 20 includes a first driving module 101, a coupling module 102, a first voltage writing module 103, and a reset module 104. The coupling module 102 and the first voltage writing module 103 are both connected to the control terminal G1 of the first driving module 101. The first driving module 101 is connected between the first power line L1 and the control terminal of the current control module 20. The current control module 20 and the light-emitting module 30 are connected between the second power line L2 and the third power line L3. Figure 16 A flowchart of a pixel circuit driving method provided in an embodiment of the present invention is shown below. Figure 16 The driving method for this pixel circuit includes:

[0123] S110. During the voltage writing stage, the first voltage writing module is controlled to write a fixed level voltage to the control terminal of the first driving module, and the first data voltage is controlled to be written to the coupling module.

[0124] S120. During the reset phase, the control reset module resets the voltage at the control terminal of the current control module.

[0125] S130. During the voltage normalization stage, the control sweep signal is written to the coupling module so that the coupling module couples the first data voltage to the control terminal of the first drive module.

[0126] S140. During the light-emitting stage, the control current control module drives the light-emitting module to emit light, and controls the voltage of the control terminal of the first driving module through the sweep frequency signal and the first data voltage, thereby controlling the voltage of the control terminal of the current control module to control the light-emitting time of the light-emitting module.

[0127] The pixel circuit driving method provided in this embodiment indirectly writes the first data voltage to the control terminal of the first driving module through a coupling module. This eliminates the need to set the conduction state of the first driving module based on the magnitude of the first data voltage. There is no voltage requirement between the first data voltage and the power supply voltage (e.g., the first power supply voltage) connected to the second terminal of the first driving module; the first power supply voltage can be flexibly set. Therefore, it can reduce the pixel voltage range, thereby reducing the bias voltage on the device and improving the reliability of the pixel circuit. Furthermore, this embodiment eliminates the need for a voltage writing control module or unit, resulting in a simple pixel circuit structure that saves layout space and thus improves PPI.

[0128] In this embodiment, the reset module 104 can be connected between the first power line L1 and the control terminal of the current control module 20. The first power line L1 is configured such that at least during the reset phase, the voltage transmitted changes from the first power supply voltage VDDW to the reset voltage VREF, and after the reset phase ends, it changes from the reset voltage VREF back to the first power supply voltage VDDW. Figure 17 Another pixel circuit driving method provided in this embodiment of the invention, refer to Figure 17 The driving method for this pixel circuit includes:

[0129] S110. During the voltage writing stage, the first voltage writing module is controlled to write a fixed level voltage to the control terminal of the first driving module, and the first data voltage is controlled to be written to the coupling module.

[0130] S1201. During the reset phase, the voltage transmitted on the first power line is controlled to switch from the first power supply voltage to the reset voltage, and the reset module is controlled to write the reset voltage to the control terminal of the current control module.

[0131] S1301. During the voltage normalization stage, the control sweep signal is written to the coupling module so that the coupling module couples the first data voltage to the control terminal of the first drive module, and at the same time controls the reset voltage to switch to the first power supply voltage.

[0132] S140. During the light-emitting stage, the control current control module drives the light-emitting module to emit light, and controls the voltage of the control terminal of the first driving module through the sweep frequency signal and the first data voltage, thereby controlling the voltage of the control terminal of the current control module to control the light-emitting time of the light-emitting module.

[0133] Continue to refer to Figure 10The first voltage writing module 103 is connected between the first initialization signal line and the control terminal G1 of the first driving module 101. The control terminal of the first voltage writing module 103 is connected to the first scan signal line S1. The voltage control module 10 also includes a first compensation module 105, which is connected between the first terminal N1 of the first driving module 101 and the control terminal G1. The control terminal of the first compensation module 105 is connected to the second scan signal line S2. The control terminal of the reset module 104 is connected to the reset signal line Set. The current control module 20 includes a first light emission control module 201, a first storage module 202, a second driving module 203, a second voltage writing module 204, a second storage module 205, an initialization module 206, a second compensation module 207, and a second light emission control module 208. The control terminal of the first light emission control module 201 serves as the control terminal of the current control module 20 and is connected to the first terminal N1 of the first driving module 101. The first storage module 202 is connected to the control terminal of the first light-emitting control module 201; the first light-emitting control module 201 is connected between the second power line L2 and the first terminal of the second driving module 203; the control terminal of the second voltage writing module 204 and the control terminal of the second compensation module 207 are both connected to the first scan signal line S1; the second voltage writing module 204 is connected between the second data line DATA2 and the first terminal of the second driving module 203; the second compensation module 207 is connected between the control terminal G2 and the second terminal of the second driving module 203; the initialization module 206 is connected between the second initialization signal line and the control terminal G2 of the second driving module 203; the control terminal of the initialization module 206 is connected to the third scan signal line S3; the control terminal of the second light-emitting control module 208 is connected to the first light-emitting control signal line EM1; and the second light-emitting control module 208 is connected between the second terminal of the second driving module 203 and the light-emitting module 30.

[0134] Combination Figure 11 In this embodiment, the voltage writing stage T1 includes an initialization stage t1, a second voltage writing stage t2, and a first voltage writing stage t3.

[0135] During the initialization phase t1, the third scan signal line transmits a low-level third scan signal S3 to control the initialization module 206 to turn on, and the second initialization voltage Vinit2 transmitted on the second initialization signal line is written to the control terminal G2 of the second drive module 203 to initialize the potential of the control terminal of the second drive module 203.

[0136] During the second voltage writing stage t2, the first scan signal line transmits a low-level first scan signal S1 to control the second voltage writing module 204, the second compensation module 207, and the first voltage writing module 103 to turn on. The second data voltage Vdata_I is written to the control terminal G2 of the second driving module 203 through the second voltage writing module 204, the second driving module 203, and the second compensation module 207. The potential of the control terminal G2 of the second driving module 203 is Vdata_I + Vth6, and it is stored in the second storage module 205, where Vth6 is the threshold voltage of the sixth transistor M6, realizing threshold compensation for the sixth transistor M6. At the same time, the first initialization voltage Vinit1 transmitted on the first initialization signal line is written to the control terminal G1 of the first driving module 101 through the first voltage writing module 103, realizing the initialization of the potential of the control terminal G1 of the first driving module 101.

[0137] During the first voltage writing stage t3, the second scan signal line transmits a low-level second scan signal S2 to control the first compensation module 105 to turn on. The first power supply voltage VDDW transmitted on the first power supply line L1 charges the control terminal G1 of the first drive module 101, thereby achieving threshold compensation for the first drive module 101. At the same time, the first data voltage Vdata_t transmitted on the first data line DATA1 is written to the first terminal of the coupling module 103.

[0138] In stage t4, the remaining sub-pixels undergo initialization stage t1, second voltage writing stage t2, and first voltage writing stage t3 row by row to complete the data writing of all pixel rows.

[0139] The specific operation of the reset phase T2, voltage normalization phase T3, and light emission phase T4 can be referred to the relevant descriptions in the above embodiments, and they also have the relevant beneficial effects described in the above embodiments, so they will not be repeated here.

[0140] Optionally, embodiments of the present invention also provide a display device, which includes the pixel circuit provided in any embodiment of the present invention. Figure 18 This is a schematic diagram of a display device provided in an embodiment of the present invention. This display device can not only... Figure 18 The mobile phone shown can also be a tablet, mobile phone, watch, wearable device, as well as electronic devices such as in-vehicle displays, camera displays, televisions, and computer screens. Since this display device includes the pixel circuitry provided in any embodiment of the present invention, the display device provided in the embodiments of the present invention also possesses the beneficial effects described in any embodiment of the present invention.

[0141] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0142] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: Voltage control module, current control module, and light-emitting module; The voltage control module includes a first driving module, a coupling module, a first voltage writing module, and a reset module. The first voltage writing module is used to transmit a fixed-level voltage to the control terminal of the first driving module, and the coupling module is used to couple a first data voltage and a frequency sweep signal to the control terminal of the first driving module. The first driving module is connected between the first power line and the control terminal of the current control module, and is used to control the voltage of the control terminal of the current control module according to the first data voltage and the frequency sweep signal, so as to control the light emission time of the light-emitting module. The current control module and the light-emitting module are connected between the second power line and the third power line, and the reset module is used to reset the control terminal voltage of the current control module. The pixel circuit further includes a third voltage writing module, which is connected between the first power line and the second terminal of the first driving module, for transmitting the voltage transmitted on the first power line to the second terminal of the first driving module; the third voltage writing module includes an eleventh transistor and a twelfth transistor, the gate of the eleventh transistor is connected to the second scan signal line, the first terminal of the eleventh transistor is connected to the first power line, and the second terminal of the eleventh transistor is connected to the second terminal of the first driving module, the gate of the twelfth transistor is connected to the second light emission control signal line, the first terminal of the twelfth transistor is connected to the first power line, and the second terminal of the twelfth transistor is connected to the second terminal of the first driving module.

2. The pixel circuit according to claim 1, characterized in that, The voltage transmitted on the first power line is a switching voltage.

3. The pixel circuit according to claim 2, characterized in that, The reset module is connected between the first power line and the control terminal of the current control module.

4. The pixel circuit according to claim 3, characterized in that, The first power line is configured such that at least during the reset phase, the voltage transmitted transitions from a first power supply voltage to a reset voltage, and after the reset phase ends, the voltage transitions from the reset voltage back to the first power supply voltage.

5. The pixel circuit according to claim 4, characterized in that, The reset module is used to transmit the reset voltage to the control terminal of the current control module during the reset phase.

6. The pixel circuit according to claim 5, characterized in that, The operation of the pixel circuit includes at least a voltage writing stage, a reset stage, and a voltage normalization stage. The reset stage is after the voltage writing stage and before the voltage normalization stage.

7. The pixel circuit according to claim 1, characterized in that, The first end of the first voltage writing module is connected to the first power line, and the second end of the first voltage writing module is connected to the control terminal of the first drive module. The first voltage writing module is used to write the first power supply voltage transmitted on the first power line to the control terminal of the first drive module.

8. The pixel circuit according to claim 6, characterized in that, The voltage control module further includes a first compensation module, a first end of which is connected to a first end of the first drive module, and a second end of which is connected to a control end of the first drive module. The first compensation module is used to compensate the threshold voltage of the first drive module during the voltage writing stage. The first end of the first voltage writing module is connected to the first initialization signal line, and the second end of the first voltage writing module is connected to the control terminal of the first driving module. The first voltage writing module is used to write the first initialization voltage transmitted on the first initialization signal line to the control terminal of the first driving module.

9. The pixel circuit according to claim 8, characterized in that, The first driving module includes a first transistor; and / or the first voltage writing module includes a second transistor; and / or the first compensation module includes a third transistor; and / or the reset module includes a fourth transistor.

10. The pixel circuit according to claim 9, characterized in that, The first terminal of the first transistor is connected to the first power supply line, the second terminal of the first transistor is connected to the control terminal of the current control module, the gate of the first transistor is connected to the coupling module, the gate of the second transistor is connected to the first scan signal line, the first terminal of the second transistor is connected to the first initialization signal line, the second terminal of the second transistor is connected to the gate of the first transistor, the gate of the third transistor is connected to the second scan signal line, the first terminal of the third transistor is connected to the second terminal of the first transistor, the second terminal of the third transistor is connected to the gate of the first transistor, the gate of the fourth transistor is connected to the reset signal line, the first terminal of the fourth transistor is connected to the first terminal of the first transistor, and the second terminal of the fourth transistor is connected to the control terminal of the current control module.

11. The pixel circuit according to claim 10, characterized in that, The first scan signal line is multiplexed as the first initialization signal line.

12. The pixel circuit according to claim 1, characterized in that, The first end of the coupling module is used to input the first data voltage and the frequency sweep signal, and the second end of the coupling module is connected to the control end of the first drive module.

13. The pixel circuit according to claim 12, characterized in that, The coupling module includes a first capacitor, a first end of which is connected to a first data line, and a second end of which is connected to the control terminal of the first driving module. The first data voltage and the sweep frequency signal share the first data line.

14. The pixel circuit according to claim 1, characterized in that, The current control module includes a first light-emitting control module and a first storage module. The control terminal of the first light-emitting control module is connected to the first terminal of the first driving module as the control terminal of the current control module. The first storage module is connected to the control terminal of the first light-emitting control module.

15. The pixel circuit according to claim 14, characterized in that, The current control module further includes a second driving module, a second voltage writing module, a second storage module, and a second light-emitting control module. The first end of the first light-emitting control module is connected to the second power supply voltage transmitted on the second power line. The second end of the first light-emitting control module is connected to the first end of the second driving module. The second end of the second driving module is connected to the light-emitting module through the second light-emitting control module. The second voltage writing module is used to write the second data voltage transmitted on the second data line to the control terminal of the second driving module, and the second storage module is connected to the control terminal of the second driving module.

16. The pixel circuit according to claim 15, characterized in that, The current control module further includes an initialization module, which is used to write the second initialization voltage transmitted by the second initialization signal line to the control terminal of the second drive module.

17. The pixel circuit according to claim 16, characterized in that, The current control module further includes a second compensation module, which is connected between the control terminal and the second terminal of the second drive module.

18. The pixel circuit according to claim 17, characterized in that, The light-emitting module includes light-emitting diodes.

19. The pixel circuit according to claim 18, characterized in that, The first light-emitting control module includes a fifth transistor, the second driving module includes a sixth transistor, the second voltage writing module includes a seventh transistor, the initialization module includes an eighth transistor, the second compensation module includes a ninth transistor, the second light-emitting control module includes a tenth transistor, the first storage module includes a second capacitor, and the second storage module includes a third capacitor. The gate of the fifth transistor is connected to the first terminal of the first driving module, the first electrode of the fifth transistor is connected to the second power line, the second electrode of the fifth transistor is connected to the first electrode of the sixth transistor, the second electrode of the sixth transistor is connected to the first electrode of the tenth transistor, the second electrode of the tenth transistor is connected to the first electrode of the light-emitting diode, the second electrode of the light-emitting diode is connected to the third power line, and the gate of the tenth transistor is connected to the first light-emitting control signal line. The gates of the seventh transistor and the ninth transistor are both connected to the first scan signal line. The first terminal of the seventh transistor is connected to the second data line. The second terminal of the seventh transistor is connected to the first terminal of the sixth transistor. The first terminal of the ninth transistor is connected to the gate of the sixth transistor. The second terminal of the ninth transistor is connected to the second terminal of the sixth transistor. The gate of the eighth transistor is connected to the third scan signal line. The first terminal of the eighth transistor is connected to the second initialization signal line. The second terminal of the eighth transistor is connected to the gate of the sixth transistor. The first terminal of the second capacitor and the first terminal of the third capacitor are both connected to the first terminal of the fifth transistor, the second terminal of the second capacitor is connected to the gate of the fifth transistor, and the second terminal of the third capacitor is connected to the gate of the sixth transistor.

20. The pixel circuit according to claim 19, characterized in that, The third scan signal line is multiplexed as the second initialization signal line.

21. The pixel circuit according to claim 1, characterized in that, The reset module is connected between the second end and the first end of the first drive module.

22. A driving method for a pixel circuit, characterized in that, The pixel circuit includes a voltage control module, a current control module, and a light-emitting module. The voltage control module includes a first driving module, a coupling module, a first voltage writing module, and a reset module. The coupling module and the first voltage writing module are both connected to the control terminal of the first driving module. The first driving module is connected between a first power line and the control terminal of the current control module. The current control module and the light-emitting module are connected between a second power line and a third power line. The reset module is connected to the control terminal of the current control module. The driving method for the pixel circuit includes: During the voltage writing phase, the first voltage writing module is controlled to write a fixed level voltage to the control terminal of the first driving module, and the first data voltage is controlled to be written to the coupling module. During the reset phase, the reset module is controlled to reset the voltage at the control terminal of the current control module; During the voltage normalization stage, a control sweep signal is written to the coupling module so that the coupling module couples the first data voltage to the control terminal of the first drive module. During the light-emitting phase, the current control module drives the light-emitting module to emit light, and controls the voltage of the control terminal of the first driving module through the frequency sweep signal and the first data voltage, thereby controlling the voltage of the control terminal of the current control module to control the light-emitting time of the light-emitting module.

23. The driving method for the pixel circuit according to claim 22, characterized in that, The first voltage writing module is connected between the first initialization signal line and the control terminal of the first driving module. The control terminal of the first voltage writing module is connected to the first scan signal line. The voltage control module further includes a first compensation module, which is connected between the first terminal and the control terminal of the first driving module. The control terminal of the first compensation module is connected to the second scan signal line. The control terminal of the reset module is connected to the reset signal line. The current control module includes a first light emission control module, a first storage module, a second driving module, a second voltage writing module, a second storage module, an initialization module, a second compensation module, and a second light emission control module. The control terminal of the first light emission control module serves as the control terminal of the current control module and is connected to the first terminal of the first driving module. The first storage module... The block is connected to the control terminal of the first light-emitting control module; the first light-emitting control module is connected between the second power line and the first terminal of the second driving module; the control terminals of the second voltage writing module and the second compensation module are both connected to the first scan signal line; the second voltage writing module is connected between the second data line and the first terminal of the second driving module; the second compensation module is connected between the control terminal and the second terminal of the second driving module; the initialization module is connected between the second initialization signal line and the control terminal of the second driving module; the control terminal of the initialization module is connected to the third scan signal line; the control terminal of the second light-emitting control module is connected to the first light-emitting control signal line; and the second light-emitting module is connected between the second terminal of the second driving module and the light-emitting module. The voltage writing phase includes an initialization phase, a first voltage writing phase, and a second voltage writing phase. During the initialization phase, the third scan signal transmitted by the third scan signal line controls the initialization module to be turned on; During the second voltage writing stage, the first scan signal transmitted by the first scan signal line controls the second voltage writing module, the second compensation module and the first voltage writing module to be turned on. During the first voltage writing phase, the second scan signal transmitted by the second scan signal line controls the first compensation module to turn on, and the first data voltage is written to the first end of the coupling module.

24. The driving method for the pixel circuit according to claim 23, characterized in that, During the reset phase, the reset signal transmitted by the reset signal line controls the reset module to turn on.

25. The driving method for a pixel circuit according to claim 24, characterized in that, During the light-emitting phase, the first light-emitting control signal transmitted by the first light-emitting control signal line controls the second light-emitting control module to turn on.

26. The driving method for a pixel circuit according to claim 25, characterized in that, The voltage transmitted on the first power line is a switching voltage, and the reset module is connected between the first power line and the control terminal of the current control module. The step of controlling the reset module to reset the voltage at the control terminal of the current control module during the reset phase includes: During the reset phase, the voltage transmitted on the first power line is controlled to switch from the first power supply voltage to the reset voltage, and the reset module is controlled to write the reset voltage to the control terminal of the current control module.

27. The driving method for a pixel circuit according to claim 26, characterized in that, During the voltage normalization stage, while writing the frequency sweep signal to the coupling module, the reset voltage is also controlled to jump to the first power supply voltage.

28. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1-21.

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