Low disturbance operation method for cross-point array memory
By applying a specific voltage pulse cycle to the cross-matrix memory, the disturbance problem of unselected memory cells is solved, resulting in smaller read/write disturbances and a lower bit error rate, thus improving the stability of the memory and its resistance to multiple accesses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2023-08-25
- Publication Date
- 2026-07-21
AI Technical Summary
Unselected memory cells in a cross-matrix memory are subject to random and repeated positive and negative pulse disturbances, resulting in memory state shifts and bit flips. Existing technologies make it difficult to achieve low-disturbance operation.
The cross-dot matrix memory array is operated using four consecutive voltage pulse cycles. By applying specific voltage pulses to selected and unselected memory cells, the impact of disturbances is reduced. This includes high-voltage access and reverse recovery voltage pulses, specifically a combination of GND and Vdd, Vdd/3.
It achieves smaller read/write disturbances, lower bit error rate, and larger storage window, improving the memory's resistance to multiple access disturbances.
Smart Images
Figure CN117198349B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor memory, and in particular to a low-disturbance operation method for cross-matrix memory. Background Technology
[0002] With the continuous advancement of electronic information technology, the demand for low-power and high-density memory arrays is constantly increasing in both the storage field and advanced in-memory computing and in-sensor computing fields. However, traditional memory generally requires multiple devices (SRAM, DRAM, etc.) or multi-terminal devices (Flash, etc.). The contact vias of multiple device units or multi-terminal devices will cause a large area overhead, thus limiting the further improvement of memory array density.
[0003] Cross-matrix memory arrays based on two-terminal devices solve this problem. Common two-terminal devices include resistive random access memory (RRAM), phase-change memory (PCRAM), and ferroelectric-based memories (FeCAP, FTJ, FeDiode, etc.). Cross-matrix memory arrays constructed from these devices with storage characteristics can achieve speeds down to 4F in-plane. 2 With its smaller cell area and further 3D stacking potential, it represents a highly promising technological approach to increasing memory density.
[0004] However, since cross-matrix memory arrays lack additional gating transistors, unselected cells are subject to voltage pulse disturbances when information is written to them; with a common low-perturbation V... dd / 3 Example of operation mode: When writing to a certain cell, the cell receives an amplitude of V. dd The write pulse triggers a flip; other unselected cells on the same word line or bit line as the selected cell will receive a V value. dd A pulse disturbance of height / 3; simultaneously, all other unselected cells not in the same word / bit line will receive -V. dd / 3 height pulse perturbation. Therefore, in a cross-matrix memory array, memory cells are subject to random and repeated positive and negative pulse perturbations, which can cause severe shifts in the cell's storage state and even bit flips. Therefore, achieving low-perturbation operation in a cross-matrix memory has become a pressing problem. Summary of the Invention
[0005] The purpose of this invention is to propose a low-perturbation operation method for cross-matrix memory. Operating a cross-matrix memory array using this invention enables the memory to have smaller cell perturbations, a lower bit error rate, and a larger storage window.
[0006] The specific technical solution of this invention is as follows:
[0007] A low-disturbance operation method for cross-matrix memory is disclosed. This method operates on a cross-matrix memory array having multiple word lines and bit lines. The intersection of each word line and bit line is a memory cell, including resistive random access memory (RRAM), phase-change memory (PCM), magnetic memory, ferroelectric memory, etc. The operation method involves simultaneously applying voltage pulses to one word line and one bit line of the cross-matrix array to select a specific memory cell, while all other memory cells are unselected. The word line and bit line containing the selected memory cell are the selected word line and selected bit line, respectively, while all other word lines and bit lines are the unselected word line and unselected bit line, respectively. The operation requires four consecutive pulse cycles.
[0008] (1) The first cycle performs the operation on the selected memory cell while perturbing other unselected memory cells. The following three cycles restore the perturbation of the unselected memory cells. Specifically, in the first cycle, GND (V) is applied to the word / bit line containing the selected memory cell. dd ) and V dd (GND) is used to enable high-voltage access to the selected memory cell; unselected word / bit lines require a 2V voltage. dd / 3(V dd / 3) and V dd / 3(2V dd / 3) To reduce the disturbance of access pulse voltage to unselected memory cells, wherein the V dd The voltage is the core operating voltage, and its value can change the original storage state of the storage cell in part or in whole. The value varies depending on the type and structure of the storage cell.
[0009] (2) In the second cycle, V is applied to the selected word / bit line. dd / 3(GND) and GND(V) dd / 3), while applying GND (V) to unselected word / bit lines. dd / 3) and V dd / 3 (GND) voltage pulse to recover from disturbances to memory cells that are not selected for non-word / bit lines;
[0010] (3) In the third cycle, V is applied to the selected word / bit line. dd / 3(GND) and GND(V) dd / 3), at the same time, GND is applied to the unselected word / bit line to realize the disturbance recovery of the unselected memory cell on the same word line;
[0011] (4) In the fourth cycle, V is applied to the selected word / bit line. dd / 3(GND) and GND(V) dd / 3), while unselected words / bitlines are simultaneously subjected to V dd / 3, to achieve disturbance recovery for unselected memory cells on the same line.
[0012] In the first cycle, the selected memory cell is subjected to V dd High-voltage access, while unselected memory cells on the same word line and same bit line are subjected to V dd / 3 voltage pulse disturbance, all unselected memory cells other than the same word / bit line are subjected to -V dd A voltage pulse disturbance of / 3 is applied. To eliminate the influence of this disturbance voltage on the storage state of each unselected memory cell, in the last three cycles, a recovery voltage pulse in the opposite direction to the disturbance voltage is applied to the unselected memory cells of the same word line, same bit line, and non-same word / bit line, respectively. That is, in the first cycle, the unselected memory cells of the non-same word / bit line are subjected to V dd / 3 voltage recovery pulse; in the second to fourth cycles, unselected memory cells on the same word line and same bit line are subjected to -V dd A voltage recovery pulse of 3 / 3 is used to achieve recovery operations on all disturbed memory cells.
[0013] The beneficial effects and corresponding principles of the ultra-low perturbation operation method for cross-matrix memory of the present invention are as follows:
[0014] When a memory cell of a cross-matrix memory is accessed according to the ultra-low disturbance operation method of the present invention, in the first cycle, all other unselected memory cells will be affected by a magnitude of V. dd The disturbance voltage pulse of / 3, in the following three cycles, all unselected memory cells will successively receive reverse recovery voltage pulses to restore the impact of the disturbance voltage pulse on the memory state. Compared to traditional V... dd Compared to the / 3 write mode, the ultra-low perturbation operation method of the present invention can achieve smaller read and write perturbations, lower bit error rate and higher storage window, while greatly improving the memory's resistance to multiple access perturbations. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the cross-dot matrix memory array of the ultra-low disturbance operation method of the present invention;
[0016] In the picture:
[0017] 1 - Selected bitline; 2 - Unselected bitline
[0018] 3 - Selected text line 4 - Unselected text line
[0019] 5 - Select storage unit
[0020] Figure 2 This is a voltage pulse diagram of the ultra-low disturbance operation method of the present invention. Detailed Implementation
[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.
[0022] This invention provides a method for operating a cross-matrix memory. For example... Figure 1 As shown, the cross-matrix memory array is formed by the overlapping of multiple word lines and bit lines. The memory consists of multiple memory cells arranged in an array, and the two sides of the memory cell array are connected by substantially orthogonal word lines and bit lines. During the access of a memory cell, the word line and bit line containing the selected memory cell are the selected word line and selected bit line, while the other word lines and bit lines are the unselected word line and unselected bit line. All other memory cells sharing the same word line as the selected memory cell are unselected memory cells sharing the same word line; all other memory cells sharing the same bit line as the selected memory cell are unselected memory cells sharing the same bit line; and all other memory cells not sharing word lines and bit lines with the selected memory cell are unselected memory cells not sharing the same word / bit line.
[0023] Perform a write operation on the selected memory cell, such as Figure 2 As shown, taking writing data 1 as an example, the write operation is divided into four cycles. In the first cycle, the selected word line and bit line are given amplitudes of GND and V respectively. dd A voltage pulse is applied to both the unselected word line and the unselected bit line, with an amplitude of 2V. dd / 3 and V dd / 3; In the second cycle, pulses are sent to the selected word line and the selected bit line, with an amplitude of V. dd / 3 and GND, the unselected word line and the unselected bit line are simultaneously pulsed, with amplitudes of GND and V respectively. dd / 3; In the third cycle, pulses are sent to the selected word line and the selected bit line, with an amplitude of V. dd / 3 is placed on GND, and both the unselected word line and bit line are placed on GND; in the fourth cycle, the selected word line and the selected bit line are given pulses with an amplitude of V. dd / 3 and GND, both the unselected word line and bit line are given an amplitude of V. dd / 3 pulse.
[0024] For writing a 0, the voltage pulse used to write a 1 needs to be swapped on the word line / bit line. This method allows for the recovery of storage state disturbances experienced by unselected memory cells during the write process, resulting in smaller read / write disturbances, lower bit error rates, and a larger storage window. It also significantly improves the memory's resistance to multiple access disturbances.
[0025] The beneficial effects of the present invention are illustrated in this embodiment:
[0026] Conventional interleaved-array memory operation suffers from drawbacks such as high bit error rate, small storage window, and accumulation of multiple disturbances due to voltage pulse perturbations in unselected memory cells. This invention employs a perturbation recovery method. Through a special voltage pulse design on the word lines and bit lines, it achieves perturbation recovery operations for unselected memory cells during memory access, thereby reducing the impact of perturbation pulses on the cell storage state and improving the stability of stored data. In summary, this invention achieves smaller read / write perturbations, a lower bit error rate, and a larger storage window in interleaved-array memory, while significantly improving the memory's resistance to multiple access disturbances.
[0027] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.
Claims
1. A low-disturbance operation method for a cross-matrix memory, wherein the method operates on a cross-matrix memory array having multiple word lines and bit lines, the intersection of each word line and bit line being a memory cell, and simultaneously applying voltage pulses to one word line and one bit line in the array to obtain a selected memory cell, while the other memory cells are unselected memory cells; characterized in that, By applying voltage pulses to the word lines and bit lines, the selected and unselected memory cells are subjected to the following four consecutive pulse cycles: 1) In the first cycle, for the word / bit line containing the selected memory cell, apply GND and V. dd To enable high-voltage access to selected memory cells, 2V is applied to unselected word / bit lines. dd / 3 and V dd / 3; 2) In the second cycle, V is applied to the selected word / bit line. dd / 3 and GND, while unselected word / bit lines apply GND and V. dd / 3 voltage pulse; 3) In the third cycle, V is applied to the selected word / bit line. dd / 3 and GND, while unselected word / bit lines are simultaneously subject to GND; 4) In the fourth cycle, V is applied to the selected word / bit line. dd / 3 and GND, while unselected words / bitlines are simultaneously subjected to V. dd / 3 pulse.
2. The low-disturbance operation method for cross-matrix memory as described in claim 1, characterized in that, The operation of writing 0 and the voltage pulse of writing 1 are swapped on the word line / bit line.
3. The low-disturbance operation method for cross-matrix memory as described in claim 1, characterized in that, The storage unit is a resistive random access memory, a phase change memory, a magnetic memory, or a ferroelectric memory.