A refresh address generation circuit

Abstract

This application discloses a refresh address generation circuit, including a refresh control circuit, a repeat command processing circuit, and an address generator. The refresh control circuit sequentially receives multiple first refresh commands and performs multiple first refresh operations accordingly. When the number of first refresh operations is less than k, it outputs a first clock signal. The repeat command processing circuit is coupled to the refresh control circuit and receives the first refresh commands. When a repeat command appears in the first refresh command, it outputs an additional refresh flag signal. The address generator is coupled to the refresh control circuit and the repeat command processing circuit, and pre-stores a first address. When the first clock signal is received but the additional refresh flag signal is not received, the generator outputs the address to be refreshed in response to the first clock signal; or, when the additional refresh flag signal is received, the generator outputs an additional address in response to the additional refresh flag signal. This application can avoid wasting instructions and improve refresh efficiency.

Description

Technical Field

[0001] This application relates to, but is not limited to, a refresh address generation circuit. Background Technology

[0002] In memory, memory is divided into multiple banks, and there are two modes for refreshing memory addresses: All Bank Refresh, which refreshes all banks together at the same address, and Same Bank Refresh, which refreshes different banks in the same bank group sequentially at the same address.

[0003] If a refresh command is mistakenly sent or missed during the refresh process of the storage address, it will cause repeated refreshes and result in waste. Summary of the Invention

[0004] In view of this, embodiments of this application provide a refresh address generation circuit that can utilize redundant repetitive instructions to refresh additional addresses that require refreshing, thereby avoiding the waste of instructions and improving refresh efficiency.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application embodiment provides a refresh address generation circuit, the refresh address generation circuit comprising:

[0007] The refresh control circuit is used to receive multiple first refresh instructions in sequence and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1.

[0008] A repeat command processing circuit, coupled to the refresh control circuit, is used to receive the first refresh command and output an additional refresh flag signal when a repeat command appears in the first refresh command.

[0009] An address generator, coupled to the refresh control circuit and the repeat command processing circuit, and pre-stores a first address, for outputting an address to be refreshed in response to the first clock signal when the first clock signal is received but the additional refresh flag signal is not received, or outputting an additional address in response to the additional refresh flag signal when the additional refresh flag signal is received; wherein, the address to be refreshed includes the first address or the second address, the second address being adjacent to the first address; the difference between the additional address and the first address is greater than a preset threshold.

[0010] Therefore, this application provides a refresh address generation circuit, including a refresh control circuit, a repeat command processing circuit, and an address generator. The refresh control circuit sequentially receives multiple first refresh instructions and performs multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1. The repeat command processing circuit is coupled to the refresh control circuit and receives the first refresh instructions. When a repeat instruction appears in the first refresh instructions, it outputs an additional refresh flag signal. The address generator is coupled to the refresh control circuit and the repeat command processing circuit, and pre-stores a first address. When the first clock signal is received but the additional refresh flag signal is not received, the address generator outputs the address to be refreshed in response to the first clock signal; or, when the additional refresh flag signal is received, it outputs an additional address in response to the additional refresh flag signal. The address to be refreshed includes either a first address or a second address, where the second address is adjacent to the first address, and the difference between the additional address and the first address is greater than a preset threshold. Thus, by utilizing the redundant repeat instructions in the first refresh instructions, the additional addresses that need refreshing are refreshed, thereby achieving effective utilization of repeat instructions, avoiding instruction waste, and improving refresh efficiency. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 1 ;

[0012] Figure 2 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 1 ;

[0013] Figure 3 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 2 ;

[0014] Figure 4 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 2 ;

[0015] Figure 5 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 3 ;

[0016] Figure 6 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 3 ;

[0017] Figure 7 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 4 ;

[0018] Figure 8This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 5 ;

[0019] Figure 9 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 6 ;

[0020] Figure 10 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 7 ;

[0021] Figure 11 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 4 ;

[0022] Figure 12 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 8 ;

[0023] Figure 13 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 9 ;

[0024] Figure 14 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 5 ;

[0025] Figure 15 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 ;

[0026] Figure 16 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 6 ;

[0027] Figure 17 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 7 ;

[0028] Figure 18 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 one;

[0029] Figure 19 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 two;

[0030] Figure 20 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 8 ;

[0031] Figure 21This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 three;

[0032] Figure 22 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 9 ;

[0033] Figure 23 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Four;

[0034] Figure 24 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 ;

[0035] Figure 25 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 five;

[0036] Figure 26 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 six;

[0037] Figure 27 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 one;

[0038] Figure 28 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 seven;

[0039] Figure 29 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 two;

[0040] Figure 30 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 three;

[0041] Figure 31 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 eight;

[0042] Figure 32 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Nine;

[0043] Figure 33 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Four;

[0044] Figure 34This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 five;

[0045] Figure 35 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 2 ten;

[0046] Figure 36 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 six;

[0047] Figure 37 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 seven;

[0048] Figure 38 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 eight. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0051] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0053] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is commonly used in electronic devices. In DDR4 SDRAM or earlier, refresh operations were performed on all banks simultaneously, meaning all banks refreshed at the same address at the same time—this is known as All Bank Refresh. DDR5 SDRAM introduced Same Bank Refresh. This means that in Same Bank Refresh mode, different banks within the same bank group cannot be refreshed simultaneously. However, if refresh commands are mistakenly sent or missed, duplicate refreshes can occur, leading to wasted resources.

[0054] Figure 1 This is a schematic diagram of a refresh address generation circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, this application embodiment provides a refresh address generation circuit 10, including: a refresh control circuit 101, a repeat command processing circuit 102, and an address generator 103. Wherein:

[0055] The refresh control circuit 101 is used to sequentially receive multiple first refresh instructions SB CMD<0:m-1> and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1.

[0056] The repeat command processing circuit 102 is coupled to the refresh control circuit 101 and is used to receive the first refresh command SB CMD and output an extra refresh flag signal Extra Refresh Flag when a repeat command appears in the first refresh command SB CMD.

[0057] Address generator 103 is coupled to refresh control circuit 101 and repeat command processing circuit 102, and pre-stores a first address. When a first clock signal is received but no extra refresh flag signal is received, it outputs the address to be refreshed in response to the first clock signal; or, when an extra refresh flag signal is received, it outputs an extra address in response to the extra refresh flag signal. The address to be refreshed includes the first address or the second address, and the second address is adjacent to the first address. The difference between the extra address and the first address is greater than a preset threshold.

[0058] It should be noted that, in the embodiments of this application, the coupling methods include: direct electrical connection, and electrical connection through other electrical components (such as resistors, timers, or inverters). The term "coupling" as used below will encompass these methods, and will not be elaborated upon further.

[0059] It should be noted that the number of address bits in the first address can be set according to actual needs, and this application does not impose any restrictions on it. For example, if the first address is a 16-bit address, denoted as Address<15:0>, other addresses obtained from the first address are also 16-bit addresses.

[0060] In this embodiment of the application, the refresh control circuit 101 can sequentially receive multiple first refresh instructions SB CMD<0:m-1>, where SB CMD<0:m-1> represents m first refresh instructions SB CMD. <0> ~SB CMD <m-1>Each first refresh instruction (SB CMD) corresponds to a bank in each bank group, and each SB CMD triggers the corresponding bank in each bank group to perform a first refresh operation (i.e., Same Bank Refresh). Accordingly, multiple first refresh instructions (SB CMD<0:m-1>) received in sequence will trigger the corresponding banks in each bank group to perform a first refresh operation in sequence, that is, multiple first refresh operations will be performed in sequence.

[0061] In this embodiment, the Bank Group includes m Banks, and the number of Banks m is set according to chip design standards. Each Bank includes multiple rows of storage cells, and the address to be refreshed is the row address of the storage cell in the Bank. During the first refresh operation performed by the refresh control circuit 101, the address generator 103 outputs the address to be refreshed during the first refresh operation, and the storage cell in the Bank corresponding to the address to be refreshed, SB CMD, is refreshed.

[0062] In this embodiment, the refresh control circuit 101 can output a SameBank refresh clock signal SB CBR CLK, which includes a first clock signal. If the number of first refresh operations is less than m, it indicates that there are still banks in the Bank Group that have not yet undergone the first refresh operation on the memory cell where the address to be refreshed, and at this time, the refresh control circuit 101 outputs the first clock signal.

[0063] Figure 2 The waveform of a portion of the signal is shown when m=4. Combined with... Figure 1 and Figure 2 SB CMD <0> SB CMD <1> SBCMD <2> and SB CMD <3> These are the first refresh commands received sequentially by the refresh control circuit, each corresponding to one of the four banks in the same Bank Group: Bank0, Bank1, Bank2, and Bank3. Correspondingly, SB CMD <0> SB CMD <1> SB CMD <2> and SB CMD <3> The pulses in the clock signal can sequentially trigger the refresh control circuit 101 to perform the first refresh operation. The SameBank refresh clock signal SB CBR CLK includes the first clock signal, which is kept at a low level.

[0064] In this embodiment of the application, a repeat instruction refers to an additional refresh instruction issued for a specific Bank. For example... Figure 2 As shown, the first refresh command is SB CMD. <0> The process includes two pulses. The first pulse has already triggered the first refresh operation of Bank0, and the second pulse is the repeat instruction. In response to the repeat instruction, the Extra Refresh Flag signal jumps to a high level, and the repeat command processing circuit 102 outputs the Extra Refresh Flag signal, which jumps to a high level, to the address generator 103.

[0065] In this embodiment of the application, combined with Figure 1 and Figure 2 The address generator 103 pre-stores a first address. Upon receiving the first clock signal but not receiving an Extra Refresh Flag signal that transitions to a high level, it outputs the address to be refreshed (Address) in response to the first clock signal during each first refresh operation. The address to be refreshed includes either the first address or the second address, with the second address adjacent to the first address, meaning the second address differs from the first address by a value of 1. For example... Figure 2 In the example, the first address is n, and the address to be refreshed includes either the first address n or the second address n+1.

[0066] Continue to combine Figure 1 and Figure 2 When the address generator 103 receives the Extra Refresh Flag signal, which transitions to a high level, it outputs an extra address k or k+1 as the address to be refreshed. The difference between the extra address (k or k+1) and the first address n is greater than a preset threshold. Since the address refresh order is based on the address values, a suitable preset threshold can be set so that the refresh order of the extra address k or k+1 is sufficiently far from the first address n, thus ensuring that the refresh of the extra address k or k+1 does not affect the ongoing first refresh operation.

[0067] It is understood that the refresh address generation circuit 10 provided in this application embodiment uses the redundant duplicate instructions in the first refresh instruction to refresh the additional address that needs to be refreshed, thereby realizing the effective use of duplicate instructions, avoiding the waste of instructions, and improving refresh efficiency.

[0068] In some embodiments of this application, reference is made to Figure 1 and Figure 2 The refresh control circuit 101 is also used to output a second clock signal when the number of first refresh operations equals m. Correspondingly, the address generator 103 is also used to receive the second clock signal and change the first address to a third address in response to the second clock signal.

[0069] In this embodiment, the refresh control circuit 101 can output a SameBank refresh clock signal SB CBR CLK, which includes a first clock signal and a second clock signal. If the number of first refresh operations is equal to m, it indicates that the memory cells containing the addresses to be refreshed in all Banks of the Bank Group have completed the first refresh operation. At this time, the refresh control circuit 101 outputs the second clock signal.

[0070] Combination Figure 1 and Figure 2 The address output signal Addr Counter Output represents the first address stored in the address generator 103. When the refresh control circuit 101 performs the first refresh operation less than m times, the first address n stored in the address generator 103 remains unchanged, and the address output signal Addr Counter Output continues to be the first address n. When the memory cells corresponding to two adjacent addresses in all banks of the BankGroup have been refreshed, that is, when the refresh control circuit 101 performs the first refresh operation equal to m times, the address generator 103 changes the first address n in response to the second clock signal. The address generator 103 can change the first address by accumulation, and the accumulated value can be controlled by pulses in the second clock signal, such as... Figure 2 As shown, the second clock signal includes two pulses. Triggered by these two pulses, the address generator 103 increments the first address n by 1 twice, and the address output signal Addr Counter Output becomes n+2, thus matching the progress of address refresh. In the subsequent m first refresh operations, the address generator 103 continues to output the address to be refreshed based on the first address that has become n+2, so as to refresh the memory cells corresponding to the next two adjacent addresses of each Bank in the Bank Group. In this way, the memory cells corresponding to all addresses of each Bank in the Bank Group can be refreshed sequentially.

[0071] Understandably, during the first refresh operation, the address generator 103 responds to the first clock signal and outputs the address to be refreshed, including the first address or the second address, while keeping the first address unchanged. After the number of first refresh operations reaches a preset value k, the address generator 103 responds to the second clock signal and changes the first address. In this way, the refresh operation is carried out without omission, and the integrity of the address is maintained.

[0072] Figure 3 for Figure 1 The diagram shows an optional structure of the refresh control circuit 101. Figure 4 and Figure 5 For corresponding Figure 3 A schematic diagram of the signal.

[0073] It should be noted that, Figure 4 The signal timing of the refresh control circuit 101 receiving multiple first refresh instructions SB CMD sequentially and performing a first refresh operation is shown, wherein the preset quantity value m of the first refresh instructions SB CMD is equal to 4 as an example. Figure 5 The signal timing of the refresh control circuit 101 receiving the second refresh command AB CMD and performing the second refresh operation is shown.

[0074] In addition, Figure 4 and Figure 5 In the diagram, except for the first refresh instruction SB CMD, the counter signal Bank Counter, the counter reset signal Bank Counter Reset, and the SameBank refresh clock signal SB CBR CLK, all signals are shown as waveforms spanning four cycles. If each cycle contains two valid pulses, the valid pulse occurring earlier in the timing sequence is the first pulse, and the valid pulse occurring later in the timing sequence is the second pulse. The signal waveforms in subsequent figures are also divided according to a similar rule, which will not be elaborated upon further.

[0075] In some embodiments of this application, such as Figure 3 and Figure 4 As shown, the refresh control circuit 101 includes a refresh window signal generation circuit 201 and a clock pulse generation circuit 202.

[0076] The refresh window signal generation circuit 201 is used to receive multiple first refresh commands SB CMD (i.e., Figure 3 SBCMD shown <0> To SB CMD <m-1>The system generates a refresh window signal (Refresh Window) based on multiple first refresh instructions (SB CMD) and the refresh window reset signal (Refresh Window Reset). Reference... Figure 4 The pulse duration of the Refresh Window signal is the window time for the refresh control circuit 101 to perform one refresh operation. The Refresh Window Reset signal is used to reset the refresh window signal generation circuit 201 after a refresh operation is completed. Here, the refresh operation performed by the refresh control circuit 101 is the first refresh operation, that is, the first refresh operation is performed on the Bank corresponding to the first refresh instruction SB CMD.

[0077] A clock pulse generation circuit 202 is coupled to a refresh window signal generation circuit 201. It receives the refresh window signal Refresh Window and the first refresh instruction SB CMD. Before the m-th first refresh operation ends, the clock pulse generation circuit 202 generates a first clock signal if the number of first refresh instructions SB CMD received is less than or equal to m. Alternatively, after the m-th first refresh operation ends, a second clock signal is generated. (Reference) Figure 4 The SameBank refresh clock signal includes a first clock signal and a second clock signal, that is, the first clock signal and the second clock signal are the values ​​of the SameBank refresh clock signal at different time periods.

[0078] In some embodiments of this application, such as Figure 3 and Figure 4 As shown, the clock pulse generation circuit 202 includes: a counting circuit 203, a counting reset signal generation circuit 204, and a first pulse generation sub-circuit 205.

[0079] The counting circuit 203 is used to receive the first refresh command SB CMD and the counting reset signal Bank CounterReset, count the first refresh command SB CMD and output the counting signal Bank Counter, and reset according to the counting reset signal Bank Counter Reset.

[0080] The counter reset signal generation circuit 204 is coupled to the counter circuit 203 and the refresh window signal generation circuit 201, and is used to generate the counter reset signal Bank Counter Reset after the first refresh operation of the mth time.

[0081] The first pulse generation sub-circuit 205 is coupled to the count reset signal generation circuit 204, and is used to generate a first clock signal based on the count signal BankCounter when the first refresh instruction SBCMD is less than m, or to generate a second clock signal based on the count reset signal Bank Counter Reset when the first refresh instruction SBCMD is equal to m.

[0082] In some embodiments of this application, such as Figure 3 and Figure 4 As shown, the refresh window signal generation circuit 201 includes: multiple refresh window sub-signal generation circuits 206 and refresh window sub-signal processing circuits 207.

[0083] The multiple refresh window sub-signal generation circuit 206 is used to receive the refresh window reset signal Refresh WindowReset and, respectively, receive multiple first refresh instructions SB CMD, and, based on the multiple first refresh instructions SB CMD and the refresh window reset signal Refresh Window Reset, sequentially output multiple refresh window sub-signals ReW (i.e., ... Figure 3 The ReW shown <0> To ReW <m-1>).

[0084] The refresh window sub-signal processing circuit 207 is coupled to multiple refresh window sub-signal generation circuits 206, and is used to receive multiple refresh window sub-signals ReW in sequence, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.

[0085] In some embodiments of this application, such as Figure 3 and Figure 5 As shown, the refresh control circuit 101 is also used to receive the second refresh command AB CMD and perform the second refresh operation.

[0086] The multiple refresh window sub-signal generation circuit 206 is also used to simultaneously receive the second refresh instruction AB CMD and the refresh window reset signal Refresh Window Reset, and generate multiple identical refresh window sub-signals ReW according to the second refresh instruction AB CMD and the refresh window reset signal Refresh Window Reset.

[0087] The refresh window sub-signal processing circuit 207 is also used to receive multiple refresh window sub-signals ReW, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.

[0088] It should be noted that the second refresh operation is performed simultaneously on all banks in the Bank Group, i.e., AllBank Refresh. When the refresh control circuit 101 receives the second refresh instruction AB CMD and performs the second refresh operation, the first refresh instruction SB CMD does not contain a valid pulse and remains at a low level, i.e., the first refresh instruction SB CMD is invalid. Consequently, the counting signal Bank Counter also remains at a low level, and the counting refresh signal Bank Counter Reset does not generate a valid pulse and remains at a low level.

[0089] Correspondingly, when the refresh control circuit 101 receives multiple first refresh instructions SB CMD sequentially and performs the first refresh operation, the second refresh instruction AB CMD does not include a valid pulse and remains at a low level, that is, the second refresh instruction SBCMD is invalid.

[0090] In this embodiment, when the multiple refresh window sub-signal generation circuits 206 receive multiple first refresh commands SBCMD, the generated refresh window sub-signals ReW are all different because the multiple first refresh commands SBCMD are different. However, when the multiple refresh window sub-signal generation circuits 206 receive a second refresh command AB CMD, they can generate multiple identical refresh window sub-signals ReW.

[0091] Understandably, the refresh control circuit 101 can receive multiple first refresh commands SBCMD sequentially and perform a first refresh operation as needed, or receive a second refresh command AB CMD and perform a second refresh operation. In other words, a single refresh control circuit 101 can flexibly perform both refresh operations, thus improving circuit compatibility.

[0092] In some embodiments of this application, such as Figure 3 As shown, the refresh control circuit 101 also includes: a second pulse generation sub-circuit 208, an internal refresh window signal generation circuit 209, an address command signal generation circuit 210, and a refresh window reset signal generation circuit 211.

[0093] In this embodiment of the application, reference is made to Figure 3 , Figure 4 and Figure 5 The second pulse generation sub-circuit 208 is coupled to the refresh window signal generation circuit 207 and is used to receive the refresh window signal Refresh Window and the address command signal Addr CMD. When the refresh control circuit 101 starts to perform the first refresh operation or the second refresh operation, it generates the first pulse of the third clock signal AB CBR CLK and outputs the second pulse of the third clock signal AB CBR CLK according to the first pulse of the address command signal Addr CMD, thereby outputting the third clock signal AB CBR CLK.

[0094] refer to Figure 4 When the refresh control circuit 101 sequentially receives multiple first refresh commands SB CMD and performs a first refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the multiple first refresh commands SB CMD. <0> ~SB CMD <3> The effective pulse, namely the first pulse of the third clock signal AB CBR CLK, is generated when the refresh control circuit 101 starts performing the first refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal AddrCMD, that is, the second pulse of the third clock signal AB CBR CLK is generated based on the first pulse of the address command signal AddrCMD.

[0095] refer to Figure 5 When the refresh control circuit 101 receives the second refresh instruction AB CMD and performs the second refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the valid pulse of the second refresh instruction AB CMD, that is, the first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts performing the second refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal Addr CMD, that is, the second pulse of the third clock signal AB CBR CLK is generated according to the first pulse of the address command signal Addr CMD.

[0096] In this embodiment of the application, reference is made to Figure 3 , Figure 4 and Figure 5 The internal refresh window signal generation circuit 209 receives the third clock signal AB CBR CLK and generates the internal refresh window signal Inner ACTWindow based on it. The first pulse of the Inner ACTWindow signal is generated after the first pulse of the third clock signal AB CBR CLK and ends before the second pulse of the third clock signal AB CBR CLK. The second pulse of the Inner ACTWindow signal is generated after the second pulse of the third clock signal AB CBR CLK and ends before the pulse of the Refresh Window signal. It should be noted that the refresh controller in the memory receives the Inner ACTWindow signal and the address to be refreshed and refreshes the memory cell according to the Inner ACTWindow signal. Therefore, the duration of the Inner ACTWindow pulse is the time required to refresh the memory cell.

[0097] In this embodiment of the application, reference is made to Figure 3 , Figure 4 and Figure 5 The address command signal generation circuit 210 generates a first pulse and a second pulse of the address command signal Addr CMD based on the falling edge of the inner refresh window signal Inner ACT Window. The first pulse of the address command signal Addr CMD is used to generate the second pulse of the inner refresh window signal Inner ACT Window and the second pulse of the third clock signal AB CBR CLK. A falling edge of the inner refresh window signal Inner ACT Window indicates the end of refreshing an address, thereby generating the address command signal Addr CMD to control the generation of the next address.

[0098] refer to Figure 4 and Figure 5 The effective pulse of the inner refresh window signal Inner ACT Window can be compressed and shifted to obtain the effective pulse of the inner pre-command signal Inner PRE CMD. That is, the falling edge of the inner pre-command signal Inner PRE CMD is first obtained based on the falling edge of the inner refresh window signal Inner ACT Window. Then, the address command signal generation circuit 210 can generate the first pulse and the second pulse of the address command signal Addr CMD based on the falling edge of the inner pre-command signal Inner PRE CMD.

[0099] In this embodiment of the application, reference is made to Figure 3 , Figure 4 and Figure 5 The refresh window reset signal generation circuit 211 receives the inner refresh window signal Inner ACT Window and generates the pulse of the refresh window reset signal Refresh Window Reset based on the falling edge of the second pulse of the inner refresh window signal Inner ACT Window.

[0100] In some embodiments of this application, such as Figure 3 As shown, the refresh control circuit 101 also includes a signal selection circuit 212.

[0101] In this embodiment of the application, reference is made to Figure 3 , 4 5. Signal selection circuit 212 is coupled to counting circuit 203, first pulse generation sub-circuit 205 and second pulse generation sub-circuit 208, and is used to receive counting signal Bank Counter, first clock signal, second clock signal (the first clock signal and the second clock signal are the SameBank refresh clock signal SB CBR CLK) and third clock signal AB CBR CLK. When refresh control circuit 101 performs the first refresh operation, it outputs the first clock signal or the second clock signal according to counting signal BankCounter. Alternatively, when refresh control circuit 101 performs the second refresh operation, it outputs the third clock signal AB CBR CLK according to counting signal Bank Counter.

[0102] refer to Figure 3 and Figure 4 When the refresh control circuit 101 performs the first refresh operation, if any counting signal Bank Counter is high, the signal selection circuit 212 outputs the first clock signal, that is, the SameBank refresh clock signal SB CBR CLK is low. If all counting signals Bank Counter jump to low, the signal selection circuit 212 outputs the second clock signal, that is, two consecutive valid pulses in the SameBank refresh clock signal SB CBR CLK.

[0103] refer to Figure 3 and Figure 5 When the refresh control circuit 101 performs a second refresh operation, all counting signals Bank Counter remain at a low level. Figure 5 (not shown), then the signal selection circuit 212 outputs the valid pulse in the third clock signal AB CBRCLK.

[0104] In some embodiments of this application, such as Figure 3 As shown, the refresh control circuit 101 also includes an address flag signal generation circuit 213.

[0105] In this embodiment of the application, reference is made to Figure 3 , Figure 4 and Figure 5 The address flag signal generation circuit 213 is coupled to the address command signal generation circuit 210 and the refresh window signal generation circuit 207. It is used to receive the address command signal Addr CMD and the refresh window signal Refresh Window. It generates the rising edge of the address flag signal AddrFlag based on the first rising edge of the address command signal Addr CMD, and generates the falling edge of the address flag signal Addr Flag based on the falling edge of the refresh window signal Refresh Window.

[0106] In some embodiments of this application, such as Figure 6 As shown, the repeat command processing circuit 102 includes: a repeat command determination circuit 401 and an additional refresh flag signal generation circuit 402.

[0107] The repeat instruction determination circuit 401 is coupled to the counting circuit 203 and is used to receive the first refresh instruction SB CMD and the counting signal Bank Counter. When no repeat instruction appears in the first refresh instruction SB CMD, no output is made, and when a repeat instruction appears in the first refresh instruction SB CMD, the repeat instruction Extra CMD is output.

[0108] The Extra Refresh Flag signal generation circuit 402 is coupled to the Repeat Instruction Determination circuit 401 and the Refresh Window signal generation circuit 201. It is used to receive the Repeat Instruction Extra CMD and the Refresh Window signal Refresh Window, and generate an Extra Refresh Flag signal Extra Refresh Flag based on the Repeat Instruction Extra CMD and the Refresh Window signal Refresh Window. The rising edge of the Extra Refresh Flag signal Extra Refresh Flag is generated based on the valid pulse of the Repeat Instruction Extra CMD, and the falling edge of the Extra Refresh Flag signal Extra Refresh Flag is generated based on the falling edge of the Refresh Window signal Refresh Window.

[0109] Figure 7 Taking the preset quantity value m of the first refresh command SB CMD being equal to 4 as an example, it illustrates... Figure 6 The waveforms of each signal. In the embodiments of this application, combined with Figure 6 and Figure 7 A repeat instruction refers to an additional refresh instruction issued for a specific bank, such as... Figure 7 As shown, the first refresh command is SB CMD. <0> The process includes two pulses. The first pulse has already triggered the first refresh operation of Bank0, so the second pulse is the repeat instruction. The repeat instruction determination circuit 401 can determine whether a repeat instruction has appeared in the corresponding first refresh instruction SB CMD based on the counting signal BankCounter. For example, Figure 7 The normal first refresh instruction (SB CMD) excluding duplicate instructions <0> ~SB CMD <3> The timing of its pulses is related to the corresponding counting signal BankCounter. <0> ~Bank Counter <3> The rising edges are aligned one by one; and the first refresh instruction SB CMD <0> The repeat instruction in the code has its pulse timing aligned only with the counting signal Bank Counter. <0> The high-level state of the instruction allows us to identify the repeat instruction by comparing the timing of the normal first refresh instruction with that of the repeat instruction.

[0110] Continue to refer to Figure 6 and Figure 7 After determining the repeat instruction, the repeat instruction determination circuit 401 can output the valid pulse of the repeat instruction, that is, output the repeat instruction Extra CMD. Figure 7 (Not shown in the image). After receiving the Extra CMD instruction, the Extra Refresh Flag signal generation circuit 402 can, in response to the valid pulse in the Extra CMD instruction, switch the Extra Refresh Flag signal from low to high. That is, the rising edge of the Extra Refresh Flag signal is generated based on the valid pulse of the Extra CMD instruction. The Extra Refresh Flag signal generation circuit 402 also receives the Refresh Window signal and can, in response to the Refresh Window signal, switch the Extra Refresh Flag signal from high to low. That is, the falling edge of the Extra Refresh Flag signal is generated based on the falling edge of the Refresh Window signal.

[0111] In some embodiments of this application, reference is made to Figure 8 The address generator 103 includes an address counter 301 and an address processing circuit 302.

[0112] Address counter 301 is coupled to signal selection circuit 212 for pre-storing the first address and receiving SameBank refresh clock signal SB CBR CLK or third clock signal AB CBR CLK from signal selection circuit 212. Figure 6 (Not shown in the image). Address counter 301 can change the first address to the third address according to the second clock signal in the SameBank refresh clock signal SB CBR CLK, or change the first address and output the fourth and fifth addresses according to the third clock signal AB CBR CLK.

[0113] Address processing circuit 302 is coupled to address counter 301, refresh window sub-signal generation circuit 206 and repeat command processing circuit 102. It is used to receive address flag signal Addr Flag and obtain the first address when the refresh control circuit performs the first refresh operation. If no extra refresh flag signal Extra Refresh Flag is received, the first address or the second address is output according to the address flag signal Addr Flag. If the extra refresh flag signal Extra Refresh Flag is received, the extra address is output within the window time of the extra refresh flag signal Extra Refresh Flag.

[0114] The address processing circuit 302 is also used to sequentially obtain the fourth address and the fifth address when the refresh control circuit performs the second refresh operation, and to sequentially output the fourth address and the fifth address according to the multiple refresh window sub-signals ReW.

[0115] In this embodiment, when the refresh control circuit performs the first refresh operation and the address processing circuit 302 does not receive the Extra Refresh Flag signal, the first address is a pre-stored address, and the second address is adjacent to the first address, meaning the first and second addresses are consecutive addresses. Therefore, the third address is incremented by 2 based on the first address to avoid repeating the first refresh operation on the same address. Thus, after all banks have completed the first refresh operation on the first and second addresses, the first address is incremented by 2 to become the third address. The refresh control circuit can then use the third address as a pre-stored address to perform a new round of the first refresh operation, ensuring that the first refresh operation is performed without omission.

[0116] In this embodiment, when the refresh control circuit performs the second refresh operation, the first address is a pre-stored address, the fourth address is incremented by 1 based on the first address, and the fifth address is incremented by 1 based on the fourth address. That is, the first address, the fourth address, and the fifth address are three consecutive addresses. In this way, the refresh control circuit 101 can perform the second refresh operation on all Bank addresses sequentially according to the address order, thereby ensuring that the second refresh operation is performed without omission.

[0117] In this embodiment of the application, combined with Figure 4 and Figure 8 When the signal selection circuit 212 outputs the second clock signal (i.e., two valid pulses in SBCBR CLK) to the address counter 301, the address counter 301 can sequentially increment the first address by 2 based on the two valid pulses of the second clock signal to obtain the third address. When the signal selection circuit 212 outputs the third clock signal AB CBR CLK to the address counter 301, the address counter 301 can increment the first address by 1 based on the first pulse of the third clock signal AB CBR CLK to obtain the fourth address. Then, the address counter 301 can increment the fourth address by 1 based on the second pulse of the third clock signal AB CBR CLK to obtain the fifth address.

[0118] In this embodiment of the application, when the refresh control circuit performs a first refresh operation and the address processing circuit 302 receives the Extra Refresh Flag signal, the address processing circuit 302 outputs an additional address within the window time of the Extra Refresh Flag signal. Combined with... Figure 2 and Figure 8 The address processing circuit 302 can select the target bit or the inverted target bit for output based on two different levels of the Extra Refresh Flag signal. When the Extra Refresh Flag signal is low, the address processing circuit 302 can select the target bit for output and combine it with the address bits other than the target bit to form a regular address n or n+1 for output. When the Extra Refresh Flag signal is high, the address processing circuit 302 can select the inverted target bit for output and combine it with the address bits other than the target bit to form an extra address k or k+1 for output. Here, the extra address k is obtained by inverting the target bit of the first address n, and the extra address k+1 is obtained by inverting the target bit of the second address n+1.

[0119] For example, if the first address n is "0000 0000 0000 0010", then the second address n+1 is "0000 0000000000011". The regular address includes both the first address n and the second address n+1. The target bit is the second bit from left to right (i.e., the second most significant bit). Thus, inverting the target bit in the first address n yields the additional address k as "0100 0000 0000 0010", and inverting the target bit in the second address yields the additional address k+1 as "0100 0000 0000 0011". It should be noted that the target bit can be any address bit higher than the preset bit. For example, if the preset bit is the third bit from left to right, then the target bit can be the first bit from left to right (i.e., the most significant bit) or the second bit from left to right (i.e., the second most significant bit).

[0120] Understandably, when triggered by the Extra Refresh Flag signal, the address generator 103 selects the target bit or its inverted form for output. This allows it to output an extra address when redundant instructions appear in the first refresh instruction. Thus, by utilizing the redundant instructions in the first refresh instruction to refresh the extra addresses that require refreshing, it avoids wasting instructions and improves refresh efficiency.

[0121] In some embodiments of this application, such as Figure 9 As shown, the address processing circuit 302 includes: a control signal generation circuit 303, an address selection circuit 304, and an additional address generation circuit 305.

[0122] The control signal generation circuit 303 is coupled to the refresh window sub-signal generation circuit 206 and the address flag signal generation circuit 213, and is used to receive multiple refresh window sub-signals ReW and address flag signals Addr Flag, and generate an address control signal Addr Ctrl based on the multiple refresh window sub-signals ReW and address flag signals Addr Flag.

[0123] Address selection circuit 304, coupled to address counter 301 and control signal generation circuit 303, is used to output the first address before the rising edge of address control signal Addr Ctrl when refresh control circuit 101 receives the first refresh instruction SB CMD, or to accumulate the first address after the rising edge of address control signal Addr Ctrl to obtain and output the second address. Address selection circuit 304 is also used to output the fourth and fifth addresses sequentially in response to address control signal Addr Ctrl when refresh control circuit 101 receives the second refresh instruction AB CMD.

[0124] An additional address generation circuit 305, coupled to an address selection circuit 304, is used to receive and output a first address or a second address when the refresh control circuit 101 performs a first refresh operation and the additional address generation circuit 305 does not receive an Extra Refresh Flag signal. Alternatively, when the refresh control circuit 101 performs a first refresh operation and the additional address generation circuit 305 receives an Extra Refresh Flag signal, it receives the first address or the second address, inverts the target bit in the first address or the second address according to the Extra Refresh Flag signal, and obtains and outputs the additional address, where the target bit is any address bit in the first address or the second address that is higher than a preset bit. Alternatively, when the refresh control circuit 101 performs a second refresh operation, the additional address generation circuit 305 is used to receive and output a fourth address or a fifth address.

[0125] In some embodiments of this application, such as Figure 10 As shown, the counting circuit 203 includes: multiple first inverters D1, multiple first latches L1, and a second inverter D2. The inputs of the multiple first inverters D1 sequentially receive multiple first refresh instructions (SB CMD). The input of the second inverter D2 receives a count reset signal (Bank Counter Reset). The set terminals of the multiple first latches L1 are sequentially connected to the outputs of the multiple first inverters D1, and the reset terminals of the multiple first latches L1 are all connected to the outputs of the second inverters D2. The multiple first latches L1 sequentially output multiple count signals (Bank Counter).

[0126] In the embodiments of this application, Figure 11 The signal timing diagram when m=4, combined with Figure 10 and Figure 11 Each valid pulse in the first refresh instruction SB CMD can trigger the corresponding counting signal Bank Counter to switch from low to high, as in the first refresh instruction SB CMD. <0> The pulse in the signal can trigger the counting signal Bank Counter. <0> The change from low to high level is also indicated by the first refresh instruction SB CMD. <1> SB CMD <2> and SB CMD <3> The pulses in the signal can trigger the counting signal Bank Counter respectively. <1> Bank Counter <2> and Bank Counter <3> The signal changes from low to high. A valid pulse in the Bank Counter Reset signal can trigger all Bank Counter counting signals. <0> ~Bank Counter <3> The signal transitions from high to low. The valid pulse in the Bank Counter Reset signal is generated after the refresh control circuit completes the m-th first refresh operation.

[0127] In some embodiments of this application, such as Figure 12 As shown, the counter reset signal generation circuit 204 includes: a first AND gate A1, a third inverter D3, a second AND gate A2, a first delay unit H1, a fourth inverter D4, and a third AND gate A3. The input of the first AND gate A1 receives multiple counting signals (Bank Counter). The input of the third inverter D3 receives a refresh window signal (Refresh Window). The input of the second AND gate A2 is connected to the outputs of the first AND gate A1 and the third inverter D3. The input of the first delay unit H1 is connected to the output of the second AND gate A2. The input of the fourth inverter D4 is connected to the output of the first delay unit H1. The input of the third AND gate A3 is connected to the outputs of the second AND gate A2 and the fourth inverter D4, and the third AND gate A3 outputs a counter reset signal (Bank Counter Reset).

[0128] In some embodiments of this application, such as Figure 13 As shown, the first pulse generation sub-circuit 205 includes: a second delay unit H2, a third delay unit H3, and a first OR gate B1. The input of the second delay unit H2 receives the count reset signal BankCounter Reset. The input of the third delay unit H3 is connected to the output of the second delay unit H2. The input of the first OR gate B1 is connected to the outputs of the second delay unit H2 and the third delay unit H3, respectively. The first OR gate B1 outputs either a first clock signal or a second clock signal; that is, the first OR gate B1 outputs the SameBank refresh clock signal SB CBR CLK.

[0129] In the embodiments of this application, Figure 14 The signal timing diagram when m=4, combined with Figure 12 , Figure 13 and Figure 14 In the case of the first refresh operation, the pulse in the Bank Counter Reset signal is based on the BankCounter signal. <0> Bank Counter <1> Bank Counter <2> Bank Counter <3> This is generated in conjunction with the Refresh Window signal. A valid pulse from the Bank Counter Reset signal, after passing through the second delay unit H2, the third delay unit H3, and the first OR gate B1, generates two valid pulses in SB CBR CLK. Specifically, the first delay unit H1 can delay the received signal by 0–2 ns, the second delay unit H2 can delay the received signal by 1–3 ns, and the third delay unit H3 can delay the received signal by 4–6 ns.

[0130] In some embodiments of this application, such as Figure 15 As shown, the refresh window sub-signals include: the first refresh window sub-signal ReW. Or the second refresh window sub-signal ReW <ab>Each refresh window sub-signal generation circuit 206 includes: a first NOR gate E1 and a second latch L2. When the refresh control circuit performs the first refresh operation, the first input terminal of the first NOR gate E1 receives the corresponding first refresh command SB CMD. Alternatively, when the refresh control circuit performs a second refresh operation, the second input of the first NOR gate E1 receives the second refresh instruction AB CMD. The set input of the second latch L2 is connected to the output of the first NOR gate E1, and the reset input of the second latch L2 receives the refresh window reset signal Refresh Window Reset; when the refresh control circuit performs a first refresh operation, the second latch L2 outputs the corresponding first refresh window sub-signal ReW. Alternatively, when the refresh control circuit performs a second refresh operation, the second latch outputs the corresponding second refresh window sub-signal ReW. <ab>Here, i is greater than or equal to 0 and less than or equal to m-1, and the first refresh instruction is SB CMD. For any of a plurality of first refresh instructions, the first refresh window sub-signal ReW Corresponding to the first refresh command SB CMD .

[0131] In the embodiments of this application, Figure 16 The signal timing diagram when m=4, combined with Figure 15 and Figure 16 When the refresh control circuit performs the first refresh operation, the first refresh instruction SB CMD is executed. <0> The valid pulse in the signal triggers the first refresh window sub-signal ReW. <0> The transition from low to high level triggers the first valid pulse in the Refresh Window Reset signal, which in turn triggers the first refresh window sub-signal, ReW. <0> The signal transitions from high to low, thus obtaining the first refresh window sub-signal ReW. <0> The valid pulse. Similarly, the first refresh instruction SB CMD <0> SB CMD <1> and SB CMD <2> The valid pulses in the signal trigger the first refresh window sub-signal ReW respectively. <0> ReW <1> and ReW <2> The transition from low to high level triggers the second to fourth valid pulses in the Refresh Window Reset signal, which in turn trigger the first Refresh Window sub-signal ReW. <0> ReW <1> and ReW <2> The signal transitions from high to low, thus obtaining the first refresh window sub-signal ReW. <0> ReW <1> and ReW <2> The effective pulse.

[0132] In this embodiment of the application, combined with Figure 15 and Figure 17 When the refresh control circuit performs the second refresh operation, the valid pulse in the second refresh instruction AB CMD triggers the second refresh window sub-signal ReW. <ab>The transition from low to high level triggers the second window refresh sub-signal, ReW, when a valid pulse in the Refresh Window Reset signal is applied. <ab>The signal transitions from high to low, thus generating the second refresh window sub-signal ReW. <ab>The effective pulse.

[0133] In some embodiments of this application, combined with Figure 15 and Figure 18 The refresh window sub-signal processing circuit 207 includes a second OR gate B2. When the refresh control circuit performs a first refresh operation, the input of the second OR gate B2 receives multiple first refresh window sub-signals ReW from the multiple refresh window sub-signal generation circuits 206. Alternatively, when the refresh control circuit performs a second refresh operation, the input of the second OR gate receives the same multiple second refresh window sub-signals ReW from the multiple refresh window sub-signal generation circuit 206. <ab>The second OR gate B2 outputs the Refresh Window signal.

[0134] In this embodiment of the application, reference is made to Figure 18 The refresh window signal generation circuit 201 also includes a twelfth inverter D12. The refresh window reset signal Refresh Window Reset is transmitted to multiple refresh window sub-signal generation circuits 206 after passing through the twelfth inverter D12.

[0135] In this embodiment of the application, reference is made to Figure 16 and Figure 18 When the refresh control circuit performs the first refresh operation, due to the first refresh window sub-signal ReW... <0> ~ReW <3> Both are active high; therefore, the Refresh Window signal output from the second OR gate B2 will include the first Refresh Window sub-signal ReW. <0> ~ReW <3> All valid pulses in the sequence.

[0136] In this embodiment of the application, reference is made to Figure 17 and Figure 18 When the refresh control circuit performs the second refresh operation, the second OR gate B2 receives the same multiple second refresh window sub-signals ReW. <ab>The refresh window signal RefreshWindow output from the second OR gate B2 and the second refresh window sub-signal ReW <ab>The waveforms are the same.

[0137] In some embodiments of this application, such as Figure 19 As shown, the second pulse generation sub-circuit 208 includes: a fourth delay unit H4, a fifth inverter D5, a fourth AND gate A4, a sixth inverter D6, a fifth AND gate A5, a second NOR gate E2, and a seventh inverter D7. The input of the fourth delay unit H4 receives the refresh window signal Refresh Window. The input of the fifth inverter D5 is connected to the output of the fourth delay unit H4. The first input of the fourth AND gate A4 receives the refresh window signal Refresh Window, and the second input of the fourth AND gate A4 is connected to the output of the fifth inverter D5. The input of the sixth inverter D6 receives the address flag signal Addr Flag. The first input of the fifth AND gate A5 is connected to the output of the sixth inverter D6, and the second input of the fifth AND gate A5 receives the address command signal Addr CMD. The input of the second NOR gate E2 is connected to the outputs of the fourth AND gate A4 and the fifth AND gate A5, respectively. The input of the seventh inverter D7 is connected to the output of the second NOR gate E2, and the seventh inverter D7 outputs the third clock signal AB CBR CLK.

[0138] In this embodiment of the application, reference is made to Figure 19 and Figure 20 The fourth delay unit H4 can delay the received refresh window signal Refresh Window by 1 to 3 ns. Then, after passing through the fourth delay unit H4, the fifth inverter D5, and the fourth AND gate A4, the refresh window signal Refresh Window can be converted into the internal activation command signal Inner ACT CMD. The pulse in the internal activation command signal Inner ACT CMD corresponds to the rising edge of the refresh window signal Refresh Window. This pulse, after passing through the second NOR gate E2 and the seventh inverter D7, constitutes the first pulse of the third clock signal AB CBR CLK. The second pulse of the third clock signal AB CBR CLK is formed based on the address flag signal Addr Flag and the address command signal AddrCMD.

[0139] In some embodiments of this application, such as Figure 21 As shown, the address command signal generation circuit 210 includes: an eighth inverter D8, a fifth delay unit H5, and a sixth AND gate A6. The input of the eighth inverter D8 receives the inner refresh window signal InnerACT Window. The input of the fifth delay unit H5 is connected to the input of the eighth inverter D8 and also receives the inner refresh window signal InnerACT Window. The input of the sixth AND gate A6 is connected to the outputs of the eighth inverter D8 and the fifth delay unit H5, respectively, and the sixth AND gate A6 outputs the address command signal Addr CMD.

[0140] In this embodiment, the fifth delay unit H5 can delay the received inner refresh window signal Inner ACTWindow by 0 to 2 ns. Combined with... Figure 21 and Figure 22 After passing through the eighth inverter D8, the fifth delay H5, and the sixth AND gate A6, the first pulse of the Inner ACT Window signal can be converted into the first pulse of the Address Command signal Addr CMD, and the second pulse of the Inner ACT Window signal can be converted into the second pulse of the Address Command signal Addr CMD.

[0141] In some embodiments of this application, such as Figure 21 As shown, the internal refresh window signal generation circuit 209 includes a third latch L3. The set terminal of the third latch L3 receives the third clock signal AB CBR CLK, the reset terminal of the third latch L3 is connected to the output terminal of the eighth inverter D8, and the third latch L3 outputs the internal refresh window signal Inner ACT Window.

[0142] In some embodiments of this application, such as Figure 23 As shown, the refresh window reset signal generation circuit 211 includes: a sixth delay unit H6, a seventh AND gate A7, and a seventh delay unit H7. The input of the sixth delay unit H6 receives the address flag signal AddrFlag. The first input of the seventh AND gate A7 is connected to the output of the sixth delay unit H6, and the second input of the seventh AND gate A7 receives the inner refresh window signal Inner ACT Window. The input of the seventh delay unit H7 is connected to the output of the seventh AND gate A7, and the seventh delay unit H7 outputs the refresh window reset signal Refresh Window Reset.

[0143] In this embodiment, the sixth delay unit H6 can delay the received address flag signal Addr Flag by 0-2ns, and the seventh delay unit H7 can delay the received signal by 4-6ns. Combined with... Figure 23 and Figure 24 After passing through the sixth delay H6, the seventh AND gate A7, and the seventh delay H7, the refresh window reset signal Refresh Window Reset can be obtained from the inner refresh window signal Inner ACT Window and the address flag signal Addr Flag.

[0144] In some embodiments of this application, such as Figure 25 As shown, the signal selection circuit 212 includes: a third NOR gate E3, a third OR gate B3, and an eighth AND gate A8. The inputs of the third NOR gate E3 receive multiple counting signals, Bank Counter. The first input of the third OR gate B3 receives either a first clock signal or a second clock signal; that is, the first input of the third OR gate B3 receives the SameBank refresh clock signal SB CBR CLK, and the second input of the third OR gate B3 receives the third clock signal AB CBRCLK. The first input of the eighth AND gate A8 is connected to the output of the third NOR gate E3, and the second input of the eighth AND gate A8 is connected to the output of the third OR gate B3. The eighth AND gate A8 outputs either the first clock signal, the second clock signal, or the third clock signal ABCBR CLK.

[0145] In this embodiment of the application, combined with Figure 4 and Figure 25 During the first refresh operation, the waveforms of each signal received by the signal selection circuit 212 are as follows: Figure 4 As shown, the signal output by the third OR gate B3 can include all the valid pulses in the SameBank refresh clock signal SB CBR CLK and the third clock signal AB CBR CLK. However, the signal output by the third NOR gate E3 can mask the valid pulses in the third clock signal AB CBR CLK. Therefore, the signal output by the eighth AND gate A8 has the same waveform as the SameBank refresh clock signal SB CBR CLK. That is, in the case of performing the first refresh operation, the eighth AND gate A8 outputs either the first clock signal or the second clock signal.

[0146] During the second refresh operation, multiple counting signals (Bank Counter) <0> ~Bank Counter <3> Both the SameBank refresh clock signal SB, CBR, and CLK remain low. Figure 4 (not shown in the image), while the waveform of the third clock signal AB CBR CLK remains as shown. Figure 4 As shown, the signal output by the eighth AND gate A8 is the same as the waveform of the third clock signal ABCBRCLK. That is, when performing the first refresh operation, the eighth AND gate A8 outputs the third clock signal ABCBRCLK.

[0147] In some embodiments of this application, such as Figure 26 As shown, the address flag signal generation circuit 213 includes a ninth inverter D9 and a fourth latch L4. The input of the ninth inverter D9 receives the address command signal Addr CMD. The set terminal of the fourth latch L4 is connected to the output of the ninth inverter D9, the reset terminal of the fourth latch L4 receives the refresh window signal Refresh Window, and the fourth latch L4 outputs the address flag signal Addr Flag.

[0148] In this embodiment of the application, combined with Figure 26 and Figure 27 The first pulse of the address command signal Addr CMD triggers the address flag signal Addr Flag to transition from low to high. The falling edge of the refresh window signal Refresh Window triggers the address flag signal Addr Flag to transition from high to low, thus obtaining... Figure 27 The waveform of the address flag signal AddrFlag is shown.

[0149] Figure 28 An optional implementation of the refresh control circuit 101 is shown. Figure 28 This includes Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 18 , Figure 19 , Figure 21 , Figure 23 , Figure 25 and Figure 26 The circuit elements shown in the figure. Figure 29 and Figure 30 It shows Figure 28 An optional waveform diagram of the middle part of the signal, wherein, Figure 29 This is a schematic diagram of the signals corresponding to the first refresh operation performed by the refresh control circuit 101. Figure 30 A schematic diagram of the signals corresponding to the second refresh operation performed by the refresh control circuit 101.

[0150] Figure 28 Taking the Bank Group with a number of Banks m=4 as an example, therefore, Figure 28 It includes four first latches L1, four first inverters D1, and four refresh window sub-signal generation circuits 206.

[0151] Combination Figure 28 and Figure 29 When the refresh control circuit 101 performs the first refresh operation, four first refresh instructions SB CMD are issued. <0> SB CMD <1> SB CMD <2> and SB CMD <3> It includes valid pulses, and the second refresh instruction ABCMD ( Figure 29 (Not shown in the image) The second refresh instruction AB CMD remains low, meaning it does not include a valid pulse. Therefore, the set terminals of the four first latches L1 receive the four first refresh instructions SB CMD respectively through the four first inverters D1. <0> SB CMD <1> SB CMD <2> and SB CMD <3> The four first latches L1 output four counting signals, namely Bank Counter. <0> Bank Counter <1> Bank Counter <2> and Bank Counter <3> The signals are fed to the inputs of the third NOR gate E3 and the first AND gate A1. Then, the signal selection circuit 212 outputs the SameBank refresh clock signal SBCBR CLK (i.e., the first clock signal or the second clock signal) through the eighth AND gate A8. Simultaneously, the set terminals of the four second latches L2 receive the four first refresh instructions SB CMD through the four first NOR gates E1. <0> SB CMD <1> SB CMD <2> and SB CMD <3> The four second latches L2 output four first refresh window sub-signals ReW respectively. <0> ReW <1> ReW <2> and ReW <3> .

[0152] Combination Figure 9 , Figure 28 and Figure 29 It can be seen that when the refresh control circuit 101 performs the first refresh operation, the signal selection circuit 212 outputs the SameBank refresh clock signal SB CBR CLK (i.e., the first clock signal or the second clock signal) to the address processing circuit 102, and the four refresh window sub-signal generation circuits 206 output four first refresh window sub-signals ReW. <0> ReW <1> ReW <2> and ReW <3> The address flag signal generation circuit 213 outputs the address flag signal Addr Flag to the address processing circuit 102.

[0153] Combination Figure 28 and Figure 30 When the refresh control circuit 101 performs a second refresh operation, four first refresh instructions SB CMD are executed. <0> SB CMD <1> SB CMD <2> and SB CMD <3> ( Figure 30 (Not shown in the image) None of the signals include valid pulses, i.e., the four first refresh instructions SB CMD. <0> SB CMD <1> SB CMD <2> and SB CMD <3> All remain at a low level, while the second refresh instruction AB CMD includes a valid pulse. Therefore, the four counting signals BankCounter output from the four first latches L1... <0> Bank Counter <1> Bank Counter <2> and Bank Counter <3> All remain at a low level. Figure 30 (Not shown in the image). Furthermore, the signal selection circuit 212 outputs the third clock signal AB CBR CLK through the eighth AND gate A8. Simultaneously, the set terminals of the four second latches L2 receive the second refresh instruction AB CMD through four first NOR gates E1, and each of the four second latches L2 outputs four identical second refresh window sub-signals ReW. <ab>.

[0154] Combination Figure 9 , Figure 28 and Figure 30 It can be seen that when the refresh control circuit 101 performs the second refresh operation, the signal selection circuit 212 outputs the third clock signal AB CBR CLK to the address processing circuit 102, and the four refresh window sub-signal generation circuits 206 output four identical second refresh window sub-signals ReW. <ab>The address flag signal generation circuit 213 outputs the address flag signal Addr Flag to the address processing circuit 102.

[0155] In some embodiments of this application, such as Figure 31 As shown, the repeat instruction determination circuit 401 includes: multiple eighth delay units H8, multiple ninth AND gates A9, and a fourth NOR gate E4. The inputs of the multiple eighth delay units H8 sequentially receive multiple counting signals Bank Counter. <0> ~Bank Counter <m-1>The first inputs of multiple ninth AND gates A9 are sequentially connected to the outputs of multiple eighth delay units H8, and the second inputs of the multiple ninth AND gates A9 sequentially receive multiple first refresh commands SB CMD. <0> ~SB CMD <m-1>The inputs of the fourth NOR gate E4 are connected to the outputs of multiple ninth AND gates A9, and the fourth NOR gate E4 outputs a repeat instruction.

[0156] The additional refresh flag signal generation circuit 402 includes a fifth latch L5. The set terminal of the fifth latch L5 receives the repeat instruction Extra CMD, the reset terminal of the fifth latch L5 receives the refresh window signal Refresh Window, and the fifth latch L5 outputs the extra refresh flag signal Extra Refresh Flag.

[0157] In this embodiment of the application, combined with Figure 31 and Figure 7 Taking m=4 as an example, the first refresh instruction is SB CMD <0> There is a repeating instruction in the system. When this repeating instruction is generated, the counting signal Bank Counter is activated. <0> High level; repeat instruction and the counting signal Bank Counter set to high level. <0> After passing through the ninth AND gate A9 and the fourth NOR gate E4, the fourth NOR gate E4 outputs the repeat instruction Extra CMD to the set terminal of the fifth latch L5, triggering the Extra Refresh Flag signal to jump from low to high. Additionally, the falling edge of the Refresh Window signal triggers the Extra Refresh Flag signal to jump from high to low. This generates a segment of high-active Extra Refresh Flag signals.

[0158] On the other hand, for the first refresh instruction SB CMD <0> SB CMD <1> SB CMD <2> and SB CMD <3> The pulses other than repeated instructions (i.e., regular instructions) correspond to the counting signal Bank Counter that passes through the first delay unit H1. <0> Bank Counter <1> Bank Counter <2> and Bank Counter <3> The timing is low. After the regular instruction and the low-level counter signal Bank Counter pass through the ninth AND gate A9 and the fourth NOR gate E4, the signal output of the fourth NOR gate E4 remains low, meaning that the Extra CMD instruction will not be generated. Thus, the fifth latch L5 will not be triggered to switch the Extra Refresh Flag signal from low to high.

[0159] It is understood that the repeat command processing circuit 102 in this embodiment uses the level of the repeat instruction and the corresponding counting signal to trigger the generation of an additional refresh flag signal, which in turn triggers the address generator 103 to generate an additional address. In this way, the redundant repeat instructions in the first refresh instruction are used to refresh the additional address that needs to be refreshed, avoiding the waste of instructions and improving refresh efficiency.

[0160] In some embodiments of this application, such as Figure 32 As shown, the control signal generation circuit 303 includes: a tenth AND gate A10, a tenth inverter A10, and a fifth NOR gate E5. The inputs of the tenth AND gate A10 respectively receive multiple refresh window sub-signals ReW. The input of the tenth inverter D10 receives the address flag signal Addr Flag. The first input of the fifth NOR gate E5 is connected to the output of the tenth AND gate A10, the second input of the fifth NOR gate E5 is connected to the output of the tenth inverter D10, and the fifth NOR gate E5 outputs the address control signal Addr Ctrl.

[0161] In the embodiments of this application, Figure 33 Taking m=4 as an example, combined with Figure 32 and Figure 33 When the refresh control circuit performs the first refresh operation, each input of the tenth AND gate A10 receives multiple first refresh window sub-signals ReW. <0> ReW <1> ReW <2> and ReW <3> Then the signal ReW output by the tenth AND gate A10 <and>The signal is always low, so the address control signal Addr Ctrl and the address flag signal Addr Flag have the same waveform. In other words, the address flag signal Addr Flag retains its waveform after passing through the control signal generation circuit 303.

[0162] Combination Figure 32 and Figure 34 When the refresh control circuit performs a second refresh operation, each input of the tenth AND gate A10 receives the same second refresh window sub-signal ReW. <ab>Then the signal ReW output by the tenth AND gate A10 <and>With the second refresh window sub-signal ReW <ab>The waveforms are the same, but the signal ReW <and>The high-level region of the address flag signal (Addr Flag) overlaps with the high-level region of the address flag signal (Addr Flag). Thus, through the fifth NOR gate E5, the signal ReW... <and>The high-level region of the address flag signal Addr Flag can be shielded, so that the address control signal Addr Ctrl is always low. In other words, the address flag signal Addr Flag is shielded after passing through the control signal generation circuit 303.

[0163] It should be noted that, Figure 33 The multiple first refresh window sub-signals ReW shown <0> ReW <1> ReW <2> and ReW <3> and Figure 16 The multiple first refresh window sub-signals ReW shown <0> ReW <1> ReW <2> and ReW <3> The waveforms are the same, meaning that... Figure 33 Multiple first refresh window sub-signals ReW <0> ReW <1> ReW <2> and ReW <3> You can follow Figure 16 We can obtain this from examples. Figure 34 The second refresh window sub-signal ReW is shown. <ab>and Figure 17 The second refresh window sub-signal ReW is shown. <ab>The waveforms are the same, meaning that... Figure 34 The second refresh window sub-signal ReW <ab>You can follow Figure 17 We can obtain this from examples.

[0164] In some embodiments of this application, such as Figure 35 As shown, the address selection circuit 304 includes an adder 306 and a first data selector MUX1.

[0165] The input of adder 306 is connected to address counter 301. Adder 306 is used to obtain a first address from address counter 301 when the refresh control circuit receives a first refresh instruction, and then accumulates the first address to obtain a second address.

[0166] The first input terminal of the first data selector MUX1 is connected to the address counter 301, and the second input terminal of the first data selector MUX1 is connected to the adder 306. The control terminal of the first data selector MUX1 receives the address control signal Addr Ctrl, and the output terminal of the first data selector MUX1 serves as the output terminal of the address selection circuit 304. When the refresh control circuit receives a first refresh command, the first data selector MUX1 retrieves a first address from the address counter 301 and a second address from the adder 306, and in response to the address control signal Addr Ctrl, selects either the first address or the second address for output.

[0167] In this embodiment of the application, reference is made to Figure 35 and Figure 36 When the refresh control circuit receives the first refresh command, the address counter 301 receives the SameBank refresh clock signal SB CBR CLK, that is, it receives the first clock signal or the second clock signal.

[0168] When address counter 301 receives the first clock signal, since the first clock signal does not include a valid pulse, it will not trigger address counter 301 to change the first address. The address output signal Addr Counter Output represents the first address stored in address counter 301. (Refer to...) Figure 36 When address counter 301 receives the first clock signal, the first address n remains unchanged. The first address n is directly transmitted to the first input terminal (i.e., the input terminal marked "0") of the first data selector MUX1. Simultaneously, the first address n is transformed into the second address n+1 after passing through adder 306, and the second address n+1 is transmitted to the second input terminal (i.e., the input terminal marked "1") of the first data selector MUX1. The address Add_1 output by the first data selector MUX1 is controlled by the address control signal Addr Ctrl, see reference... Figure 36 The first data selector MUX1 alternately outputs n and n+1 based on the level of the address control signal AddrCtrl. That is, when the address control signal AddrCtrl is low, the first data selector MUX1 outputs the first address n input to its first input terminal; when the address control signal AddrCtrl is high, the first data selector MUX1 outputs the second address n+1 input to its second input terminal. Each set of n and n+1 output by the first data selector MUX1 is used to perform the first refresh operation on the corresponding SameBank in the Bank Group, until all Banks in the Bank Group have completed the first refresh operation, i.e., the number of first refresh operations reaches m (where m is the number of operations). Figure 36 (Taking m=4 as an example), during this process, the first address stored in the address counter 301 remains unchanged at n, that is, the address output signal AddrCounter Output remains unchanged at n until the number of the first refresh operation reaches m.

[0169] When the number of first refresh operations reaches m, meaning all banks have completed the first refresh operation of this round, address counter 301 receives the second clock signal. Since the second clock signal includes two valid pulses, address counter 301 will increment by 2 at the first address, thus changing the first address to the third address. At this point, all banks in the Bank Group have completed the previous round of first refresh operations. After the refresh control circuit receives the next round of first refresh instructions, it can perform the next round of first refresh operations according to the third address.

[0170] For example, if the current first address is 0000, incrementing the first address by 1 results in the second address 0001. This process is repeated for each bank in the first refresh operation (Same Bank Refresh). After all banks have completed this round of the first refresh operation, the address counter 301 is triggered by two pulses in the second clock signal, incrementing the first address by 2 and outputting 0010, before proceeding to the next round of the first refresh operation.

[0171] It should be noted that, Figure 36 and Figure 2 The waveforms of the first clock signal or the second clock signal shown are the same, that is to say, Figure 36 The first clock signal or the second clock signal shown can be transmitted through the clock signal. Figure 2 We can obtain this from examples.

[0172] Understandably, when performing the first refresh operation on a SameBank within a Bank Group, it refreshes two adjacent addresses (i.e., the first address and the second address) within that SameBank, keeping the first address unchanged throughout this process. Once all Banks in the Bank Group have completed their first refresh operations on the two adjacent addresses (i.e., after all Banks in the Bank Group have completed the previous round of first refresh operations), the first address is incremented by 2 to become the third address, which can then be used for the next round of first refresh operations. This ensures that the addresses in each Bank are refreshed sequentially, guaranteeing the continuity of refreshed addresses and preventing any addresses from being missed during the first refresh operation.

[0173] In this embodiment of the application, reference is made to Figure 35 The first data selector MUX1 is also used to obtain the fourth address or the fifth address from the address counter 301 when the refresh control circuit receives the second refresh instruction, and output the fourth address or the fifth address in response to the address control signal AddrCtrl.

[0174] refer to Figure 35 and Figure 37 When the refresh control circuit receives the second refresh command, the address counter 301 receives the third clock signal AB CBR CLK. Each valid pulse in the third clock signal AB CBR CLK triggers the address counter 301 to increment by 1 at the first address. The address output signal Addr Counter Output represents the first address stored in the address counter 301, as shown in the reference. Figure 37 The address output signal, Addr Counter Output, is incremented under the trigger of the third clock signal, ABCBR CLK. Figure 37 The third clock signal AB CBR CLK shown contains four cycles, with each cycle consisting of two valid pulses. Thus, in the first cycle, the first address n is triggered to change to the fourth address n+1 and the fifth address n+2; in the second cycle, n+2 is triggered to change to the fourth address n+3 and the fifth address n+4 as the first address, and so on.

[0175] Simultaneously, the address control signal Addr Ctrl remains low, so the first data selector MUX1 only outputs the fourth and fifth addresses received at its first input. In other words, the address Add_1 output by the first data selector MUX1 is consistent with the address output signal Addr Counter Output. This allows for a second refresh operation on all addresses in the Bank in address order, avoiding any omissions that prevent the second refresh operation from being performed.

[0176] It should be noted that, Figure 37 and Figure 5 The waveforms of the third clock signal AB CBR CLK shown are the same, that is, Figure 37 The third clock signal AB CBR CLK shown can be... Figure 5 We can obtain this from examples.

[0177] Understandably, when all banks in the Bank Group undergo the second refresh operation, the address counter 301 generates consecutive addresses (including the fourth and fifth addresses) based on the third clock signal AB CBR CLK, and outputs these consecutive addresses through the address selection circuit 304, so that each address in all banks completes the second refresh operation sequentially (i.e., All Bank Refresh). This ensures that the second refresh operation is performed on all addresses in the order they appear, guaranteeing the continuity of the refreshed addresses and preventing any addresses from being missed and thus avoiding the need for a second refresh operation. Furthermore, using a single address generator allows for flexible execution of both refresh operations, thereby improving the circuit's compatibility.

[0178] In some embodiments of this application, such as Figure 35 As shown, the additional address generation circuit 305 includes: an eleventh inverter D11, a second data selector MUX2, and an address delay module 307.

[0179] The input of the eleventh inverter D11 is connected to the output of the address selection circuit 304 (i.e., the output of the first data selector MUX1). The eleventh inverter D11 is used to obtain the target bit from the first address or the second address from the address selection circuit 304 when the refresh control circuit receives the first refresh command, and then invert the target bit in the first address or the second address before outputting it.

[0180] The first input of the second data selector MUX2 is connected to the output of the address selection circuit 304 (i.e., connected to the output of the first data selector MUX1), and the second input of the second data selector MUX2 is connected to the output of the eleventh inverter D11. The second data selector MUX2 is used to obtain the target bit from the first address or the second address from the address selection circuit 304 and output the target bit from the first address or the second address when the refresh control circuit receives the first refresh command and the control terminal of the second data selector MUX2 does not receive the Extra Refresh Flag signal. Alternatively, the second data selector MUX2 is used to obtain the inverted target bit from the first address or the second address from the eleventh inverter D11 and output the inverted target bit from the first address or the second address when the refresh control circuit receives the first refresh command and the control terminal of the second data selector MUX2 receives the Extra Refresh Flag signal.

[0181] The input terminal of the address delay module 307 is connected to the output terminal of the address selection circuit 304. The address delay module 307 is used to obtain other bits of the first address or the second address from the address selection circuit 304 when the refresh control circuit receives the first refresh command, and output the other bits of the first address or the second address after delaying them. The other bits are address bits other than the target bit.

[0182] In this embodiment of the application, reference is made to Figure 35 The address Add_1 received by the additional address generation circuit 305 from the address selection circuit 304 is divided into two parts for transmission. The target bit of address Add_1 is transmitted to the first input terminal (i.e., the input terminal marked "0") of the second data selector MUX2. The target bit of address Add_1 is inverted by the eleventh inverter D11 and transmitted to the second input terminal (i.e., the input terminal marked "1") of the second data selector MUX2. The other bits of address Add_1, excluding the target bit, are transmitted to the address delay module 307. In other words, the second data selector MUX2 selects the target bit of address Add_1 for output based on the Extra Refresh Flag signal, or it selects the inverted target bit of address Add_1 for output. Simultaneously, since the target bit of address Add_1 will be delayed in timing after passing through the second data selector MUX2 and the eleventh inverter D11, the other bits of address Add_1, excluding the target bit, need to pass through the address delay module 307 to match the timing.

[0183] In this embodiment of the application, combined with Figure 35 and Figure 38 When the refresh control circuit receives the first refresh command and performs the first refresh operation, if there is a duplicate command in the first refresh command, such as... Figure 38 The first refresh command in CMD <0> If a duplicate instruction exists, the Extra Refresh Flag signal is output high to the control terminal of the second data selector MUX2. At this time, the second data selector MUX2 selects the target bit of the inverted address Add_1 for output, thus the extra address generation circuit 305 outputs an extra address k or k+1 as the address to be refreshed. Correspondingly, when the refresh control circuit receives the first refresh instruction and performs the first refresh operation, if there is no duplicate instruction in the first refresh instruction, such as... Figure 38 First refresh command SB CMD <0> ~SB CMD <1> When the timing position corresponding to the regular pulse in the circuit is determined, the Extra Refresh Flag signal is output as low to the control terminal of the second data selector MUX2. At this time, the second data selector MUX2 selects the target bit of the address Add_1 that has not been inverted and outputs it. Thus, the extra address generation circuit 305 outputs the first address n or the second address n+1 as the address to be refreshed. That is, the extra address generation circuit 305 uses the address Add_1 output by the address selection circuit 304 as the address to be refreshed.

[0184] In this embodiment of the application, reference is made to Figure 35 When the refresh control circuit receives the second refresh command and performs the second refresh operation, the address Add_1 output by the address selection circuit 304 includes either the fourth address or the fifth address. At this time, the Extra Refresh Flag signal remains low. Therefore, the second data selector MUX2 selects the target bit of the uninverted address Add_1 for output. Consequently, the extra address generation circuit 305 outputs either the fourth address or the fifth address as the address to be refreshed. That is, the extra address generation circuit 305 uses the address Add_1 output by the address selection circuit 304 as the address to be refreshed.

[0185] Understandably, when the Extra Refresh Flag signal is triggered, the address generator 103 selects the target bit or its inverted form from address Add_1 via the second data selector MUX2 for output. This allows it to output an additional address when redundant instructions appear in the first refresh instruction. Thus, by utilizing the redundant instructions in the first refresh instruction to refresh additional addresses that require updating, it avoids wasting instructions and improves refresh efficiency.

[0186] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0187] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0188] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.< / ab> < / ab> < / ab> < / and> < / and> < / ab> < / and> < / ab> < / and> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab>

Claims

1. A refresh address generation circuit, characterized in that, The refresh address generation circuit includes: The refresh control circuit is used to receive multiple first refresh instructions in sequence and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal, where m is an integer greater than or equal to 1. A repeat command processing circuit, coupled to the refresh control circuit, is used to receive the first refresh command and output an additional refresh flag signal when a repeat command appears in the first refresh command. An address generator, coupled to the refresh control circuit and the repeat command processing circuit, and pre-stores a first address. When the first clock signal is received but the additional refresh flag signal is not received, the generator outputs an address to be refreshed in response to the first clock signal; or, when the additional refresh flag signal is received, the generator outputs an additional address in response to the additional refresh flag signal. The address to be refreshed includes either the first address or a second address, with the second address adjacent to the first address. The difference between the additional address and the first address is greater than a preset threshold. The refresh control circuit is also used to output a second clock signal when the number of the first refresh operation is equal to m. The address generator is further configured to receive the second clock signal and change the first address to a third address in response to the second clock signal.

2. The refresh address generation circuit according to claim 1, characterized in that, The refresh control circuit includes: A refresh window signal generation circuit is used to receive multiple first refresh instructions and refresh window reset signals, and generate a refresh window signal according to the multiple first refresh instructions and refresh window reset signals; wherein, the pulse duration of the refresh window signal is the window time for the refresh control circuit to perform one refresh operation, and the refresh window reset signal is used to reset the refresh window signal generation circuit after one refresh operation is completed; A clock pulse generation circuit, coupled to the refresh window signal generation circuit, is used to receive the refresh window signal and the first refresh instruction. Before the number of the first refresh instructions received by the clock pulse generation circuit is less than or equal to m and before the m-th first refresh operation ends, the first clock signal is generated; or, after the m-th first refresh operation ends, the second clock signal is generated.

3. The refresh address generation circuit according to claim 2, characterized in that, The clock pulse generation circuit includes: A counting circuit is configured to receive the first refresh instruction and a counting reset signal, count the first refresh instruction and output a counting signal, and reset according to the counting reset signal. A count reset signal generation circuit, coupled to the counting circuit and the refresh window signal generation circuit, is used to generate the count reset signal after the m-th first refresh operation is completed; The first pulse generation sub-circuit, coupled to the counting reset signal generation circuit, is used to generate the first clock signal according to the counting signal when the first refresh instruction is less than m, or to generate the second clock signal according to the counting reset signal when the first refresh instruction is equal to m.

4. The refresh address generation circuit according to claim 2, characterized in that, The refresh window signal generation circuit includes: Multiple refresh window sub-signal generation circuits are used to receive refresh window reset signals and receive multiple first refresh instructions in sequence, and output multiple refresh window sub-signals in sequence according to the multiple first refresh instructions and the refresh window reset signals. A refresh window sub-signal processing circuit, coupled to multiple refresh window sub-signal generation circuits, is used to sequentially receive multiple refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal.

5. The refresh address generation circuit according to claim 4, characterized in that, The refresh control circuit is further configured to receive a second refresh command and perform a second refresh operation; wherein, The multiple refresh window sub-signal generation circuits are also used to simultaneously receive the second refresh instruction and the refresh window reset signal, and generate the same multiple refresh window sub-signals one-to-one according to the second refresh instruction and the refresh window reset signal; The refresh window sub-signal processing circuit is further configured to receive multiple refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal.

6. The refresh address generation circuit according to claim 4, characterized in that, The refresh control circuit also includes: The second pulse generation sub-circuit, coupled to the refresh window signal generation circuit, is used to receive the refresh window signal and the address command signal, generate the first pulse of the third clock signal when the refresh control circuit starts to perform the first refresh operation or the second refresh operation, and output the second pulse of the third clock signal according to the first pulse of the address command signal, thereby outputting the third clock signal. An internal refresh window signal generation circuit receives the third clock signal and generates the internal refresh window signal based on the third clock signal; wherein, the first pulse of the internal refresh window signal is generated after the first pulse of the third clock signal and ends before the second pulse of the third clock signal is generated; the second pulse of the internal refresh window signal is generated after the second pulse of the third clock signal and ends before the pulse of the refresh window signal ends. The address command signal generation circuit is used to generate a first pulse and a second pulse of the address command signal based on the falling edge of the internal refresh window signal; wherein, the first pulse of the address command signal is used to generate the second pulse of the internal refresh window signal and the second pulse of the third clock signal; A refresh window reset signal generation circuit receives the internal refresh window signal and generates a pulse for the refresh window reset signal based on the falling edge of the second pulse of the internal refresh window signal.

7. The refresh address generation circuit according to claim 6, characterized in that, The refresh control circuit also includes: The signal selection circuit is coupled to the counting circuit, the first pulse generation sub-circuit, and the second pulse generation sub-circuit, and is used to receive the counting signal, the first clock signal, the second clock signal, and the third clock signal. When the refresh control circuit performs the first refresh operation, it outputs the first clock signal or the second clock signal according to the counting signal, or when the refresh control circuit performs the second refresh operation, it outputs the third clock signal according to the counting signal.

8. The refresh address generation circuit according to claim 6, characterized in that, The refresh control circuit also includes: The address flag signal generation circuit, coupled to the address command signal generation circuit and the refresh window signal generation circuit, is used to receive the address command signal and the refresh window signal, generate the rising edge of the address flag signal based on the first rising edge of the address command signal, and generate the falling edge of the address flag signal based on the falling edge of the refresh window signal.

9. The refresh address generation circuit according to claim 3, characterized in that, The repeat command processing circuit includes: A repeat instruction determination circuit, coupled to the counting circuit, is used to receive the first refresh instruction and the counting signal, not to output when no repeat instruction appears in the first refresh instruction, and to output the repeat instruction when a repeat instruction appears in the first refresh instruction. An additional refresh flag signal generation circuit, coupled to the repeat instruction determination circuit and the refresh window signal generation circuit, is used to receive the repeat instruction and the refresh window signal, and generate the additional refresh flag signal according to the repeat instruction and the refresh window signal; wherein, the rising edge of the additional refresh flag signal is generated according to the valid pulse of the repeat instruction, and the falling edge of the additional refresh flag signal is generated according to the falling edge of the refresh window signal.

10. The refresh address generation circuit according to claim 7, characterized in that, The address generator includes: An address counter, coupled to the signal selection circuit, is used to pre-store the first address, change the first address to a third address according to the second clock signal, or change the first address and output a fourth and a fifth address according to the third clock signal; the first address, the fourth address, and the fifth address are three consecutive addresses. The address processing circuit, coupled to the address counter, the refresh window sub-signal generation circuit, and the repeat command processing circuit, is used to receive the address flag signal and obtain the first address when the refresh control circuit performs the first refresh operation. If the additional refresh flag signal is not received, the first address or the second address is output according to the address flag signal. If the additional refresh flag signal is received, the additional address is output within the window time of the additional refresh flag signal. The address processing circuit is further configured to, when the refresh control circuit performs the second refresh operation, sequentially acquire the fourth address and the fifth address, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals.

11. The refresh address generation circuit according to claim 10, characterized in that, The address processing circuit includes: A control signal generation circuit, coupled to the refresh window sub-signal generation circuit and the address flag signal generation circuit, is used to receive multiple refresh window sub-signals and the address flag signal, and generate an address control signal based on the multiple refresh window signals and the address flag signal; The address selection circuit, coupled to the address counter and the control signal generation circuit, is used to output the first address before the rising edge of the address control signal arrives when the refresh control circuit receives the first refresh instruction, or to accumulate the first address after the rising edge of the address control signal arrives to obtain and output the second address; the address selection circuit is also used to output the fourth address and the fifth address sequentially in response to the address control signal when the refresh control circuit receives the second refresh instruction. An additional address generation circuit, coupled to the address selection circuit, is used to receive and output the first address and the second address when the refresh control circuit performs the first refresh operation and the additional address generation circuit does not receive the additional refresh flag signal; or, when the refresh control circuit performs the first refresh operation and the additional address generation circuit receives the additional refresh flag signal, it receives the first address and the second address, inverts the target bit in the first address and the second address according to the additional refresh flag signal, and obtains and outputs the additional address, wherein the target bit is any address bit in the first address and the second address that is higher than a preset bit; or, when the refresh control circuit performs the second refresh operation, it receives and outputs the fourth address or the fifth address.

12. The refresh address generation circuit according to claim 3, characterized in that, The counting circuit includes: Multiple first inverters, the input terminals of the multiple first inverters sequentially receive multiple first refresh commands; The second inverter receives the count reset signal at its input terminal. Multiple first latches are provided, with the set terminals of the multiple first latches sequentially connected to the output terminals of the multiple first inverters, and the reset terminals of the multiple first latches connected to the output terminals of the second inverters. The multiple first latches sequentially output multiple counting signals.

13. The refresh address generation circuit according to claim 3, characterized in that, The counting reset signal generation circuit includes: A first AND gate, the input of which receives a plurality of the counting signals; The third inverter receives the refresh window signal at its input terminal. The second AND gate has its input terminals connected to the output terminals of the first AND gate and the third inverter, respectively. A first delay unit, the input of which is connected to the output of the second AND gate; A fourth inverter, the input of which is connected to the output of the first delay unit; The third AND gate has its input terminals connected to the output terminals of the second AND gate and the fourth inverter, respectively, and outputs the count reset signal.

14. The refresh address generation circuit according to claim 3, characterized in that, The first pulse generation sub-circuit includes: The second delay unit receives the count reset signal at its input terminal; A third delay unit, wherein the input terminal of the third delay unit is connected to the output terminal of the second delay unit; The first OR gate has its input terminals connected to the output terminals of the second delay unit and the third delay unit, respectively, and outputs either the first clock signal or the second clock signal.

15. The refresh address generation circuit according to claim 5, characterized in that, The refresh window sub-signal includes: a first refresh window sub-signal or a second refresh window signal; each refresh window sub-signal generation circuit includes: The first NOR gate receives the corresponding first refresh instruction at its first input terminal when the refresh control circuit performs the first refresh operation, or receives the second refresh instruction at its second input terminal when the refresh control circuit performs the second refresh operation. The second latch has its set terminal connected to the output terminal of the first NOR gate, and its reset terminal receiving the refresh window reset signal. When the refresh control circuit performs the first refresh operation, the second latch outputs the corresponding first refresh window sub-signal; or, when the refresh control circuit performs the second refresh operation, the second latch outputs the corresponding second refresh window sub-signal.

16. The refresh address generation circuit according to claim 15, characterized in that, The refresh window sub-signal processing circuit includes: The second OR gate receives multiple first refresh window sub-signals at its input terminal when the refresh control circuit performs the first refresh operation, or receives the same multiple second refresh window sub-signals at its input terminal when the refresh control circuit performs the second refresh operation; the second OR gate outputs the refresh window signal.

17. The refresh address generation circuit according to claim 6, characterized in that, The second pulse generation sub-circuit includes: The fourth delay unit receives the refresh window signal at its input. The fifth inverter, the input of which is connected to the output of the fourth delay unit; The fourth AND gate, the first input of which receives the refresh window signal, and the second input of which is connected to the output of the fifth inverter; The sixth inverter receives an address flag signal at its input terminal; The fifth AND gate has its first input connected to the output of the sixth inverter, and its second input receives the address command signal. The second NOR gate, the input of the second NOR gate is connected to the output of the fourth AND gate and the output of the fifth AND gate respectively; The seventh inverter has its input connected to the output of the second NOR gate, and outputs the third clock signal.

18. The refresh address generation circuit according to claim 6, characterized in that, The address command signal generation circuit includes: The eighth inverter receives the internal refresh window signal at its input terminal; The fifth delay unit, whose input is connected to the input of the eighth inverter, receives the internal refresh window signal; The sixth AND gate, whose input terminals are connected to the output terminals of the eighth inverter and the fifth delay unit respectively, outputs the address command signal.

19. The refresh address generation circuit according to claim 18, characterized in that, The internal refresh window signal generation circuit includes: The third latch has a set terminal that receives the third clock signal, a reset terminal that is connected to the output terminal of the eighth inverter, and an output of the internal refresh window signal.

20. The refresh address generation circuit according to claim 6, characterized in that, The refresh window reset signal generation circuit includes: The sixth delay unit receives the address flag signal at its input terminal; The seventh AND gate has its first input connected to the output of the sixth delay, and its second input receiving the internal refresh window signal. The seventh delay unit has its input connected to the output of the seventh AND gate, and outputs the refresh window reset signal.

21. The refresh address generation circuit according to claim 7, characterized in that, The signal selection circuit includes: The third NOR gate receives multiple counting signals at its input terminals. The third OR gate has a first input terminal that receives the first clock signal or the second clock signal, and a second input terminal that receives the third clock signal. The eighth AND gate has its first input connected to the output of the third NOR gate, and its second input connected to the output of the third OR gate. The eighth AND gate outputs the first clock signal, the second clock signal, or the third clock signal.

22. The refresh address generation circuit according to claim 8, characterized in that, The address flag signal generation circuit includes: The ninth inverter receives the address command signal at its input terminal; The fourth latch has its set terminal connected to the output terminal of the ninth inverter, its reset terminal receiving the refresh window signal, and its outputting the address flag signal.

23. The refresh address generation circuit according to claim 9, characterized in that, The repeat instruction determination circuit includes: Multiple eighth delay units, the input terminals of which sequentially receive multiple counting signals; Multiple ninth AND gates, the first input terminals of the multiple ninth AND gates are sequentially connected to the output terminals of the multiple eighth delays, and the second input terminals of the multiple ninth AND gates sequentially receive multiple first refresh commands; The fourth NOR gate has its input terminals connected to the output terminals of multiple ninth AND gates, and outputs the repeat instruction.

24. The refresh address generation circuit according to claim 9, characterized in that, The additional refresh flag signal generation circuit includes: The fifth latch receives the repeat instruction at its set terminal, receives the refresh window signal at its reset terminal, and outputs the additional refresh flag signal.

25. The refresh address generation circuit according to claim 11, characterized in that, The control signal generation circuit includes: The tenth AND gate, whose input terminals respectively receive multiple refresh window sub-signals; The tenth inverter receives the address flag signal at its input terminal; The fifth NOR gate has its first input connected to the output of the tenth AND gate, and its second input connected to the output of the tenth inverter. The fifth NOR gate outputs the address control signal.

26. The refresh address generation circuit according to claim 11, characterized in that, The address selection circuit includes: an adder and a first data selector; The input terminal of the adder is connected to the address counter; the adder is used to obtain the first address when the refresh control circuit receives the first refresh instruction, and to accumulate the first address to obtain the second address; The first input terminal of the first data selector is connected to the address counter, the second input terminal of the first data selector is connected to the adder, the control terminal of the first data selector receives the address control signal, and the output terminal of the first data selector serves as the output terminal of the address selection circuit. The first data selector is configured to, when the refresh control circuit receives the first refresh instruction, obtain the first address from the address counter and the second address from the adder, and, in response to the address control signal, select the first address or the second address for output; The first data selector is further configured to, when the refresh control circuit receives the second refresh instruction, obtain the fourth address or the fifth address from the address counter, and output the fourth address or the fifth address in response to the address control signal.

27. The refresh address generation circuit according to claim 26, characterized in that, The additional address generation circuit includes: an eleventh inverter, a second data selector, and an address delay module; The input terminal of the eleventh inverter is connected to the output terminal of the address selection circuit; the eleventh inverter is used to obtain the target bit in the first address or the second address from the address selection circuit when the refresh control circuit receives the first refresh instruction, and then invert the target bit in the first address or the second address and output it. The first input terminal of the second data selector is connected to the output terminal of the address selection circuit, and the second input terminal of the second data selector is connected to the output terminal of the eleventh inverter. The second data selector is configured to, when the refresh control circuit receives the first refresh instruction and the control terminal of the second data selector does not receive the additional refresh flag signal, obtain the target bit from the first address or the second address from the address selection circuit and output the target bit from the first address or the second address; or, when the refresh control circuit receives the first refresh instruction and the control terminal of the second data selector receives the additional refresh flag signal, obtain the inverted target bit from the first address or the second address from the eleventh inverter and output the inverted target bit from the first address or the second address. The input terminal of the address delay module is connected to the output terminal of the address selection circuit; the address delay module is used to obtain other bits of the first address or the second address from the address selection circuit when the refresh control circuit receives the first refresh instruction, and output the other bits of the first address or the second address after delay; the other bits are address bits other than the target bit.

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