receiving circuit and memory

Abstract

This disclosure provides a receiving circuit and a memory. The receiving circuit includes: an input buffer configured to receive a first input signal and a second input signal, compare the first input signal and the second input signal, and output a first output signal and a second output signal. In differential mode, the first input signal and the second input signal are respectively a first signal and a second signal; in single-ended mode, the first input signal is one of the first signal and the second signal, and the second input signal is a reference voltage signal. The first signal and the second signal are complementary. A conversion module configured to receive the first output signal and the second output signal and amplify the voltage difference between the first output signal and the second output signal to output a first internal signal and a second internal signal. This disclosure at least helps to reduce the power consumption and complexity of the receiving circuit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a receiving circuit and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] DRAM can include Double Data Rate (DDR), GDDR (Graphics Double Data Rate) DRAM, and Low Power Double Data Rate (LPDDR). As DRAM applications expand to more fields, such as the increasing use of DRAM in mobile applications, users are demanding higher power consumption specifications from DRAM users. Summary of the Invention

[0004] This disclosure provides a receiving circuit and a memory, which at least helps to reduce the power consumption and complexity of the receiving circuit.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a receiving circuit, including: an input buffer configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal, wherein, in differential mode, the first input signal and the second input signal are respectively a first signal and a second signal, and in single-ended mode, the first input signal is one of the first signal and the second signal, the second input signal is a reference voltage signal, and the first signal and the second signal are complementary; and a conversion module configured to receive the first output signal and the second output signal and amplify the voltage difference between the first output signal and the second output signal to output a first internal signal and a second internal signal.

[0006] In some embodiments, the receiving circuit further includes: a selection module, which receives an original first signal, an original second signal, and an original reference voltage signal, and is configured to provide the first input signal and the second input signal to the input buffer in response to a mode selection signal, wherein the mode selection signal is used to characterize the single-ended mode or the differential mode, the first signal corresponds to the original first signal, the second signal corresponds to the original second signal, and the original reference voltage signal corresponds to the reference voltage signal.

[0007] In some embodiments, the selection module includes: a first selection unit and a second selection unit, wherein one of the first selection unit and the second selection unit receives the original first signal and the original reference voltage signal, and the other receives the original second signal and the original reference voltage signal; in the single-ended mode, one of the first selection unit and the second selection unit outputs the first signal or the second signal in response to the mode selection signal, and the other outputs the reference voltage signal in response to the mode selection signal; in the differential mode, one of the first selection unit and the second selection unit outputs the first signal in response to the mode selection signal, and the other outputs the second signal in response to the mode selection signal.

[0008] In some embodiments, the input buffer includes: a current control module configured to provide current to a first node in response to a bias voltage signal; an input module and a load module connected to the input module, the input module being connected to the first node and the input module being connected to the load module via a second node and a third node; wherein the input module receives a first input signal and a second input signal, the second node outputs the first output signal, and the third node outputs the second output signal.

[0009] In some embodiments, the current control module is configured to adjust the current supplied to the first node in response to the bias voltage signal, such that the current supplied to the first node in the single-ended mode is less than the current supplied to the first node in the differential mode.

[0010] In some embodiments, the current control module includes: a first control unit connected to the first node and configured to provide a first current to the first node in response to the bias voltage signal; and a second control unit connected to the first node and configured to provide a second current to the first node in response to a control signal and the bias voltage signal; wherein, in the single-ended mode, the first control unit is turned on and the second control unit is not turned on, and in the differential mode, both the first control unit and the second control unit are turned on.

[0011] In some embodiments, the first control unit includes: a first PMOS transistor, the gate of which receives an enable signal, and the source of which is connected to a power supply voltage; a second PMOS transistor and a third PMOS transistor, the sources of which are both connected to the drain of the first PMOS transistor, the drains of which are both connected to the first node, and the gates of which receive the bias voltage signal.

[0012] In some embodiments, the second control unit includes: a fourth PMOS transistor, the gate of which receives the control signal, and the source of which is connected to a power supply voltage; a fifth PMOS transistor and a sixth PMOS transistor, the sources of which are both connected to the drain of the fourth PMOS transistor, the drains of which are both connected to the first node, and the gates of which receive the bias voltage signal.

[0013] In some embodiments, the input module includes: a seventh PMOS transistor, the gate of which receives the first input signal, the source of which is connected to the first node, and the drain of which is connected to the second node; and an eighth PMOS transistor, the gate of which receives the second input signal, the source of which is connected to the first node, and the drain of which is connected to the third node.

[0014] In some embodiments, the load module includes: a first load unit connected between the second node and ground, configured such that the equivalent resistance value of the first load unit in the single-ended mode is greater than the equivalent resistance value of the first load unit in the differential mode; and a second load unit connected between the third node and ground, configured such that the equivalent resistance value of the second load unit in the single-ended mode is greater than the equivalent resistance value of the second load unit in the differential mode.

[0015] In some embodiments, the first load unit includes: a first resistor connected between the second node and the fourth node; and a first adjustable load connected between the fourth node and the ground terminal, configured to adjust the equivalent resistance value of the first adjustable load in response to an adjustment signal, wherein the equivalent resistance value of the first adjustable load in the single-ended mode is greater than the equivalent resistance value of the first adjustable load in the differential mode; the second load unit includes: a second resistor connected between the third node and the fifth node; and a second adjustable load connected between the fifth node and the ground terminal, configured to adjust the equivalent resistance value of the second adjustable load in response to the adjustment signal, wherein the equivalent resistance value of the second adjustable load in the single-ended mode is greater than the equivalent resistance value of the second adjustable load in the differential mode.

[0016] In some embodiments, the first adjustable load includes: a third resistor connected between the fourth node and ground; a first MOSFET, with a first end connected to the fourth node and a second end connected to ground, and a control terminal of the first MOSFET receiving the adjustment signal, wherein in the single-ended mode, the first MOSFET is turned off in response to the adjustment signal, and in the differential mode, the first MOSFET is turned on in response to the adjustment signal.

[0017] In some embodiments, the second adjustable load includes: a fourth resistor connected between the fifth node and the ground terminal; a second MOSFET, the first end of the second MOSFET being connected to the fifth node, the second end of the second MOSFET being connected to the ground terminal, and the control terminal of the second MOSFET receiving the adjustment signal, wherein, in the single-ended mode, the second MOSFET is turned off in response to the adjustment signal, and in the differential mode, the second MOSFET is turned on in response to the adjustment signal.

[0018] In some embodiments, the conversion module includes: an amplification unit configured to amplify the voltage difference between the first output signal and the second output signal; and a conversion unit configured to perform level logic conversion on the first output signal and the second output signal amplified by the amplification unit, and output the first internal signal and the second internal signal.

[0019] In some embodiments, the amplification unit is further configured to adjust a first operating current of the amplification unit in response to a first bias signal, such that the first operating current in the single-ended mode is less than the first operating current in the differential mode.

[0020] In some embodiments, the conversion unit is further configured to adjust the second operating current of the conversion unit in response to a second bias signal, such that the second operating current in the single-ended mode is less than the second operating current in the differential mode.

[0021] According to some embodiments of this disclosure, another aspect of this disclosure also provides a memory including a receiving circuit as described in any of the foregoing claims.

[0022] The technical solutions provided in this disclosure have at least the following advantages:

[0023] The input buffer can utilize both the first and second signals in differential mode, or it can utilize a reference voltage signal and one of the first and second signals in single-ended mode. In other words, the same input buffer can be used in both differential and single-ended modes, which helps reduce the complexity and layout area of ​​the receiving circuit. Furthermore, in single-ended mode, the input buffer only receives one of the first and second signals, and the other received signal is the reference voltage signal, which reduces the operating current in the receiving circuit, thereby helping to reduce the power consumption of the receiving circuit. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A functional block diagram of a receiving circuit provided in an embodiment of this disclosure;

[0026] Figure 2 This is a functional block diagram of a receiving circuit;

[0027] Figures 3 to 6 Four other functional block diagrams of the receiving circuit provided in one embodiment of this disclosure;

[0028] Figure 7 and Figure 8 Schematic diagrams of two circuit structures of the input buffer in a receiving circuit provided in an embodiment of this disclosure;

[0029] Figures 9 to 11The present invention discloses three circuit structure diagrams of the load module in a receiving circuit according to an embodiment of the present invention. Detailed Implementation

[0030] Analysis revealed that the receiving circuit operates in either differential or single-ended mode depending on actual needs. However, the receiving circuit creates separate clock paths for differential and single-ended modes, meaning that the clock signal received by the receiving circuit in differential mode uses a different clock path than the clock signal received by the receiving circuit in single-ended mode.

[0031] refer to Figure 2 , Figure 2 This is a functional block diagram of a receiving circuit. The receiving circuit includes two input buffers: a differential input buffer 11 and a single-ended input buffer 12, as well as a conversion module 13. When the receiving circuit operates in differential mode, the differential input buffer 11 is active, while the single-ended input buffer 12 is inactive. The differential input buffer 11 receives a first input signal Dqs_t and a second input signal Dqs_c through a first clock path and outputs them to the conversion module 13. The conversion module 13 then outputs a first internal signal Dqst and a second internal signal Dqsc. When the receiving circuit operates in single-ended mode, the single-ended input buffer 12 is active, while the differential input buffer 11 is inactive. The single-ended input buffer 12 receives either the first input signal Dqs_t or the second input signal Dqs_c through a second clock path, and also receives a reference voltage signal vref, which is output to the conversion module 13. The conversion module 13 then outputs the first internal signal Dqst and the second internal signal Dqsc.

[0032] As can be seen, the differential input buffer 11 uses the first clock path when receiving the first input signal Dqs_t and the second input signal Dqs_c, while the single-ended input buffer 12 uses the second clock path when receiving either the first input signal Dqs_t or the second input signal Dqs_c. Since the first and second clock paths are different, interference will occur between them when the receiving circuit switches between differential and single-ended modes. This will cause glitches in the first input signal Dqs_t and / or the second input signal Dqs_c received by the input buffers, reducing the accuracy of the first internal signal Dqst and the second internal signal Dqsc output by the conversion module 13. Furthermore, designing two types of input buffers in the receiving circuit is not conducive to simplifying the circuit layout, increases its complexity, and does not save on overall power consumption.

[0033] This disclosure provides a receiving circuit and a memory. In the receiving circuit, the input buffer can operate in differential mode using both a first signal and a second signal, or in single-ended mode using a reference voltage signal and one of the first and second signals. That is, the same input buffer can be used in both differential and single-ended modes, which helps reduce the complexity and layout area of ​​the receiving circuit. Furthermore, in single-ended mode, the input buffer only receives one of the first and second signals, and the other received signal is the reference voltage signal, which reduces the operating current in the receiving circuit, thereby helping to reduce the power consumption of the receiving circuit.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] This disclosure provides a receiving circuit according to one embodiment. The receiving circuit provided by this disclosure will be described in detail below with reference to the accompanying drawings. Figure 1 , Figures 3 to 6 Five functional block diagrams of a receiving circuit provided in one embodiment of this disclosure; Figure 7 and Figure 8 Schematic diagrams of two circuit structures of the input buffer in a receiving circuit provided in an embodiment of this disclosure; Figures 9 to 11 The diagram shows three circuit structures of the load module in the receiving circuit provided in one embodiment of this disclosure.

[0036] Reference Figure 1 and Figure 3The receiving circuit includes: an input buffer 101 configured to receive a first input signal input1 and a second input signal input2, compare the first input signal input1 and the second input signal input2, and output a first output signal out1_p and a second output signal out1_n. In differential mode, the first input signal input1 and the second input signal input2 are respectively a first signal In1 and a second signal In2. In single-ended mode, the first input signal input1 is one of the first signal In1 and the second signal In2, and the second input signal input2 is a reference voltage signal vref. The first signal In1 and the second signal In2 are complementary. A conversion module 102 configured to receive the first output signal out1_p and the second output signal out1_n and amplify the voltage difference between the first output signal out1_p and the second output signal out1_n to output a first internal signal out2_p and a second internal signal out2_n.

[0037] As can be seen, in the receiving circuit provided in this embodiment, an input buffer 101 that can be used in both differential mode and single-ended mode is designed. On the one hand, this helps to reduce the complexity and layout area of ​​the receiving circuit. On the other hand, the input buffer 101 receives the first input signal input1 and the second input signal input2 through the same transmission path in both differential mode and single-ended mode. This helps to reduce the interference to the first input signal input1 and the second input signal input2 when the receiving circuit switches between differential mode and single-ended mode, thereby improving the accuracy of the first internal signal out2_p and the second internal signal out2_n output by the conversion module 102. Furthermore, it simplifies the complexity of the receiving circuit. Using only one input buffer 101 helps to reduce the operating current of the receiving circuit, thereby helping to reduce the overall power consumption of the receiving circuit.

[0038] In some embodiments, the first signal In1 and the second signal In2 can be a clock signal and a complementary clock signal, respectively. When the receiving circuit operates in differential mode, it is typically used to receive higher frequency signals for better performance; when the receiving circuit operates in single-ended mode, it receives only one clock signal with a lower frequency and a reference voltage signal vref for lower frequency operation to save power.

[0039] In some embodiments, reference Figure 5The input buffer 101 may include: a current control module 111 configured to provide current to a first node net1 in response to a bias voltage signal bias0; an input module 112 and a load module 113 connected to the input module 112, wherein the input module 112 is connected to the first node net1 and to the load module 113 via a second node net2 and a third node net3; wherein the input module 112 receives a first input signal input1 and a second input signal input2, and the second node net2 outputs a first output signal out1_p (see reference). Figure 1 The third node, net3, outputs the second output signal out1_n (see reference). Figure 1 ).

[0040] In some embodiments, continue to refer to Figure 5 The current control module 111 can be configured to adjust the current supplied to the first node net1 in response to the bias voltage signal bias0, so that the current supplied to the first node net1 in single-ended mode is less than the current supplied to the first node net1 in differential mode. This helps to reduce the operating current in the single-ended mode of the receiving circuit, thereby reducing the overall power consumption of the receiving circuit.

[0041] In one example, refer to Figure 7 The current control module 111 may include: a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receiving an enable signal EnN, and the source of the first PMOS transistor MP1 connected to the power supply voltage Vccl; a second PMOS transistor MP2 and a third PMOS transistor MP3, the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 being connected to the drain of the first PMOS transistor MP1, the drains of the second PMOS transistor MP2 and the third PMOS transistor MP3 being connected to the first node net1, and the gates of the second PMOS transistor MP2 and the third PMOS transistor MP3 receiving a bias voltage signal bias0. Thus, the control enable signal EnN can be used as a master switch to determine whether the input buffer 101 is working. For example, when the control enable signal EnN is low, the first PMOS transistor MP1 is turned on, allowing the input buffer 101 to work; when the control enable signal EnN is high, the first PMOS transistor MP1 is turned off. At this time, regardless of whether the bias voltage signal bias0 is high or low, there is no current path in the input buffer 101, that is, the input buffer 101 will not work.

[0042] Furthermore, by controlling the level of the bias voltage signal bias0 to adjust the conduction levels of the second PMOS transistor MP2 and the third PMOS transistor MP3, it is beneficial to ensure that the current supplied to the first node net1 by the current control module 111 in single-ended mode is less than the current supplied to the first node net1 in differential mode. For example, in differential mode, the bias voltage signal bias0 is controlled at a first level value, while in single-ended mode, the bias voltage signal bias0 is controlled at a second level value, and the second level value is greater than the first level value. Thus, the conduction levels of the second PMOS transistor MP2 and the third PMOS transistor MP3 in differential mode are greater than their conduction levels in single-ended mode, resulting in a greater current at the first node net1 in differential mode than in single-ended mode.

[0043] In some embodiments, reference Figure 8 The current control module 111 may include: a first control unit 1111, connected to the first node net1, configured to turn on in response to a bias voltage signal bias0 to provide a first current to the first node net1; and a second control unit 1112, connected to the first node net1, configured to turn on in response to a control signal SeEn and a bias voltage signal bias0 to provide a second current to the first node net1; wherein, in single-ended mode, the first control unit 1111 is turned on and the second control unit 1112 is not turned on, and in differential mode, both the first control unit 1111 and the second control unit 1112 are turned on. As can be seen, in single-ended mode, only one current path of the first control unit 1111 is turned on to provide current to the first node net1, that is, the current at the first node net1 is the first current. In differential mode, there are two parallel current paths of the first control unit 1111 and the second control unit 1112 turned on to provide current to the first node net1, that is, the current at the first node net1 is the sum of the first current and the second current, so that the current at the first node net1 in single-ended mode is less than the current at the first node net1 in differential mode.

[0044] In some embodiments, continue to refer to Figure 8The first control unit 1111 may include: a first PMOS transistor MP1, the gate of the first PMOS transistor MP1 receiving an enable signal EnN, and the source of the first PMOS transistor MP1 connected to a power supply voltage Vccl; a second PMOS transistor MP2 and a third PMOS transistor MP3, the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 being connected to the drain of the first PMOS transistor MP1, the drains of the second PMOS transistor MP2 and the third PMOS transistor MP3 being connected to a first node net1, and the gates of the second PMOS transistor MP2 and the third PMOS transistor MP3 receiving a bias voltage signal bias0. The control enable signal EnN can be used as a master switch to determine whether the first control unit 1111 is working. For example, when the control enable signal EnN is low, the first PMOS transistor MP1 is turned on, allowing the first control unit 1111 to work. When the control enable signal EnN is high, the first PMOS transistor MP1 is turned off. At this time, regardless of whether the bias voltage signal bias0 is high or low, there is no current path in the first control unit 1111, meaning that the first control unit 1111 will not work.

[0045] Among them, continue to refer to Figure 8 The second control unit 1112 may include: a fourth PMOS transistor MP4, the gate of which receives a control signal SeEn, and the source of which is connected to a power supply voltage Vccl; a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, the sources of which are both connected to the drain of the fourth PMOS transistor MP4, the drains of which are both connected to the first node net1, and the gates of which are both received a bias voltage signal bias0.

[0046] In one example, in single-ended mode, the enable signal EnN is low, turning on the first PMOS transistor MP1. The bias voltage signal bias0 is at a level that allows the second PMOS transistors MP2 and MP3 to conduct. The conduction level of the second and third PMOS transistors MP2 and MP3 can be controlled by adjusting the bias voltage signal bias0, thus controlling the current flowing through them. The control signal SeEn is high, turning off the fourth PMOS transistor MP4. Therefore, regardless of the bias voltage signal bias0, no current flows through the fifth and sixth PMOS transistors MP5 and MP6, meaning the second control unit 1112 is not turned on, and the current at the first node net1 is provided solely by the first control unit 1111. In differential mode, the enable signal EnN is low, turning on the first PMOS transistor MP1. The bias voltage signal bias0 is high, turning on the second PMOS transistor MP2 and MP3 to conduct. S0 is at a level that enables the second PMOS transistor MP2 and the third PMOS transistor MP3 to conduct. The conduction level of the second PMOS transistor MP2 and the third PMOS transistor MP3 can be controlled by adjusting the level of the bias voltage signal bias0, thereby controlling the magnitude of the current flowing through the second PMOS transistor MP2 and the third PMOS transistor MP3. The control signal SeEn is also at a low level, enabling the fourth PMOS transistor MP4 to conduct. The bias voltage signal bias0 is also at a level that enables the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 to conduct. The conduction level of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 can be controlled by adjusting the level of the bias voltage signal bias0, thereby controlling the magnitude of the current flowing through the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6. That is, both the first control unit 1111 and the second control unit 1112 are conducting. The current at the first node net1 is the sum of the first current and the second current.

[0047] In some embodiments, reference Figure 7 and Figure 8 The input module 112 may include: a seventh PMOS transistor MP7, the gate of which receives the first input signal input1, the source of which is connected to the first node net1, and the drain of which is connected to the second node net2; and an eighth PMOS transistor MP8, the gate of which receives the second input signal input2, the source of which is connected to the first node net1, and the drain of which is connected to the third node net3.

[0048] It should be noted that the level changes of the first input signal input1 and the second input signal input2 are asynchronous. This causes the turn-on time of the seventh PMOS transistor MP7, which receives the first input signal input1, to differ from the turn-on time of the eighth PMOS transistor MP8, which receives the second input signal input2. Furthermore, at the same time, the conduction degree of the seventh PMOS transistor MP7 differs from that of the eighth PMOS transistor MP8. Understandably, because the conduction degree of the seventh PMOS transistor MP7 differs from that of the eighth PMOS transistor MP8, their current shunting capabilities at the first node net1 also differ, resulting in a difference between the voltage at the second node net2 and the voltage at the third node net3.

[0049] In one example, when the level of the first input signal input1 is higher than the level of the second input signal input2, the conduction degree of the eighth PMOS transistor MP8 is greater than that of the seventh PMOS transistor MP7. This causes more current to flow into the path of the eighth PMOS transistor MP8 at the first node net1, making the current at the third node net3 greater than the current at the second node net2. The voltage at the third node net3 is higher than the voltage at the second node net2, resulting in a high level of the second output signal out1_n output by the third node net3 and a low level of the first output signal out1_p output by the second node net2. This makes the first output signal out1_p and the second output signal out1_n complementary.

[0050] In some embodiments, reference Figure 7 and Figure 8The load module 113 may include: a first load unit 1131, connected between the second node net2 and ground, configured such that the equivalent resistance value of the first load unit 1131 in single-ended mode is greater than the equivalent resistance value of the first load unit 1131 in differential mode; and a second load unit 1132, connected between the third node net3 and ground, configured such that the equivalent resistance value of the second load unit 1132 in single-ended mode is greater than the equivalent resistance value of the second load unit 1132 in differential mode. It is evident that the equivalent resistance value of both the first load unit 1131 and the second load unit 1132 in single-ended mode is greater than the equivalent resistance value in differential mode. Since the current at the first node net1 in single-ended mode is less than the current at the first node net1 in differential mode, and the current at the first node net1 is the sum of the current at the second node net2 and the current at the third node net3, under the premise that the conduction degree of the eighth PMOS transistor MP8 is different from that of the seventh PMOS transistor MP7, the absolute value of the difference between the current at the second node net2 and the current at the third node net3 in single-ended mode is the first difference value, and the absolute value of the difference between the current at the second node net2 and the current at the third node net3 in differential mode is the second difference value. Therefore, the first difference value is smaller than the second difference value.

[0051] Thus, when the equivalent resistance values ​​of both the first load unit 1131 and the second load unit 1132 in single-ended mode are greater than those in differential mode, the larger equivalent resistance allows for a larger voltage difference between the second node net2 and the third node net3, even when the difference between the current at the second node net2 and the current at the third node net3 is small in single-ended mode. This results in a larger voltage swing at the second node net2 and the third node net3 in single-ended mode.

[0052] This can be understood as follows: the product of the equivalent resistance of the first load unit 1131 and the current flowing through the second node net2 is the first product; the product of the equivalent resistance of the second load unit 1132 and the current flowing through the third node net3 is the second product; and the difference between the voltage at the second node net2 and the voltage at the third node net3 is the difference between the first product and the second product. In one example, the equivalent resistance of the first load unit 1131 is equal to the equivalent resistance of the second load unit 1132, then the difference between the voltage at the second node net2 and the voltage at the third node net3 is the product of that equivalent resistance and the difference between the current flowing through the second node net2 and the current at the third node net3.

[0053] In some embodiments, reference Figure 9The first load unit 1131 may include a first sub-resistor R1 and a second sub-resistor R2 connected in series, and a third sub-resistor R3 and a fourth sub-resistor R4 connected in parallel. One end of the first sub-resistor R1 is connected to the second node net2, and the other end of the first sub-resistor R1 is connected to one end of the second sub-resistor R2. The other end of the second sub-resistor R2 is connected to one end of both the third sub-resistor R3 and the fourth sub-resistor R4. The other end of the third sub-resistor R3 is connected to the other end of the fourth sub-resistor R4. The second load unit 1132 may include a fifth sub-resistor R5 and a sixth sub-resistor R6 connected in series, and a seventh sub-resistor R7 and an eighth sub-resistor R8 connected in parallel. One end of the fifth sub-resistor R5 is connected to the third node net3, and the other end of the fifth sub-resistor R5 is connected to one end of the sixth sub-resistor R6. The other end of the sixth sub-resistor R6 is connected to one end of both the seventh sub-resistor R7 and the eighth sub-resistor R8. The other end of the seventh sub-resistor R7 is connected to the other end of the eighth sub-resistor R8.

[0054] It should be noted that, whether for the first load unit 1131 or the second load unit 1132, Figure 9 The example only uses two sub-resistors connected in series and two sub-resistors connected in parallel. In practical applications, the number of sub-resistors connected in series and the number of sub-resistors connected in parallel can be reasonably designed according to the actual requirements of the equivalent resistance of the first load unit 1131 and / or the second load unit 1132 in the receiving circuit. Alternatively, several sub-resistors connected in series can be designed to form the first load unit 1131 and / or the second load unit 1132, or several sub-resistors connected in parallel can be designed to form the first load unit 1131 and / or the second load unit 1132, or several sub-resistors that have already formed a parallel circuit can be designed to form the first load unit 1131 and / or the second load unit 1132.

[0055] In some embodiments, reference Figure 10 and Figure 11The first load unit 1131 may include: a first resistor 1133 connected between the second node net2 and the fourth node net4; a first adjustable load 1134 connected between the fourth node net4 and ground, configured to adjust the equivalent resistance value of the first adjustable load 1134 in response to the adjustment signal SeEnN, and the equivalent resistance value of the first adjustable load 1134 in single-ended mode is greater than the equivalent resistance value of the first adjustable load 1134 in differential mode; the second load unit 1132 may include: a second resistor 1135 connected between the third node net3 and the fifth node net5; a second adjustable load 1136 connected between the fifth node net5 and ground, configured to adjust the equivalent resistance value of the second adjustable load 1136 in response to the adjustment signal SeEnN, and the equivalent resistance value of the second adjustable load 1136 in single-ended mode is greater than the equivalent resistance value of the second adjustable load 1136 in differential mode. Thus, by controlling the equivalent resistance value of the first adjustable load 1134 in single-ended mode to be greater than that in differential mode, it is beneficial to ensure that the equivalent resistance value of the first load unit 1131 in single-ended mode is greater than that in differential mode; by controlling the equivalent resistance value of the second adjustable load 1136 in single-ended mode to be greater than that in differential mode, it is beneficial to ensure that the equivalent resistance value of the second load unit 1132 in single-ended mode is greater than that in differential mode.

[0056] It should be noted that in some embodiments, the resistance of the first resistor 1133 and the second resistor 1135 is 0, that is, the load module 113 only has an adjustable load part, the second node net2 and the fourth node net4 are nodes with the same potential, and the third node net3 and the fifth node net5 are nodes with the same potential.

[0057] In some embodiments, reference Figure 11 The first adjustable load 1134 may include: a third resistor 1137 connected between the fourth node net4 and ground; a first MOSFET M1, the first end of which is connected to the fourth node net4, the second end of which is connected to ground, and the control terminal of the first MOSFET M1 receiving an adjustment signal SeEnN. In single-ended mode, the first MOSFET M1 is turned off in response to the adjustment signal SeEnN, and in differential mode, the first MOSFET M1 is turned on in response to the adjustment signal SeEnN.

[0058] It is understandable that the third resistor 1137 and the first MOSFET M1 are connected in parallel. In single-ended mode, when the first MOSFET M1 is turned off in response to the adjustment signal SeEnN, the first adjustable load 1134 is composed of the third resistor 1137. In differential mode, when the first MOSFET M1 is turned on in response to the adjustment signal SeEnN, the first adjustable load 1134 is composed of the third resistor 1137 and the first MOSFET M1 connected in parallel. The resistance of the third resistor 1137 is greater than the total resistance of the third resistor 1137 and the first MOSFET M1 connected in parallel, thereby realizing that the equivalent resistance value of the first adjustable load 1134 in single-ended mode is greater than the equivalent resistance value of the first adjustable load 1134 in differential mode.

[0059] It should be noted that, Figure 11 Taking the third resistor 1137 as an example, which includes four sub-resistors connected in series: a ninth sub-resistor R9, a tenth sub-resistor R10, an eleventh sub-resistor R11, and a twelfth sub-resistor R12. In practical applications, the number of sub-resistors connected in series can be reasonably designed according to the actual resistance value requirements of the receiving circuit for the third resistor 1137. Alternatively, several sub-resistors connected in parallel can be designed to form the third resistor 1137, or several sub-resistors that have already formed a parallel circuit can be designed to form the third resistor 1137, or a third resistor 1137 with both series and parallel sub-resistors can be designed. Furthermore, Figure 11 Taking the first MOSFET M1 as an NMOS transistor as an example, in single-ended mode, when the adjustment signal SeEnN is low, the first MOSFET M1 is off; in differential mode, when the adjustment signal SeEnN is high, the first MOSFET M1 is on. In practical applications, the first MOSFET M1 can also be a PMOS transistor. In single-ended mode, when the adjustment signal SeEnN is high, the first MOSFET M1 is off; in differential mode, when the adjustment signal SeEnN is low, the first MOSFET M1 is on.

[0060] Among them, continue to refer to Figure 11 The second adjustable load 1136 may include: a fourth resistor 1138 connected between the fifth node net5 and ground; a second MOSFET M2, the first end of which is connected to the fifth node net5, the second end of which is connected to ground, and the control terminal of the second MOSFET M2 receiving an adjustment signal SeEnN. In single-ended mode, the second MOSFET M2 is turned off in response to the adjustment signal SeEnN, and in differential mode, the second MOSFET M2 is turned on in response to the adjustment signal SeEnN.

[0061] It is understandable that the fourth resistor 1138 and the second MOSFET M2 are connected in parallel. In single-ended mode, when the second MOSFET M2 is turned off in response to the adjustment signal SeEnN, the second adjustable load 1136 is composed of the fourth resistor 1138. In differential mode, when the second MOSFET M2 is turned on in response to the adjustment signal SeEnN, the second adjustable load 1136 is composed of the fourth resistor 1138 and the second MOSFET M2 connected in parallel. The resistance of the fourth resistor 1138 is greater than the total resistance of the fourth resistor 1138 and the second MOSFET M2 connected in parallel. Thus, the equivalent resistance of the second adjustable load 1136 in single-ended mode is greater than the equivalent resistance of the second adjustable load 1136 in differential mode.

[0062] It should be noted that, Figure 11 Taking the fourth resistor 1138, which comprises four sub-resistors connected in series—the thirteenth, fourteenth, fifteenth, and sixteenth—as an example, in practical applications, the number of sub-resistors connected in series can be rationally designed according to the actual resistance value requirements of the receiving circuit. Alternatively, several sub-resistors connected in parallel can be designed to form the fourth resistor 1138, or several sub-resistors already forming a parallel circuit can be designed to form the fourth resistor 1138, or a fourth resistor 1138 can be designed with both series and parallel sub-resistors. Furthermore, Figure 11 Taking the second MOSFET M2 as an NMOS transistor as an example, in single-ended mode, when the adjustment signal SeEnN is low, the second MOSFET M2 is off; in differential mode, when the adjustment signal SeEnN is high, the second MOSFET M2 is on. In practical applications, the second MOSFET M2 can also be a PMOS transistor. In single-ended mode, when the adjustment signal SeEnN is high, the second MOSFET M2 is off; in differential mode, when the adjustment signal SeEnN is low, the second MOSFET M2 is on.

[0063] Continue to refer to Figure 11 In some embodiments, the first resistor 1133 may include: a first sub-resistor R1 and a second sub-resistor R2 connected in series, and a third sub-resistor R3 and a fourth sub-resistor R4 connected in parallel, wherein one end of the first sub-resistor R1 is connected to the second node net2, the other end of the first sub-resistor R1 is connected to one end of the second sub-resistor R2, the other end of the second sub-resistor R2 is connected to one end of both the third sub-resistor R3 and the fourth sub-resistor R4, and the other end of the third sub-resistor R3 is connected to the other end of the fourth sub-resistor R4.

[0064] The second resistor 1135 may include a fifth sub-resistor R5 and a sixth sub-resistor R6 connected in series, and a seventh sub-resistor R7 and an eighth sub-resistor R8 connected in parallel. One end of the fifth sub-resistor R5 is connected to the third node net3, and the other end of the fifth sub-resistor R5 is connected to one end of the sixth sub-resistor R6. The other end of the sixth sub-resistor R6 is connected to one end of both the seventh sub-resistor R7 and the eighth sub-resistor R8. The other end of the seventh sub-resistor R7 is connected to the other end of the eighth sub-resistor R8.

[0065] In some embodiments, reference Figure 3 The receiving circuit may further include: a selection module 103, which receives the original first signal In1, the original second signal In2 and the original reference voltage signal vref, and is configured to provide the input buffer 101 with the first input signal input1 and the second input signal input2 in response to the mode selection signal modeselect, wherein the mode selection signal modeselect is used to characterize single-ended mode or differential mode, the first signal In1 corresponds to the original first signal In1, the second signal In2 corresponds to the original second signal In2, and the original reference voltage signal vref corresponds to the reference voltage signal vref.

[0066] Thus, the receiving circuit can control, via the selection module 103, whether the signals received by the receiving circuit are the original first signal In1 and the original second signal In2, so that the input buffer 101 receives the first signal In1 and the second signal In2 to operate in differential mode, or whether the receiving circuit receives one of the original first signal In1 and the original second signal In2 and the original reference voltage signal vref, so that the signals received by the input buffer 101 are one of the first signal In1 and the second signal In2 and the reference voltage signal vref to operate in single-ended mode.

[0067] In some embodiments, the mode selection signal (mode select) may include: a first mode selection signal (not shown) for characterizing a single-ended mode, and a second mode selection signal (not shown) for characterizing a differential mode. For example, when the mode selection signal (mode select) received by the selection module 103 is the first mode selection signal, the selection module 103 controls the receiving circuit to receive the original first signal In1 and the original second signal In2, such that the input buffer 101 receives the first signal In1 and the second signal In2; when the mode selection signal (mode select) received by the selection module 103 is the second mode selection signal, the selection module 103 controls the receiving circuit to receive the signal (either the original first signal In1 and the original second signal In2) and the original reference voltage signal vref, such that the input buffer 101 receives the signal (either the first signal In1 and the second signal In2) and the reference voltage signal vref.

[0068] In other embodiments, the selection module 103 may also control the receiving circuit to operate in differential mode or single-ended mode based on two states of the mode selection signal `mode select`. For example, when the mode selection signal `mode select` received by the selection module 103 is high, the signals received by the selection module 103 are the original first signal `In1` and the original second signal `In2`, so that the signals received by the input buffer 101 are the first signal `In1` and the second signal `In2`; when the mode selection signal `mode select` received by the selection module 103 is low, the signals received by the selection module 103 are one of the original first signal `In1` and the original second signal `In2` and the original reference voltage signal `vref`, so that the signals received by the input buffer 101 are one of the first signal `In1` and the second signal `In2` and the reference voltage signal `vref`.

[0069] In some embodiments, reference Figure 4The selection module 103 may include a first selection unit 123 and a second selection unit 133. One of the first selection unit 123 and the second selection unit 133 receives the original first signal In1 and the original reference voltage signal vref, and the other receives the original second signal In2 and the original reference voltage signal vref. In single-ended mode, one of the first selection unit 123 and the second selection unit 133 outputs the first signal In1 or the second signal In2 in response to the mode selection signal mode select, and the other outputs the reference voltage signal vref in response to the mode selection signal mode select. In differential mode, one of the first selection unit 123 and the second selection unit 133 outputs the first signal In1 in response to the mode selection signal mode select, and the other outputs the second signal In2 in response to the mode selection signal mode select.

[0070] In one example, continue to refer to Figure 4 The first selection unit 123 receives the original first signal In1 and the original reference voltage signal vref, and the second selection unit 133 receives the original second signal In2 and the original reference voltage signal vref.

[0071] In single-ended mode, the first selection unit 123 outputs a first signal In1 in response to the mode selection signal mode select, and the second selection unit 133 outputs a reference voltage signal vref in response to the mode selection signal mode select. Alternatively, the first selection unit 123 outputs a reference voltage signal vref in response to the mode selection signal mode select, and the second selection unit 133 outputs a second signal In2 in response to the mode selection signal mode select, so that the signal received by the input buffer 101 is one of the first signal In1 and the second signal In2, as well as the reference voltage signal vref.

[0072] In differential mode, the first selection unit 123 outputs a first signal In1 in response to the mode selection signal mode select, and the second selection unit 133 outputs a second signal In2 in response to the mode selection signal mode select, so that the input buffer 101 receives the first signal In1 and the second signal In2.

[0073] In some embodiments, reference Figure 6The conversion module 102 may include: an amplification unit 122 configured to amplify the voltage difference between the first output signal out1_p and the second output signal out1_n; and a conversion unit 132 configured to perform level logic conversion on the first output signal and the second output signal amplified by the amplification unit 122, and output the first internal signal out2_p and the second internal signal out2_n.

[0074] It should be noted that the level logic conversion of the first output signal and the second output signal after amplification by the amplification unit 122 refers to converting the first output signal out1_p output by the second node net2 and the second output signal out1_n output by the third node net3 from analog level to digital level, so that the high level state of the first internal signal out2_p and / or the second internal signal out2_n output by the conversion module 102 is infinitely close to the power supply voltage, and the low level state of the first internal signal out2_p and / or the second internal signal out2_n is infinitely close to the ground voltage, so as to facilitate the processing of subsequent logic circuits.

[0075] In some embodiments, continue to refer to Figure 6 The amplification unit 122 can also be configured to adjust its first operating current in response to the first bias signal Bias1, so that the first operating current in single-ended mode is less than the first operating current in differential mode. This helps to further ensure that the operating current of the receiving circuit in single-ended mode is less than that in differential mode, thereby reducing the overall power consumption of the receiving circuit.

[0076] In some embodiments, continue to refer to Figure 6 The conversion unit 132 can also be configured to adjust its second operating current in response to the second bias signal Bias2, so that the second operating current in single-ended mode is less than that in differential mode. This helps to further ensure that the operating current of the receiving circuit in single-ended mode is less than that in differential mode, thereby reducing the overall power consumption of the receiving circuit.

[0077] It should be noted that the first bias signal bias1 and the second bias signal bias2 can be the same bias signal, which helps to reduce the complexity of the receiving circuit.

[0078] The following is Figure 8 The receiving circuit shown is an example to illustrate the working principle of a receiving circuit provided in an embodiment of this disclosure. It should be noted that the working principles of the first control unit 1111, the second control unit 1112, the input module 112, and the load module 113 have been briefly described above. The following description, in conjunction with... Figure 8A brief description of the overall working principle of the receiving circuit is provided.

[0079] refer to Figure 8 In single-ended mode, when the enable signal EnN is low, the first PMOS transistor MP1 is turned on, and the bias voltage signal bias0 is at a level that turns on the second PMOS transistor MP2 and the third PMOS transistor MP3. The conduction level of the second PMOS transistor MP2 and the third PMOS transistor MP3 can be controlled by adjusting the level of the bias voltage signal bias0. When the control signal SeEn is high, the fourth PMOS transistor MP4 is turned off, and no current flows through the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, that is, the second control unit 1112 is not turned on.

[0080] In differential mode, when the enable signal EnN is low, the first PMOS transistor MP1 is turned on. The bias voltage signal bias0 is at a level that turns on the second PMOS transistor MP2 and the third PMOS transistor MP3. The control signal SeEn is also low, turning on the fourth PMOS transistor MP4. The bias voltage signal bias0 is also at a level that turns on the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6. The conduction level of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 is controlled by adjusting the level of the bias voltage signal bias0.

[0081] In both modes described above, when the level of the first input signal input1 is higher than the level of the second input signal input2, the level of the second output signal out1_n output by the third node net3 will be high, and the level of the first output signal out1_p output by the second node net2 will be low. When the level of the first input signal input1 is lower than the level of the second input signal input2, the level of the second output signal out1_n output by the third node net3 will be low, and the level of the first output signal out1_p output by the second node net2 will be high. Moreover, in single-ended mode, the equivalent resistance of the load module 113 is greater than that in differential mode. This means that even when the difference between the current at the second node net2 and the current at the third node net3 is small in single-ended mode, the voltage difference between the second node net2 and the third node net3 can be large, resulting in a large voltage swing between the second node net2 and the third node net3 in single-ended mode.

[0082] In summary, designing an input buffer 101 that can be used in both differential and single-ended modes has several advantages. First, it reduces the complexity and layout area of ​​the receiving circuit. Second, by receiving the first input signal input1 and the second input signal input2 through the same transmission path in both differential and single-ended modes, the input buffer 101 helps reduce interference to the first and second input signals input1 and input2 when the receiving circuit switches between differential and single-ended modes, thereby improving the accuracy of the first internal signal out2_p and the second internal signal out2_n output by the conversion module 102. Third, it helps to ensure that the operating current of the receiving circuit in single-ended mode is less than that in differential mode, thus reducing the power consumption of the receiving circuit in single-ended mode.

[0083] Another embodiment of this disclosure also provides a memory including the aforementioned receiving circuit. Thus, the memory can selectively receive a first signal In1, a second signal In2, and a reference voltage signal vref to selectively operate in differential mode or single-ended mode. In differential mode, the first signal In1 and the second signal In2 received by the memory can be two complementary clock signals, and the frequencies of the first signal In1 and the second signal In2 are relatively high, which is beneficial to improving the processing speed and operating performance of the memory. In single-ended mode, the memory only receives one of the first signal In1 and the second signal In2, that is, it only receives one clock signal to operate at a lower frequency, which is beneficial to saving power consumption. Furthermore, the first signal In1 and the second signal In2 received by the memory can be shared in both differential mode and single-ended mode, and the operating current of the memory in single-ended mode can be reduced by adjusting the enable signal EnN, the bias voltage signal bias0, the control signal SeEn, and the load module 113, thereby reducing the overall power consumption of the memory.

[0084] In some embodiments, the memory may be DDR memory, such as DDR5 memory.

[0085] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A receiving circuit, characterized by include: An input buffer is configured to receive a first input signal and a second input signal, compare the first input signal with the second input signal, and output a first output signal and a second output signal. In differential mode, the first input signal and the second input signal are respectively a first signal and a second signal. In single-ended mode, the first input signal is one of the first signal and the second signal, and the second input signal is a reference voltage signal. The first signal and the second signal are complementary. The conversion module is configured to receive the first output signal and the second output signal and amplify the voltage difference between the first output signal and the second output signal to output a first internal signal and a second internal signal. The selection module receives the original first signal, the original second signal, and the original reference voltage signal, and is configured to... In response to the mode selection signal, the first input signal and the second input signal are provided to the input buffer, wherein the mode selection signal is used to characterize the single-ended mode or the differential mode, the first signal corresponds to the original first signal, the second signal corresponds to the original second signal, and the original reference voltage signal corresponds to the reference voltage signal.

2. The receiving circuit as described in claim 1, characterized in that, The selection module includes: A first selection unit and a second selection unit, wherein one of the first selection unit and the second selection unit receives the original first signal and the original reference voltage signal, and the other receives the original second signal and the original reference voltage signal; In the single-ended mode, one of the first selection unit and the second selection unit outputs the first signal or the second signal in response to the mode selection signal, and the other outputs the reference voltage signal in response to the mode selection signal; In the differential mode, one of the first selection unit and the second selection unit outputs the first signal in response to the mode selection signal, and the other outputs the second signal in response to the mode selection signal.

3. The receiving circuit as described in claim 1, characterized in that, The input buffer includes: The current control module is configured to provide current to the first node in response to a bias voltage signal; An input module and a load module connected to the input module, wherein the input module is connected to the first node, and the input module is connected to the load module via a second node and a third node; The input module receives the first input signal and the second input signal, the second node outputs the first output signal, and the third node outputs the second output signal.

4. The receiving circuit as described in claim 3, characterized in that, The current control module is configured to adjust the current supplied to the first node in response to the bias voltage signal, such that the current supplied to the first node in the single-ended mode is less than the current supplied to the first node in the differential mode.

5. The receiving circuit as described in claim 3, characterized in that, The current control module includes: A first control unit, connected to the first node, is configured to turn on in response to the bias voltage signal to provide a first current to the first node; A second control unit, connected to the first node, is configured to turn on in response to a control signal and the bias voltage signal to provide a second current to the first node; In the single-ended mode, the first control unit is turned on and the second control unit is not turned on; in the differential mode, both the first control unit and the second control unit are turned on.

6. The receiving circuit as described in claim 5, characterized in that, The first control unit includes: The first PMOS transistor has an enable signal at its gate and a power supply voltage at its source. The second PMOS transistor and the third PMOS transistor have their sources connected to the drain of the first PMOS transistor. The drains of the second PMOS transistor and the third PMOS transistor are both connected to the first node. The gates of the second PMOS transistor and the third PMOS transistor both receive the bias voltage signal.

7. The receiving circuit as described in claim 5, characterized in that, The second control unit includes: The fourth PMOS transistor has its gate receiving the control signal and its source connected to the power supply voltage. The fifth PMOS transistor and the sixth PMOS transistor are connected to the drain of the fourth PMOS transistor. The drains of the fifth PMOS transistor and the sixth PMOS transistor are connected to the first node. The gates of the fifth PMOS transistor and the sixth PMOS transistor both receive the bias voltage signal.

8. The receiving circuit as described in claim 3, characterized in that, The input module includes: The seventh PMOS transistor has its gate receiving the first input signal, its source connected to the first node, and its drain connected to the second node. The eighth PMOS transistor has its gate receiving the second input signal, its source connected to the first node, and its drain connected to the third node.

9. The receiving circuit as described in claim 3, characterized in that, The load module includes: A first load unit, connected between the second node and ground, is configured such that, in the single-ended mode, the equivalent resistance value of the first load unit is greater than that in the differential mode. The second load unit, connected between the third node and ground, is configured such that, in the single-ended mode, the equivalent resistance value of the second load unit is greater than that in the differential mode.

10. The receiving circuit as described in claim 9, characterized in that, The first load unit includes: The first resistor is connected between the second node and the fourth node; A first adjustable load, connected between the fourth node and the ground terminal, is configured to adjust the equivalent resistance value of the first adjustable load in response to an adjustment signal, wherein the equivalent resistance value of the first adjustable load in the single-ended mode is greater than the equivalent resistance value of the first adjustable load in the differential mode. The second load unit includes: The second resistor is connected between the third node and the fifth node; A second adjustable load, connected between the fifth node and the ground terminal, is configured to adjust the equivalent resistance value of the second adjustable load in response to the adjustment signal, and the equivalent resistance value of the second adjustable load in the single-ended mode is greater than the equivalent resistance value of the second adjustable load in the differential mode.

11. The receiving circuit as claimed in claim 10, characterized in that, The first adjustable load includes: The third resistor is connected between the fourth node and the ground terminal; A first MOSFET, wherein a first end of the first MOSFET is connected to the fourth node, a second end of the first MOSFET is connected to the ground terminal, and a control terminal of the first MOSFET receives the adjustment signal, wherein in the single-ended mode, the first MOSFET is turned off in response to the adjustment signal, and in the differential mode, the first MOSFET is turned on in response to the adjustment signal.

12. The receiving circuit as described in claim 10, characterized in that, The second adjustable load includes: The fourth resistor is connected between the fifth node and the ground terminal; The second MOSFET has its first end connected to the fifth node and its second end connected to ground. The control terminal of the second MOSFET receives the adjustment signal. In the single-ended mode, the second MOSFET is turned off in response to the adjustment signal, and in the differential mode, the second MOSFET is turned on in response to the adjustment signal.

13. The receiving circuit as claimed in claim 1, characterized in that, The conversion module includes: The amplification unit is configured to amplify the voltage difference between the first output signal and the second output signal; The conversion unit is configured to perform level logic conversion on the first output signal and the second output signal after being amplified by the amplification unit, and output the first internal signal and the second internal signal.

14. The receiving circuit as described in claim 13, characterized in that, The amplification unit is further configured to adjust the first operating current of the amplification unit in response to a first bias signal, such that the first operating current in the single-ended mode is less than the first operating current in the differential mode.

15. The receiving circuit as described in claim 13, characterized in that, The conversion unit is further configured to adjust the second operating current of the conversion unit in response to a second bias signal, such that the second operating current in the single-ended mode is less than the second operating current in the differential mode.

16. A memory, characterized in that, Includes the receiving circuit as described in any one of claims 1-15.

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