A method for preparing an IGBT device integrated with GaN and an IGBT device

Abstract

The present invention relates to a method for preparing an IGBT device integrated with GaN and an IGBT device, comprising: making a front structure of an IGBT, performing trench etching on the front of a silicon wafer to form a first trench; growing a gate oxide layer in the first trench; performing polysilicon gate filling in the first trench to form a gate electrode; performing ion implantation on the outside of the first trench to form an N-type heavily doped region and a P-type body region; performing front ILD oxide layer growth on the silicon wafer, and performing front metal deposition and covering its surface to form a second metal layer, i.e., an emitter; inverting the silicon wafer, performing ion implantation on the back of the silicon wafer to form a P-type collector region to form an IGBT structure; growing a GaN layer and an Al GaN layer on the surface of the inverted silicon wafer to form an Al GaN / GaN interface; performing back metal deposition to form a first metal layer, i.e., a collector. The present invention makes it unnecessary to encapsulate a freewheeling diode in an external circuit when using the IGBT device, thus avoiding the introduction of additional parasitic inductance and parasitic resistance, and reducing the packaging area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing an IGBT device integrated with GaN and an IGBT device. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a semiconductor device widely used in the field of power electronics and power control. It is a hybrid power switching device that combines the characteristics of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and ordinary bipolar transistor (Bipolar Junction Transistor, BJT).

[0003] As a voltage-driven power electronic device, IGBT usually works with inductive loads. The current of inductive loads will not be cut off when they are turned off. Therefore, an anti-parallel diode is usually required as a freewheeling diode to release the current. However, the anti-parallel diode not only requires additional packaging, but also requires additional wire bonding process, which will introduce parasitic inductance and parasitic resistance, and will also occupy additional packaging area of ​​the electronic device. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the problem in the prior art that diodes require additional packaging. By providing a method for preparing an IGBT device integrated with GaN and an IGBT device, it is unnecessary to package a freewheeling diode in an external circuit during use of the IGBT, thereby avoiding the introduction of additional parasitic inductance and parasitic resistance and reducing the packaging area.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a method for preparing an IGBT device integrated with GaN, comprising:

[0006] Step S1, manufacturing the front structure of the IGBT, performing trench etching on the front side of the silicon wafer to form a first trench 2;

[0007] Step S2, growing a gate oxide layer in the first trench 2;

[0008] Step S3, after the gate oxide layer is formed, a polysilicon gate is filled in the first trench on the inner side of the gate oxide layer to form a gate electrode, and the surface of the polysilicon gate is flush with the surface of the silicon wafer;

[0009] Step S4, performing doping ion implantation on the outer side of the first trench along the boundary of the first trench; Step S5, performing front ILD oxide layer growth on the silicon wafer, and then depositing metal on the front side of the ILD oxide layer and covering its surface to form a second metal layer, i.e., an emitter;

[0010] Step S6, turning the silicon wafer over, and performing ion implantation on the back side of the silicon wafer to form a P-type collector region, thereby forming an IGBT structure;

[0011] Step S7, growing a GaN layer and an AlGaN layer on the inverted silicon wafer surface and inside the P-type collector region to form an AlGaN / GaN interface;

[0012] Step S8, performing back metal deposition to form a first metal layer, namely, a collector.

[0013] In one embodiment of the present invention, in step S4, the N-type heavily doped region is obtained through one or more N+ ion implantations.

[0014] In one embodiment of the present invention, in the step S4, the P-type body region is obtained through one or more P+ ion implantations.

[0015] In one embodiment of the present invention, in step S6, the P-type collector region is obtained by one or more P+ ion implantations.

[0016] In one embodiment of the present invention, in step S7, the method for forming the GaN layer is specifically as follows:

[0017] Performing trench etching in the inverted silicon wafer to form a second trench 3, and growing GaN in the second trench 3 to obtain a GaN layer;

[0018] In one embodiment of the present invention, in step S7, the method for forming the AlGaN layer is specifically as follows:

[0019] A third trench is dug on GaN by dry etching, and AlGaN is grown in the third trench to obtain an AlGaN layer.

[0020] In one embodiment of the present invention, the second groove and the third groove are arranged in parallel, and the two are not connected.

[0021] In one embodiment of the present invention, the etching depths of the first trench, the second trench and the third trench are 0.5-1 um.

[0022] In a second aspect, the present invention further provides an IGBT device, which is obtained by using the preparation method described in any of the above embodiments.

[0023] In one embodiment of the present invention, a drift region is further included, and the drift region is located between the P-type body region and the P-type collector region.

[0024] The above technical solution of the present invention has the following advantages compared with the prior art:

[0025] The present invention discloses a method for preparing an IGBT device integrated with GaN. By integrating GaN and AlGaN in the IGBT, it is unnecessary to package a freewheeling diode in an external circuit during use of the IGBT, thereby avoiding the introduction of additional parasitic inductance and parasitic resistance and reducing the packaging area. The IGBT device integrated with GaN performs electron transmission based on the two-dimensional electron gas at the GaN / AlGaN interface, has extremely high electron mobility, and can effectively shorten the IGBT turn-off time and energy loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein

[0027] Figure 1 is a flow chart of a method for preparing an IGBT device integrated with GaN in Embodiment 1 of the present invention;

[0028] Figure 2 1 is a schematic diagram of the structure of forming a first groove on the front side of a silicon wafer in step S1 of the first embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of the structure in which the gate oxide layer is grown in step S2 of the first embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of a structure in which polysilicon gate filling is completed in step S3 of the first embodiment of the present invention;

[0031] Figure 5 It is a schematic diagram of the structure formed by the N-type heavily doped region and the P-type body region in step S4 of the first embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of the structure of the ILD oxide layer and the second metal layer formed in step S5 of the first embodiment of the present invention;

[0033] Figure 7 It is a schematic diagram of the structure of the P-type collector region formed after the wafer is inverted in step S6 of the first embodiment of the present invention;

[0034] Figure 8 is a schematic diagram of the structure after the second trench and the third trench are etched and formed in step S7 of the first embodiment of the present invention;

[0035] Fig. 9 is a schematic diagram of the structure after the growth of GaN and AlGaN is completed in step S7 of the first embodiment of the present invention;

[0036] Fig.10 It is a schematic diagram of the structure after the second metal layer is formed in step S8 of the first embodiment of the present invention.

[0037] Explanation of the reference numerals in the specification: 1. first metal layer; 2. first trench; 3. second trench; 4. third trench; 5. GaN layer; 6. Al GaN; 7. P-type collector region; 8. drift region; 9. gate oxide layer; 10. polysilicon gate; 11. P-type body region; 12. N-type heavily doped region; 13. ILD oxide layer; 14. second metal layer. DETAILED DESCRIPTION

[0038] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0039] Embodiment 1

[0040] Reference Figure 1 As shown, a first embodiment of the present invention provides a method for preparing an IGBT device integrated with GaN. The preparation method integrates GaN in the IGBT so that there is no need to package a freewheeling diode in an external circuit during use of the IGBT, thereby avoiding the introduction of additional parasitic inductance and parasitic resistance and reducing the packaging area.

[0041] Specifically, refer to Figures 1 to 10 As shown, the method for preparing the IGBT device with integrated GaN diode includes:

[0042] Step S1, refer to Figure 2 As shown, the front structure of the IGBT is manufactured by performing trench etching on the front side of the silicon wafer to form a first trench 2; the first trench 2 extends vertically downward from the front side of the silicon wafer.

[0043] Step S2, refer to Figure 3 As shown, a gate oxide layer 9 is grown in the first trench 2 ; the sidewalls and the bottom wall of the first trench 2 are covered with the gate oxide layer 9 .

[0044] Step S3, refer to Figure 4 As shown, after the gate oxide layer 9 is formed, a polysilicon gate 10 is filled inside the first trench 2 and located inside the gate oxide layer 9 to form a gate electrode, and the surface of the polysilicon gate 10 is flush with the surface of the silicon wafer; the polysilicon gate 10 is insulated from the sidewalls and bottom wall of the first trench 2 by the gate oxide layer 9.

[0045] Step S4, refer to Figure 5 As shown, doping ions are implanted along the boundary of the first trench 2 outside the first trench 2 to form an N-type heavily doped region 12; after the N-type heavily doped region 12 is formed, ions are implanted again to form a P-type body region 11;

[0046] Wherein, in step S4, the N-type heavily doped region is obtained by one or more N+ ion implantations, and the P-type body region 11 is obtained by one or more P+ ion implantations.

[0047] Step S5, refer to Figure 6 As shown, a front ILD oxide layer 13 is grown on a silicon wafer, and then a front metal is deposited on the ILD oxide layer 13 to cover its surface, forming a second metal layer 14, namely, an emitter; the ILD oxide layer is an electrical insulating layer.

[0048] Step S6, refer to Figure 7 As shown, the silicon wafer is turned over, and ion implantation is performed on the back of the silicon wafer to form a P-type collector region 7, thereby forming an IGBT structure; in the step S6, the P-type collector region 7 is obtained after one or more P+ ion implantations.

[0049] Step S7, refer to Figure 8 and 9 As shown, a GaN layer 5 and an Al GaN layer 6 are grown on the surface of the inverted silicon wafer and located inside the P-type collector region to form an Al GaN / GaN interface; the method for forming the GaN layer is specifically as follows: trench etching is performed in the inverted silicon wafer to form a second trench 3, and GaN is grown in the second trench 3 to obtain a GaN layer 5 (gallium nitride layer); the method for forming the Al GaN layer 6 is specifically as follows: a third trench 3 is dug on the GaN by a dry etching process, and AlGaN is grown in the third trench 3 to obtain an AlGaN layer 6 (aluminum gallium nitride layer), wherein the second trench 3 and the third trench 4 are arranged in parallel, and the two are not connected.

[0050] In this embodiment, the etching depth of the first trench 2, the second trench 3 and the third trench 4 is 0.5-1 um.

[0051] Step S8, refer to Fig.10 As shown, back metal deposition is performed to form a first metal layer 1, ie, a collector.

[0052] In the first embodiment of the present invention, GaN generates piezoelectric effect due to external stress, and polarization charge is induced at the interface, while the energy band of AlGaN is bent at the interface, resulting in a triangular potential well. A large number of electrons gather in the triangular potential well and are confined at the interface, which is called two-dimensional electron gas (2DEG). By growing GaN in the second trench 3 and growing AlGaN in the third trench 4 in the IGBT structure, a GaN / lGaN interface is formed, and then the two-dimensional electron gas at the GaN / lGaN interface performs electron transmission, which has extremely high electron mobility and can effectively shorten the IGBT turn-off time and energy loss.

[0053] Embodiment 2

[0054] Reference Fig.10 As shown, the second embodiment of the present invention provides an IGBT device integrated with GaN, and the IGBT device integrated with GaN diode is obtained by the preparation method described in the first embodiment. The IGBT device integrated with GaN diode is, from bottom to top, first metal layer 1-second trench 3-third trench 4-GaN layer 5-AlGaN layer 6-P-type collector region 7-drift region 8-first trench 2-gate oxide layer 9-polysilicon gate-P-type body region 11-N-type heavily doped region 12-ILD oxide layer 13-second metal layer 14. By integrating GaN and AlGaN in the IBGT device, the IGBT does not need to encapsulate the freewheeling diode in the external circuit during use, avoiding the introduction of additional parasitic inductance and parasitic resistance, and reducing the packaging area.

[0055] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A method for preparing an IGBT device integrated with GaN, characterized in that: include: Step S1, manufacturing the front structure of the IGBT, performing trench etching on the front side of the silicon wafer to form a first trench 2; Step S2, growing a gate oxide layer in the first trench; Step S3, after the gate oxide layer is formed, a polysilicon gate is filled in the first trench on the inner side of the gate oxide layer to form a gate electrode, and the surface of the polysilicon gate is flush with the surface of the silicon wafer; Step S4, performing doping ion implantation on the outer side of the first trench along the boundary of the first trench to form an N-type heavily doped region; After the N-type heavily doped region is formed, ion implantation is performed to form a P-type body region; Step S5, growing a front ILD oxide layer on the silicon wafer, and then depositing a metal on the front side of the ILD oxide layer and covering its surface to form a second metal layer, namely, an emitter; Step S6, turning the silicon wafer over, and performing ion implantation on the back side of the silicon wafer to form a P-type collector region, thereby forming an IGBT structure; Step S7, growing a GaN layer and an AlGaN layer on the inverted silicon wafer surface and inside the P-type collector region to form an AlGaN / GaN interface, wherein the contact interface between the GaN layer and the AlGaN layer is located in a vertical direction, and the P-type collector region is in contact with the GaN layer and the AlGaN layer; Step S8, performing back metal deposition to form a first metal layer, namely, a collector.

2. The method for preparing an IGBT device integrated with GaN according to claim 1, characterized in that: In step S4, the N-type heavily doped region is obtained through one or more N+ ion implantations.

3. The method for preparing an IGBT device integrated with GaN according to claim 1, characterized in that: In the step S4, the P-type body region is obtained through one or more P+ ion implantations.

4. The method for preparing an IGBT device integrated with GaN according to claim 3, characterized in that: In the step S6, the P-type collector region is obtained through one or more P+ ion implantations.

5. The method for preparing an IGBT device integrated with GaN according to claim 1, characterized in that: In step S7, the method for forming the GaN layer is specifically as follows: A trench is etched in the inverted silicon wafer to form a second trench, and GaN is grown in the second trench to obtain a GaN layer.

6. The method for preparing an IGBT device integrated with GaN according to claim 5, characterized in that: In step S7, the method for forming the AlGaN layer is specifically as follows: A third trench is dug on GaN by a dry etching process, and AlGaN is grown in the third trench to obtain an AlGaN layer.

7. The method for preparing an IGBT device integrated with GaN according to claim 6, characterized in that: The second groove and the third groove are arranged in parallel, and the two are not connected.

8. The method for preparing an IGBT device integrated with GaN according to claim 7, characterized in that: The etching depths of the first trench, the second trench and the third trench are 0.5-1 um.

9. An IGBT device, characterized in that: The IGBT device is obtained by the preparation method according to any one of claims 1 to 8.

10. The IGBT device according to claim 9, characterized in that: A drift region is also included, and the drift region is located between the P-type body region and the P-type collector region.

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