A method of manufacturing a gate-all-around transistor

Abstract

The application discloses a manufacturing method of a ring gate transistor, and relates to the technical field of semiconductors, which aims to reduce the manufacturing difficulty of an inner spacer included in the ring gate transistor. The manufacturing method comprises the following steps: performing first lateral thinning treatment on at least the part of each layer of the sacrificial layer located in a third region along the width direction of a fin; and performing oxidation treatment on at least the remaining part of each layer of the sacrificial layer located in the third region to form an oxide layer. A dielectric layer is formed to fill both sides of the oxide layer along the width direction of the fin. The outer sidewall of the dielectric layer along the width direction of the fin is flush with the outer sidewall of the channel layer along the width direction of the fin. Under the mask effect of a first mask layer, at least the part of the fin located in a first region and a second region is removed, so that the two sides of the part of the oxide layer and the dielectric layer corresponding to the third region are exposed. Second lateral thinning treatment is performed on the part of the oxide layer and the dielectric layer corresponding to the third region along the length direction of the fin. An inner spacer is formed on both sides of the remaining part of the oxide layer and the dielectric layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a gate-around transistor. Background Technology

[0002] Gate-around transistors (GMT-A) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistor types in an integrated circuit are GMT-A, it is beneficial to improve the operating performance of the integrated circuit. Furthermore, placing inner walls between the gate stack and the source region, and between the gate stack and the drain region in a GMT-A can limit the length of the gate stack and suppress the effects of short-channel effects.

[0003] However, using existing gate-around transistor manufacturing methods, it is difficult to form the notches used to fill the inner sidewalls during the manufacturing process, which is not conducive to improving the yield and performance of gate-around transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing a gate-around transistor, which reduces the manufacturing difficulty of the inner sidewalls included in the gate-around transistor, thereby improving the yield and performance of the gate-around transistor.

[0005] To achieve the above objectives, the present invention provides a method for manufacturing a gate-ring transistor, the method comprising:

[0006] First, at least a fin is formed on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin includes at least one semiconductor stack, each semiconductor stack including a sacrificial layer and a channel layer located on the sacrificial layer. Along the length direction of the fin, the fin includes a first region, a second region, and a third region located between the first and second regions. Next, along the width direction of the fin, at least the portion of each sacrificial layer located in the third region is subjected to a first lateral thinning process; and at least the remaining portion of each sacrificial layer located in the third region is oxidized to form an oxide layer. Next, a dielectric layer is formed filling both sides of the oxide layer along the width direction of the fin. The outer wall of the dielectric layer along the width direction of the fin is flush with the outer wall of the channel layer along the width direction of the fin. Next, under the masking action of a first mask layer, at least the portions of the fin located in the first and second regions are removed, so that the portions of the oxide layer and dielectric layer corresponding to the third region are exposed on both sides. The first mask layer spans across the portion of the fin corresponding to the third region. Next, along the length of the fin, a second lateral thinning process is performed on the portion of the oxide layer and dielectric layer corresponding to the third region; and inner sidewalls are formed on both sides of the remaining portions of the oxide layer and dielectric layer. Next, source and drain regions are formed on both sides of the fin along its length. Next, at least a portion of the first mask layer is removed, and the remaining portions of the oxide layer and dielectric layer are removed, so that each channel layer included in the fin forms a nanostructure. Next, a gate stack structure is formed around the periphery of each nanostructure.

[0007] In the manufacturing method provided by the present invention, after forming a fin comprising at least one semiconductor stack on a semiconductor substrate, a first lateral thinning process is performed on at least the portion of each sacrificial layer located in the third region (the region between the source and drain regions in the gate-around transistor) along the width direction of the fin. At this time, the remaining portion of at least each sacrificial layer in the third region is recessed inward along the width direction of the fin. Next, at least the remaining portion of each sacrificial layer in the third region is oxidized, and the resulting oxide layer is also recessed inward along the width direction of the fin. Next, a dielectric layer is formed filling both sides of the oxide layer along the width direction of the fin. The outer wall of this dielectric layer along the width direction of the fin is flush with the outer wall of the channel layer along the width direction of the fin. Therefore, the presence of the dielectric layer prevents the nanostructure from being unable to be released as a whole layer due to the subsequent inner sidewalls filling both sides of the oxide layer along the width direction of the fin, thus improving the yield of the gate-around transistor. Next, under the masking effect of the first mask layer, at least the portions of the fin located in the first and second regions are removed, exposing both sides of the portions of the oxide layer and dielectric layer corresponding to the third region. Then, along the length direction of the fin, a second lateral thinning process is performed on the portions of the oxide layer and dielectric layer corresponding to the third region. It is understood that the manufacturing method provided by the present invention achieves selective etching of the portions of the oxide layer and dielectric layer corresponding to the third region relative to the channel layer using an etchant; because compared with the conventional manufacturing method that achieves selective etching of the sacrificial layer relative to the channel layer, which is also made of semiconductor material, using an etchant, it is easier to achieve a high etching selectivity between the oxide layer and the dielectric layer and the channel layer respectively, the second thinning process of the manufacturing method provided by the present invention is less difficult and is less likely to cause damage to the channel layer, further improving the yield of the gate-around transistor. Meanwhile, since it is easier to achieve a high etching selectivity between the oxide layer and the dielectric layer and the channel layer respectively, the manufacturing method provided by the present invention can reduce the difficulty of releasing the nanostructure by removing the remaining parts of the oxide layer and dielectric layer after removing at least part of the first mask layer, thereby further improving the yield of the gate ring transistor and improving the working performance of the gate ring transistor. Attached Figure Description

[0008] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0009] Figure 1 A flowchart illustrating the manufacturing method of a gate-ring transistor provided in an embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 1 ;

[0011] Figure 3 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 2 ;

[0012] Figure 4 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 3 ;

[0013] Figure 5 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 4 ;

[0014] Figure 6 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 5 ;

[0015] Figure 7 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 6 ;

[0016] Figure 8 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 7 ;

[0017] Figure 9 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 8 ;

[0018] Figure 10 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 9 ;

[0019] Figure 11 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 ;

[0020] Figure 12 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 one;

[0021] Figure 13 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 two;

[0022] Figure 14 This is a schematic diagram of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 three;

[0023] Figure 15 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 Four;

[0024] Figure 16 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 five;

[0025] Figure 17 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 six;

[0026] Figure 18 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 seven;

[0027] Figure 19 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 eight;

[0028] Figure 20 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 10 Nine;

[0029] Figure 21 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 2 ten;

[0030] Figure 22 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 2 eleven;

[0031] Figure 23 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 2 Twelve and symbol Figure 2 Thirteen;

[0032] Figure 24Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 2 Fourteen and illustration Figure 2 fifteen;

[0033] Figure 25 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 2 Sixteen and illustration Figure 2 Seventeen;

[0034] Figure 26 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 2 Eighteen and indication Figure 2 nineteen;

[0035] Figure 27 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 3 Ten and symbol Figure 3 eleven;

[0036] Figure 28 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 3 Twelve and symbol Figure 3 Thirteen;

[0037] Figure 29 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 3 Fourteen and illustration Figure 3 fifteen;

[0038] Figure 30 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 3 Sixteen and illustration Figure 3 Seventeen;

[0039] Figure 31 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 3 Eighteen and indication Figure 3 nineteen;

[0040] Figure 32 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 4 Ten and symbol Figure 4 eleven;

[0041] Figure 33 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 4 twelve;

[0042] Figure 34 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 4 Thirteen and illustration Figure 4 fourteen;

[0043] Figure 35 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 4 fifteen;

[0044] Figure 36 Parts (1) and (2) are longitudinal cross-sectional views of the middle and edge regions of the inner wall along the width direction of the ring-gate transistor formed by the manufacturing method provided in the embodiments of the present invention during the manufacturing process. Figure 4 Sixteen and illustration Figure 4 Seventeen;

[0045] Figure 37 This is a schematic cross-sectional view of the structure of a gate-ring transistor formed using the manufacturing method provided in this embodiment of the invention during the manufacturing process. Figure 4 eighteen.

[0046] Reference numerals: 11 Semiconductor substrate, 12 Stacked material layer, 13 Fin structure, 14 Shallow trench isolation structure, 15 Fin, 16 Semiconductor stack, 17 Sacrificial layer, 18 Channel layer, 19 First region, 20 Second region, 21 Third region, 22 Second mask layer, 23 Oxide layer, 24 Dielectric layer, 25 First mask layer, 26 Sacrificial gate, 27 Gate sidewall, 28 Inner sidewall, 29 Source region, 30 Drain region, 31 Interlayer dielectric layer, 32 Nanostructure, 33 Gate stack structure. Detailed Implementation

[0047] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0048] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0049] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0051] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0052] Gate-around transistors (GMT-A) offer advantages over planar transistors and fin field-effect transistors, such as higher gate control capability. Therefore, when all transistor types in an integrated circuit are GMT-A, it is beneficial to improve the operating performance of the integrated circuit. Furthermore, placing inner walls between the gate stack and the source region, and between the gate stack and the drain region in a GMT-A can limit the length of the gate stack and suppress the effects of short-channel effects.

[0053] Specifically, in the fabrication of the inner sidewall using existing gate-around transistor (GOT) methods, after forming fins and sacrificial gates and gate sidewalls spanning the fins on a semiconductor substrate, the fin structure is patterned under the masking effect of the sacrificial gates and gate sidewalls. After patterning, the remaining channel layer and sacrificial layer in the fins are exposed along their length. Then, using an etchant that etches only the sacrificial layer and has little or no effect on the channel layer, the remaining sacrificial gate layers at their length edges are removed to form notches for filling the inner sidewalls. Next, deposition and etching processes are used to form the inner sidewalls filling the notches, thus realizing the fabrication of the inner sidewalls in the GOT transistor.

[0054] However, in the process of forming the above-mentioned notch, the etching process is usually required to achieve a high selectivity etching ratio between the sacrificial layer and the channel layer (e.g., the etching selectivity ratio between the sacrificial layer and the channel layer is greater than or equal to 100:1). However, the current etchant is difficult to achieve a high selectivity etching ratio between the two, which makes it more difficult to form the notch used to fill the inner sidewall and easily causes damage to the channel layer, which is not conducive to improving the yield and working performance of the gate ring transistor.

[0055] To address the aforementioned technical problems, embodiments of the present invention provide a method for manufacturing a gate-around transistor. In this method, under the masking effect of a first mask layer, at least the portions of the fin located in the first and second regions are removed, exposing both sides of the portions of the oxide and dielectric layers corresponding to the third region. Then, along the length of the fin, the portions of the oxide and dielectric layers corresponding to the third region undergo a second lateral thinning process to form a notch for filling the inner sidewall. It is understood that the manufacturing method provided by the present invention achieves selective etching of the portions of the oxide and dielectric layers corresponding to the third region relative to the channel layer using an etchant, thereby reducing the manufacturing difficulty of the inner sidewall and improving the yield and performance of the gate-around transistor.

[0056] like Figure 1 As shown, this embodiment of the invention provides a method for manufacturing a gate-ring transistor. The following will describe a method based on... Figures 2 to 37 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the manufacturing method of this gate-ring transistor includes the following steps:

[0057] First, such as Figure 4 As shown, at least one fin 15 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin 15 includes at least one semiconductor stack 16, each semiconductor stack 16 including a sacrificial layer 17 and a channel layer 18 located on the sacrificial layer 17. Along the length direction of the fin 15, the fin 15 includes a first region 19, a second region 20, and a third region 21 located between the first region 19 and the second region 20.

[0058] In practical applications, each channel layer in the aforementioned semiconductor stack is used to fabricate the nanostructure included in the gate-around transistor. Therefore, the material and thickness of each channel layer are the same as the material and thickness of the corresponding nanostructure, and the number of semiconductor stack layers included in the fin is equal to the number of nanostructure layers included in the gate-around transistor. As for the sacrificial layer included in the semiconductor stack, the material of the sacrificial layer can be any semiconductor material different from the channel layer material. Secondly, since a partial gate stack structure will be formed in the space where the sacrificial layer is located in the third region, the thickness of the sacrificial layer can be determined based on the thickness of the gate stack structure included in the gate-around transistor, and is not specifically limited here.

[0059] As for the first, second, and third regions included in the fin, there are no clear physical boundaries between these three regions. Subsequently, nanostructures will be formed based on the portion of each channel layer in the fin corresponding to the third region. Therefore, the ranges of the first, second, and third regions in the fin can be determined based on the length of the nanostructures included in the gate-around transistor and their positions within the gate-around transistor.

[0060] For example, forming fins on a semiconductor substrate may include the steps of: Figure 2 As shown, at least one stacked material layer 12 can be formed on the semiconductor substrate 11 using processes such as epitaxial growth. This stacked material layer 12 is used to manufacture the aforementioned semiconductor stack; therefore, the thickness of the stacked material layer 12 and the material and thickness of each film layer can be determined based on the number of semiconductor stack layers included in the fin, and the material and thickness of the channel layer and sacrificial layer included in each semiconductor stack. Next, as... Figure 3 As shown, photolithography and etching processes can be used to pattern at least one layer of stacked material and a portion of the semiconductor substrate 11 to form a fin structure 13 on the semiconductor substrate 11. Then, as... Figure 4 As shown, a shallow trench isolation structure 14 covering the semiconductor substrate 11 can be formed using processes such as deposition and etching. The top height of the shallow trench isolation structure 14 is less than or equal to the top height of the sacrificial layer 17 located at the bottom layer, and the portion of the fin structure exposed outside the shallow trench isolation structure 14 is the fin portion 15.

[0061] Next, as Figure 5 and Figure 11 As shown, along the width direction of the fin 15, at least the portion of each sacrificial layer 17 located in the third region undergoes a first lateral thinning process. Figure 6 and Figure 12 As shown, at least the remaining portion of each sacrificial layer 17 located in the third region is oxidized to form an oxide layer 23.

[0062] In practical applications, such as Figure 5 As shown, along the width direction of the fin 15, the portions of each sacrificial layer 17 located in the first, second, and third regions can all undergo a first lateral thinning process. In this case, the width of each remaining portion of the sacrificial layer 17 along its length is smaller than the width of the channel layer 18. Furthermore, as... Figure 6 As shown, the remaining portions of each sacrificial layer 17 located in the first, second, and third regions are oxidized to form an oxide layer 23. At this point, the oxide layer 23 is located not only in the third region but also in the first and second regions.

[0063] Alternatively, along the width direction of the fin, at least the portion of each sacrificial layer located in the third region may undergo a first lateral thinning process, including: such as... Figure 10As shown, a second mask layer 22 can be formed covering the outer periphery of the fin located in the first and second regions using processes such as photolithography. The material of this second mask layer 22 can be determined according to the actual application scenario, and is not specifically limited here. For example, the second mask layer 22 can be a photoresist mask layer or spin-coated carbon, etc. After the second mask layer 22 is formed, only the portion of the fin located in the third region 21 is exposed. Next, as... Figure 11 As shown, under the masking effect of the second mask layer 22, and along the width direction of the fin, only the portion of each sacrificial layer 17 located in the third region undergoes the first lateral thinning process. At this time, as... Figure 11 As shown, only the remaining portion of each sacrificial layer 17 in the third region has a width less than the width of the channel layer 18, while the portion of each sacrificial layer 17 in the first and second regions has a width equal to the width of the channel layer 18. Furthermore, as... Figure 12 As shown, under the masking effect of the second mask layer 22, only the remaining part of each sacrificial layer 17 located in the third region is oxidized, and the resulting oxide layer 23 is only located in the third region.

[0064] Specifically, the first lateral thinning process is performed only on the portion of each sacrificial layer located in the third region, or the first lateral thinning process is performed on the portions of each sacrificial layer located in the first, second, and third regions. The amount of thinning can be determined according to the width of the fin and actual needs, as long as it can be applied to the manufacturing method provided in the embodiments of the present invention.

[0065] For example, after the first lateral thinning process, the width of the remaining portion of each sacrificial layer in the third region can be greater than or equal to 3 nm and less than or equal to 15 nm. For instance, the width of the remaining portion of each sacrificial layer in the third region after the first lateral thinning process can be 3 nm, 5 nm, 7 nm, 9 nm, 11 nm, 13 nm, or 15 nm, etc. In this case, the width of the remaining portion of each sacrificial layer in the third region after the first lateral thinning process is within the above range. This prevents problems such as bending or collapse of the remaining portion of each sacrificial layer in the third region after the first thinning process due to a small width, or difficulty in providing sufficient support for the channel layer above it with a narrow sacrificial layer, thus improving the yield of the gate-around transistor. Furthermore, it also prevents the channel layer from being affected by oxidation due to a large width, as this would require a longer processing time for at least the remaining portion of each sacrificial layer in the third region. This is beneficial for improving the formation quality of the nanostructure.

[0066] Secondly, the embodiments of the present invention do not specifically limit the processing conditions such as temperature and time of the above oxidation treatment.

[0067] Next, as Figure 7 and Figure 13 As shown, a dielectric layer 24 is formed and filled on both sides of the oxide layer 23 along the width direction of the fin 15. The outer wall of the dielectric layer 24 along the width direction of the fin 15 is flush with the outer wall of the channel layer 18 along the width direction of the fin 15.

[0068] In practical applications, a dielectric material can be deposited to cover the existing structure and fill both sides of the oxide layer along the width of the fin. Then, under the masking effect of at least the channel layer, the portion of the dielectric material filling the oxide layer beyond the width of the fin can be removed to obtain the dielectric layer. For example, Figure 7 As shown, before the first lateral thinning and oxidation treatment of the sacrificial layer 17, and before the second mask layer is formed, the dielectric layer 24 formed at this time is located not only in the third region, but also in the first and second regions. Figure 13 As shown, a second mask layer is formed before the first lateral thinning process is performed on the sacrificial layer 17, so the resulting dielectric layer 24 only fills the third region.

[0069] Specifically, the material of the dielectric layer can be the same as or different from that of the oxide layer. Understandably, a second lateral thinning process will be performed on the oxide layer and dielectric layer located in the third region to obtain a notch for filling the inner sidewall; and the etching rate of the etchant on the oxide layer and dielectric layer will affect the morphology of the formed inner sidewall, so the material of the dielectric layer can be determined according to the morphology of the inner sidewall to be formed.

[0070] Next, as Figure 9 and Figure 16 As shown, under the masking effect of the first mask layer 25, at least the portions of the fin located in the first and second regions are removed, so that the sides of the portions of the oxide layer 23 and the dielectric layer 24 corresponding to the third region are exposed. The first mask layer 25 spans the portion of the fin corresponding to the third region.

[0071] In practical applications, the structure and material of the first mask layer can be determined according to the actual application scenario, as long as it has a masking function. For example, the first mask layer can be a photoresist mask layer. Another example is... Figure 8 and Figure 14 As shown, the first mask layer 25 may include a sacrificial gate 26 and gate sidewalls 27 located at least on both sides of the sacrificial gate 26 along the length direction.

[0072] Specifically, the formation process of the first mask layer can be determined based on its structure and material. For example, taking a first mask layer comprising a sacrificial gate and gate sidewalls as an example, a deposition process can be used to form a material layer covering the formed structure; and the material layer can be sequentially planarized and patterned to obtain the sacrificial gate. Then, a deposition process is used to form sidewall material covering the formed structure, and then a dry etching process is used to remove the portion of the sidewall material covering the sacrificial gate sidewalls to obtain the gate sidewalls.

[0073] It should be noted that, in the case of forming a second mask layer, the second mask layer may be removed by wet etching or dry etching after the dielectric layer is formed and before the first mask layer is formed; or, the second mask layer may be removed after the first mask layer is formed and before at least the portion of the fin located in the first region and the second region is removed.

[0074] It is worth noting that the second mask layer is removed only after the first mask layer has been formed. At this point, the presence of the second mask layer during the fabrication of the first mask layer can somewhat limit the formation location of the first mask layer, reducing alignment difficulties.

[0075] Furthermore, after forming the first mask layer, processes such as dry etching can be used to remove at least the portion of the fin located in the first and second regions. Specifically, for example... Figure 8 and Figure 9 As shown, if the second mask layer is not formed before the first lateral thinning and oxidation treatment of the sacrificial layer, the oxide layer 23 and the dielectric layer 24 are also located in the first and second regions. Therefore, it is necessary to remove the portions of the fins, oxide layer, and dielectric layer located in the first and second regions under the masking effect of the first mask layer 25.

[0076] And such Figure 14 and Figure 15 As shown, when the second mask layer 22 is formed before the first lateral thinning and oxidation treatment of the sacrificial layer 17, the portion of the fin 15 corresponding to the first and second regions consists of alternating layers of the sacrificial layer 17 and the channel layer 18. In this case, the removal of the fin 15 corresponding to the first and second regions is the same as the manufacturing process of a conventional gate-around transistor, which reduces the etching difficulty.

[0077] Next, as Figures 17 to 19 As shown, along the length direction of the fin, a second lateral thinning process is performed on the portion of the oxide layer 23 and the dielectric layer 24 corresponding to the third region; as shown... Figures 20 to 22 As shown, inner sidewalls 28 are formed on both sides of the remaining portions of oxide layer 23 and dielectric layer 24.

[0078] In practical applications, the second lateral thinning process described above can be performed using dry etching or wet etching techniques. Specifically, for example... Figure 17 As shown, the etching rate of the etchant used in the second lateral thinning process can be the same for both the oxide layer 23 and the dielectric layer 24. In this case, the depth of the notches formed after the second lateral thinning process to fill the inner sidewalls 28 is the same in all portions along the width direction of the trench layer 18, which allows the thickness of the subsequently formed inner sidewalls 28 to be the same in all portions along the width direction of the trench layer 18. Specifically, the materials of the oxide layer 23 and the dielectric layer 24 can be the same or different. For example, the materials of the oxide layer 23 and the dielectric layer 24 can include at least one of silicon oxide, silicon carbide, and silicon oxynitride. For example, the materials of the oxide layer 23 and the dielectric layer 24 can both be silicon oxide; or, the material of the oxide layer 23 is silicon oxide, and the material of the dielectric layer 24 can be silicon carbide or silicon oxynitride.

[0079] Or, such as Figure 18 and Figure 19 As shown, at least a portion of the material of the dielectric layer 24 is different from that of the oxide layer 23, and the etching rate of the etchant used in the second lateral thinning process differs between the oxide layer 23 and at least a portion of the dielectric layer 24. Wherein, as Figure 18 As shown, the etchant can have a higher etching rate on the oxide layer 23 and a slower etching rate on the dielectric layer 24; in this case, the depth of the formed notch in the middle portion along the width direction of the trench layer 18 is greater than the depth of the edge portion. Or, as... Figure 19 As shown, the etchant can also have a higher etching rate on the dielectric layer 24 and a slower etching rate on the oxide layer 23; in this case, the depth of the edge portion of the notch along the width direction of the channel layer 18 is greater than the depth of the middle portion. In the above case, the material of the dielectric layer 24 can be any insulating material that is different from the material of the oxide layer 23 and has a different etching rate. For example, if the material of the oxide layer 23 includes silicon oxide, the material of the dielectric layer 24 can include silicon nitride and / or silicon carbonitride.

[0080] After forming the recess for filling the inner wall, as Figures 20 to 22 As shown, processes such as deposition and etching can be used to form inner sidewalls 28 that fill the remaining portions of the oxide layer 23 and the dielectric layer 24. The inner sidewalls 28 can be flat or have a middle portion that is concave inward or convex outward.

[0081] Next, as Figures 22 to 25 As shown, source region 29 and drain region 30 can be formed on both sides of the fin along its length using epitaxial growth or other processes. The materials of source region 29 and drain region 30 can be silicon, silicon germanium, or germanium, etc.

[0082] Next, as Figures 26 to 28 As shown, an interlayer dielectric layer 31 is formed covering the semiconductor substrate 11. The top of the interlayer dielectric layer 31 is flush with the top of the first mask layer 25. The material of the interlayer dielectric layer 31 can be any insulating material different from that of the oxide layer 23 and the dielectric layer 24. For example, if the material of the oxide layer 23 is silicon oxide and the material of the dielectric layer 24 is silicon oxynitride, the material of the interlayer dielectric layer 31 can be silicon nitride.

[0083] Of course, if subsequent operations have little or no impact on the source and drain regions, the aforementioned interlayer dielectric layer may not be formed.

[0084] Next, as Figures 29 to 31 As shown, at least a portion of the first mask layer and the remaining portions of the oxide layer and dielectric layer are removed to form nanostructures 32 in each channel layer 18 included in the fin.

[0085] In practical applications, dry etching or wet etching processes can be used to completely remove the first mask layer. Alternatively, if the first mask layer also includes a sacrificial gate and gate sidewalls, such as... Figures 29 to 31 As shown, only the sacrificial gate needs to be removed. Then, processes such as dry etching or wet etching can be used to remove the remaining oxide and dielectric layers, releasing the nanostructure 32.

[0086] Next, as Figures 32 to 37 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 33 surrounding each nanostructure 32.

[0087] Specifically, the aforementioned gate stack structure may include a gate dielectric layer surrounding each nanostructure layer and a gate electrode located on the gate dielectric layer. The gate dielectric layer may be made of dielectric materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate electrode may be made of conductive materials such as TiN, TaN, or TiSiN.

[0088] It is worth noting that, as mentioned above, such as Figures 34 to 37 As shown, when the etching rates of the dielectric layer and oxide layer in the second lateral thinning process are different, the middle portion of the inner sidewall of the formed inner sidewall 28 along the width direction of the gate stack structure 33 will be recessed inward or protruded outward. At this time, part of the gate stack structure 33 can be formed in the recesses corresponding to the middle and edge regions of the inner sidewall, so that this part of the gate stack structure 33 has a certain control capability over the edge portions of the nanostructure 32 along the length direction when the gate ring transistor is in operation, reducing the resistivity of the edge portions of the nanostructure 32 along the length direction, which is beneficial to improving the driving performance of the gate ring transistor.

[0089] As can be seen from the above manufacturing process, such as Figures 2 to 37As shown, in the manufacturing method provided in this embodiment of the invention, after forming a fin 15 including at least one semiconductor stack 16 on a semiconductor substrate 11, a first lateral thinning process is performed on at least the portion of each sacrificial layer 17 located in the third region 21 (the region between the source region 29 and the drain region 30 in the gate-around transistor) along the width direction of the fin 15. At this time, at least the remaining portion of each sacrificial layer 17 in the third region 21 is recessed inward along the width direction of the fin 15. Next, at least the remaining portion of each sacrificial layer 17 located in the third region 21 is oxidized, and the resulting oxide layer 23 is also recessed inward along the width direction of the fin 15. Next, a dielectric layer 24 is formed to fill both sides of the oxide layer 23 along the width direction of the fin 15. The outer wall of the dielectric layer 24 along the width direction of the fin 15 is flush with the outer wall of the channel layer 18 along the width direction of the fin 15. Therefore, the presence of the dielectric layer 24 can prevent the nanostructure 32 from being unable to be released as a whole layer due to the inner sidewall 28 being filled on both sides of the oxide layer 23 along the width direction of the fin 15, which is beneficial to improving the yield of the gate-around transistor. Next, under the masking effect of the first mask layer 25, at least the portion of the fin 15 located in the first region 19 and the second region 20 is removed, so that the two sides of the portions of the oxide layer 23 and the dielectric layer 24 corresponding to the third region 21 are exposed. Then, along the length direction of the fin 15, a second lateral thinning process is performed on the portions of the oxide layer 23 and the dielectric layer 24 corresponding to the third region 21. It is understood that the manufacturing method provided in this embodiment of the invention selectively etches the portion of the oxide layer 23 and dielectric layer 24 corresponding to the third region 21 relative to the channel layer 18 using an etchant. Compared with the conventional manufacturing method that selectively etches the sacrificial layer 17 relative to the channel layer 18, which is also made of semiconductor material, using an etchant, it is easier to achieve a high etching selectivity between the oxide layer 23 and dielectric layer 24 and the channel layer 18, respectively. Therefore, the second thinning process of the manufacturing method provided in this embodiment of the invention is less difficult and is less likely to damage the channel layer 18, further improving the yield of the gate-around transistor. At the same time, because it is easier to achieve a high etching selectivity between the oxide layer 23 and dielectric layer 24 and the channel layer 18, the manufacturing method provided in this embodiment of the invention, after removing at least a portion of the first mask layer 25, can also reduce the difficulty of releasing the nanostructure 32 by removing the remaining portion of the oxide layer 23 and dielectric layer 24, further improving the yield of the gate-around transistor and helping to improve the working performance of the gate-around transistor.

[0090] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0091] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A method for manufacturing a gate-ring transistor, characterized in that, include: At least fins are formed on the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin includes at least one semiconductor stack, each semiconductor stack including a sacrificial layer and a channel layer located on the sacrificial layer; along the length direction of the fin, the fin includes a first region, a second region, and a third region located between the first region and the second region; Along the width direction of the fin, at least the portion of each sacrificial layer located in the third region is subjected to a first lateral thinning process; And at least the remaining portion of each of the sacrificial layers located in the third region is oxidized to form an oxide layer; A dielectric layer is formed that fills both sides of the oxide layer along the width direction of the fin; The outer wall of the medium layer along the width direction of the fin is flush with the outer wall of the channel layer along the width direction of the fin. Under the masking effect of the first mask layer, at least the portions of the fins located in the first and second regions are removed, so that the portions of the oxide layer and the dielectric layer corresponding to the third region are exposed on both sides. The first mask layer spans the portion of the fin corresponding to the third region; Along the length direction of the fin, a second lateral thinning process is performed on the portion of the oxide layer and the dielectric layer corresponding to the third region; Inner sidewalls are formed on both sides of the remaining portions of the oxide layer and the dielectric layer; A source region and a drain region are formed on both sides of the fin along its length. At least a portion of the first mask layer is removed, and the remaining portions of the oxide layer and the dielectric layer are removed, so that each channel layer included in the fin forms a nanostructure; A gate stack structure is formed around the periphery of each layer of the nanostructure.

2. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The process of forming fins on a semiconductor substrate includes: At least one layer of stacked material is formed on the semiconductor substrate; The at least one layer of stacked material and a portion of the semiconductor substrate are patterned to form a fin-like structure on the semiconductor substrate; A shallow trench isolation structure is formed covering the semiconductor substrate; the top height of the shallow trench isolation structure is less than or equal to the top height of the sacrificial layer located at the bottom layer, and the portion of the fin structure exposed outside the shallow trench isolation structure is a fin.

3. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The first lateral thinning process, which involves at least the portion of each sacrificial layer located in the third region along the width direction of the fin, includes performing a first lateral thinning process on the portions of each sacrificial layer located in the first region, the second region, and the third region along the width direction of the fin. The removal of at least the portion of the fin located in the first region and the second region under the masking effect of the first masking layer includes: removing the portions of the fin, the oxide layer, and the dielectric layer located in the first region and the second region under the masking effect of the first masking layer.

4. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The first lateral thinning process, performed along the width direction of the fin, at least on the portion of each sacrificial layer located in the third region, includes: forming a second mask layer covering the periphery of the fin located in the first and second regions; then, under the masking effect of the second mask layer, and along the width direction of the fin, performing the first lateral thinning process only on the portion of each sacrificial layer located in the third region. After forming the dielectric layer filling both sides of the oxide layer along the width direction of the fin, and before removing at least the portion of the fin located in the first region and the second region under the masking action of the first mask layer, the manufacturing method of the ring gate transistor further includes: removing the second mask layer.

5. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, The etching agent used in the second lateral thinning process has the same etching rate for both the oxide layer and the dielectric layer.

6. The method for manufacturing a gate-to-ring transistor according to claim 5, characterized in that, The oxide layer and the dielectric layer are made of the same material; and / or, The materials of the oxide layer and the dielectric layer include at least one of silicon oxide, silicon oxycarbonate, and silicon oxynitride.

7. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, At least a portion of the material of the dielectric layer is different from that of the oxide layer, and the etching rate of the etchant used in the second lateral thinning process is different for the oxide layer and at least a portion of the dielectric layer.

8. The method for manufacturing a gate-to-ring transistor according to claim 7, characterized in that, The oxide layer is made of silicon oxide; and / or, The material of the dielectric layer includes silicon nitride and / or silicon carbonitride.

9. The method for manufacturing a gate-to-ring transistor according to claim 1, characterized in that, After the first lateral thinning process, the width of the remaining portion of each sacrificial layer in the third region is greater than or equal to 3 nm and less than or equal to 15 nm.

10. A method for manufacturing a gate-to-ring transistor according to any one of claims 1 to 9, characterized in that, The first mask layer includes a sacrificial gate and gate sidewalls located at least on both sides of the sacrificial gate along its length. The removal of at least a portion of the first mask layer includes: removing the sacrificial gate.

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