Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, the substrate comprises a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the material of the epitaxial layer comprises silicon carbide, the epitaxial layer comprises a gate trench, the surface of the epitaxial layer exposed at the bottom of the gate trench is a carbon surface of silicon carbide; a first gate oxide layer is located at the bottom and sidewall of the gate trench and does not extend to the surface of the epitaxial layer, the thickness of the first gate oxide layer at the bottom of the gate trench is greater than the thickness of the first gate oxide layer at the sidewall; a second gate oxide layer is located on the surface of the first gate oxide layer and does not extend to the surface of the epitaxial layer; and a gate is located in the gate trench and fills the gate trench. The application provides a semiconductor structure and a forming method thereof, which can reduce the parasitic capacitance of the surface of the epitaxial layer and improve the reliability of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Silicon carbide MOSFETs with trench gates are semiconductor devices that differ from traditional silicon substrates and horizontal channels. However, current processes for fabricating these trench gate-structured silicon carbide devices still have limitations, leading to compromises in device performance and reliability.

[0003] Therefore, it is necessary to provide more effective and reliable technical solutions. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can reduce the parasitic capacitance on the surface of the epitaxial layer and improve device reliability.

[0005] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate, the epitaxial layer being made of silicon carbide, the epitaxial layer including a gate trench, the exposed surface of the epitaxial layer at the bottom of the gate trench being a carbon surface of silicon carbide; forming a first gate oxide layer at the bottom and sidewalls of the gate trench and on the surface of the epitaxial layer using a thermal oxidation process, the thickness of the first gate oxide layer at the bottom of the gate trench being greater than the thickness of the first gate oxide layer on the sidewalls; forming a second gate oxide layer on the surface of the first gate oxide layer; forming a gate filling the gate trench in the gate trench; and removing the first gate oxide layer and the second gate oxide layer located on the surface of the epitaxial layer.

[0006] In some embodiments of this application, the oxidation temperature of the thermal oxidation process is 1000 to 1200 degrees Celsius.

[0007] In some embodiments of this application, the thickness ratio of the first gate oxide layer at the bottom of the gate trench to the thickness of the first gate oxide layer on the sidewall is (1.5-2.5):1.

[0008] In some embodiments of this application, the method for forming the semiconductor structure further includes: performing an annealing process on the first gate oxide layer.

[0009] In some embodiments of this application, the process parameters of the annealing process include: a process temperature higher than 1300 degrees Celsius; and process gases including NO or N2O, N2 or Ar or He.

[0010] In some embodiments of this application, the second gate oxide layer includes a first aluminum oxide layer, a lanthanum oxide layer, and a second aluminum oxide layer sequentially located on the surface of the first gate oxide layer.

[0011] In some embodiments of this application, the thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

[0012] In some embodiments of this application, the second gate oxide layer is semi-crystalline and some atoms in the second gate oxide layer diffuse into the first gate oxide layer.

[0013] In some embodiments of this application, the method for forming the second gate oxide layer includes: forming a second gate oxide layer on the surface of the first gate oxide layer, wherein the second gate oxide layer is in a semi-amorphous state; performing an annealing process on the second gate oxide layer to convert the second gate oxide layer into a semi-crystalline state and causing some atoms in the second gate oxide layer to diffuse into the first gate oxide layer.

[0014] In some embodiments of this application, the process parameters of the annealing process include: a process temperature below 800 degrees Celsius; and a process gas including O2.

[0015] Another aspect of this application provides a semiconductor structure comprising: a substrate, the substrate including a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate, the epitaxial layer being made of silicon carbide, the epitaxial layer including a gate trench, the exposed surface of the epitaxial layer at the bottom of the gate trench being a carbon surface of silicon carbide; a first gate oxide layer located at the bottom of the gate trench and not extending to the surface of the epitaxial layer, the thickness of the first gate oxide layer at the bottom of the gate trench being greater than the thickness of the first gate oxide layer at the sidewalls; a second gate oxide layer located on the surface of the first gate oxide layer not extending to the surface of the epitaxial layer; and a gate located in the gate trench filling the gate trench.

[0016] In some embodiments of this application, the thickness ratio of the first gate oxide layer at the bottom of the gate trench to the thickness of the first gate oxide layer on the sidewall is (1.5-2.5):1.

[0017] In some embodiments of this application, the second gate oxide layer is semi-crystalline and some atoms in the second gate oxide layer diffuse into the first gate oxide layer.

[0018] In some embodiments of this application, the second gate oxide layer includes a first aluminum oxide layer, a lanthanum oxide layer, and a second aluminum oxide layer sequentially located on the surface of the first gate oxide layer.

[0019] In some embodiments of this application, the thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

[0020] This application provides a semiconductor structure and a method for forming the same, wherein the surface of the epitaxial layer does not have a high dielectric constant material layer, which can reduce the parasitic capacitance on the surface of the epitaxial layer and improve the reliability of the device. Attached Figure Description

[0021] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0022] in:

[0023] Figures 1 to 5 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation

[0024] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0025] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0026] Figures 1 to 5 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0027] refer to Figure 1 As shown, a substrate 100 is provided, the substrate 100 including a semiconductor substrate 101 and an epitaxial layer 102 located on the surface of the semiconductor substrate 101. The material of the epitaxial layer includes silicon carbide. The epitaxial layer 102 includes a gate trench 110 for forming a gate. The surface of the epitaxial layer 102 exposed at the bottom of the gate trench 110 is a carbon surface of silicon carbide.

[0028] In some embodiments of this application, the semiconductor structure described in the embodiments of this application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0029] In some embodiments of this application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide. The epitaxial layer 102 may have doped ions, such as N-type doped ions.

[0030] In some embodiments of this application, the material of the epitaxial layer 102 includes 4H-SiC, the surface of the epitaxial layer 102 exposed at the bottom of the gate trench 110 is the carbon surface of the 4H-SiC, and the surface of the epitaxial layer 102 exposed on the sidewalls of the gate trench 110 is the A-plane or M-plane of the 4H-SiC. Various polycrystalline types of silicon carbide exist, the most common being 3C-SiC with a cubic crystal structure, 4H-SiC and 6H-SiC with a hexagonal crystal structure, etc. Single-crystal SiC can be oriented and polished to present a main crystal plane as its surface, such as the (0001) plane, i.e., the silicon plane, with silicon as the surface. Other surfaces perpendicular to the silicon plane also include A-planes or M-planes, etc., with the opposite surface of the silicon plane being the carbon plane.

[0031] refer to Figure 2 As shown, a first gate oxide layer 120 is formed at the bottom and sidewalls of the gate trench 110 and on the surface of the epitaxial layer 102 using a thermal oxidation process. The thickness of the first gate oxide layer 120 at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewalls.

[0032] In some embodiments of this application, the material of the first gate oxide layer 120 includes silicon oxide.

[0033] In some embodiments of this application, the oxidation temperature of the thermal oxidation process is 1000 to 1200 degrees Celsius.

[0034] In some embodiments of this application, the thickness ratio of the first gate oxide layer 120 at the bottom of the gate trench 110 to the thickness of the first gate oxide layer 120 on the sidewall is (1.5-2.5):1, for example 2:1.

[0035] In the technical solution of this application, the surface of the epitaxial layer 102 exposed at the bottom of the gate trench 110 is the carbon surface of the 4H-SiC, and the surface of the epitaxial layer 102 exposed on the sidewall of the gate trench 110 is either the A-side or the M-side of the 4H-SiC. At a temperature of 1000 to 1200 degrees Celsius, the oxidation rate of the carbon surface is greater than that of the A-side and the M-side. Therefore, the thickness of the first gate oxide layer 120 at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewall.

[0036] Furthermore, since the thickness of the first gate oxide layer 120 at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewall, and the first gate oxide layer 120 at the corner of the bottom of the gate trench 110 is thicker, the bottom of the gate trench 110, especially the corner, is better protected, is less prone to leakage current, and has low parasitic capacitance.

[0037] In some embodiments of this application, the method of forming the semiconductor structure further includes annealing the first gate oxide layer 120. The interface between the epitaxial layer 102 (SiC) and the first gate oxide layer 120 (SiO2) has unterminated bonds, which act as electron traps. Therefore, NO or N2O annealing can terminate free bonds.

[0038] In some embodiments of this application, the process parameters of the annealing process include: a process temperature higher than 1300 degrees Celsius; and process gases including NO or N2O, N2 or Ar or He. NO or N2O is used as the actual process gas, while N2 or Ar or He provides an inert atmosphere. The mass percentage of NO or N2O in the total process gas is 8% to 12%, for example, 10%.

[0039] In some embodiments of this application, the thickness of the first gate oxide layer 120 is less than 10 nanometers, for example, 9 nanometers, 8 nanometers, 7 nanometers, 6 nanometers or 5 nanometers.

[0040] refer to Figure 3 As shown, a second gate oxide layer 130 is formed on the surface of the first gate oxide layer 120.

[0041] In some embodiments of this application, the second gate oxide layer 130 includes a first aluminum oxide layer (Al2O3), a lanthanum oxide layer (La2O3), and a second aluminum oxide layer (Al2O3) sequentially located on the surface of the first gate oxide layer 120.

[0042] In some embodiments of this application, the thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

[0043] In other embodiments of this application, the second gate oxide layer 130 may also be a single-layer structure, such as a single-layer aluminum oxide layer or a single-layer lanthanum oxide layer. The second gate oxide layer 130 may also be a multilayer stacked layer composed of any number of aluminum oxide layers or lanthanum oxide layers.

[0044] In other embodiments of this application, the second gate oxide layer 130 may also be a single layer or stacked layer of any other suitable high dielectric constant material.

[0045] In some embodiments of this application, the second gate oxide layer 130 is in a semi-crystalline state, and some atoms (e.g., La and / or Al) in the second gate oxide layer 130 diffuse into the first gate oxide layer 120. In some embodiments of this application, the first gate oxide layer 120 is also converted to a semi-crystalline state. The deposited film still contains some byproducts, such as hydrogen and carbon, which escape from the film when it is converted to a semi-crystalline state.

[0046] In some embodiments of this application, the method for forming the second gate oxide layer 130 includes: forming a second gate oxide layer 130 on the surface of the first gate oxide layer 120, wherein the second gate oxide layer 130 is in a semi-amorphous state; performing an annealing process on the second gate oxide layer 130 to transform the second gate oxide layer 130 into a semi-crystalline state, and allowing some atoms in the second gate oxide layer 130 to diffuse into the first gate oxide layer 120. A semi-amorphous state refers to a state where, in optical observation, there is no evidence of crystal structure such as rough surfaces and grain boundaries; and in X-ray analysis, a halo pattern is shown, which is evidence of a crystalline state. A semi-crystalline state refers to a state where, in optical observation, a smooth surface is observed; and in X-ray analysis, a spot / halo pattern is shown.

[0047] In some embodiments of this application, the process parameters of the annealing process include: a process temperature below 800 degrees Celsius, such as 750 degrees Celsius, 700 degrees Celsius, 650 degrees Celsius, or 600 degrees Celsius; and a process gas including O2.

[0048] refer to Figure 4 As shown, a gate 140 is formed in the gate trench 110 to fill the gate trench 110. Specifically, the top surface of the gate 140 is flush with the top surface of the epitaxial layer 102.

[0049] In some embodiments of this application, the gate 140 is made of doped polycrystalline silicon. Methods for forming the gate 140 include chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0050] refer to Figure 5 As shown, the first gate oxide layer 120 and the second gate oxide layer 130 located on the surface of the epitaxial layer 102 are removed.

[0051] In some embodiments of this application, the method for removing the first gate oxide layer 120 and the second gate oxide layer 130 located on the surface of the epitaxial layer 102 includes chemical mechanical polishing, wet etching, or dry etching.

[0052] In the technical solution of this application, removing the first gate oxide layer 120 and the second gate oxide layer 130 on the surface of the epitaxial layer 102 can reduce the parasitic capacitance on the surface of the epitaxial layer 102 and improve the device reliability.

[0053] This application provides a method for forming a semiconductor structure in which there is no high dielectric constant material layer on the surface of the epitaxial layer, which can reduce the parasitic capacitance on the surface of the epitaxial layer and improve the reliability of the device.

[0054] Embodiments of this application also provide a semiconductor structure, referencing Figure 5 As shown, the system includes: a substrate 100, which includes a semiconductor substrate 101 and an epitaxial layer 102 located on the surface of the semiconductor substrate 101. The material of the epitaxial layer 102 includes silicon carbide. The epitaxial layer 102 includes a gate trench 110, and the exposed surface of the epitaxial layer at the bottom of the gate trench is a carbon surface of silicon carbide; a first gate oxide layer 120 located at the bottom and sidewalls of the gate trench 110 that does not extend to the surface of the epitaxial layer 102, wherein the thickness of the first gate oxide layer at the bottom of the gate trench is greater than the thickness of the first gate oxide layer at the sidewalls; a second gate oxide layer 130 located on the surface of the first gate oxide layer 120 that does not extend to the surface of the epitaxial layer 102; and a gate 140 located in the gate trench 110 and filling the gate trench 110.

[0055] In some embodiments of this application, the semiconductor structure described in the embodiments of this application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0056] In some embodiments of this application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide. The epitaxial layer 102 may have doped ions, such as N-type doped ions.

[0057] In some embodiments of this application, the material of the epitaxial layer 102 includes 4H-SiC, the surface of the epitaxial layer 102 exposed at the bottom of the gate trench 110 is the carbon surface of the 4H-SiC, and the surface of the epitaxial layer 102 exposed on the sidewalls of the gate trench 110 is the A-plane or M-plane of the 4H-SiC. Various polycrystalline types of silicon carbide exist, the most common being 3C-SiC with a cubic crystal structure, 4H-SiC and 6H-SiC with a hexagonal crystal structure, etc. Single-crystal SiC can be oriented and polished to present a main crystal plane as its surface, such as the (0001) plane, i.e., the silicon plane, with silicon as the surface. Other surfaces perpendicular to the silicon plane also include A-planes or M-planes, etc., with the opposite surface of the silicon plane being the carbon plane.

[0058] Continue to refer to Figure 5 As shown, the thickness of the first gate oxide layer 120 located at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewall.

[0059] In some embodiments of this application, the material of the first gate oxide layer 120 includes silicon oxide.

[0060] In some embodiments of this application, the thickness ratio of the first gate oxide layer 120 at the bottom of the gate trench 110 to the thickness of the first gate oxide layer 120 on the sidewall is (1.5-2.5):1, for example 2:1.

[0061] In some embodiments of this application, the thickness of the first gate oxide layer 120 is less than 10 nanometers, for example, 9 nanometers, 8 nanometers, 7 nanometers, 6 nanometers or 5 nanometers.

[0062] In the technical solution of this application, the surface of the epitaxial layer 102 exposed at the bottom of the gate trench 110 is the carbon surface of the 4H-SiC, and the surface of the epitaxial layer 102 exposed on the sidewall of the gate trench 110 is either the A-side or the M-side of the 4H-SiC. At a temperature of 1000 to 1200 degrees Celsius, the oxidation rate of the carbon surface is greater than that of the A-side and the M-side. Therefore, the thickness of the first gate oxide layer 120 at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewall.

[0063] Furthermore, since the thickness of the first gate oxide layer 120 at the bottom of the gate trench 110 is greater than the thickness of the first gate oxide layer 120 on the sidewall, and the first gate oxide layer 120 at the corner of the bottom of the gate trench 110 is thicker, the bottom of the gate trench 110, especially the corner, is better protected, is less prone to leakage current, and has low parasitic capacitance.

[0064] Continue to refer to Figure 5As shown, the second gate oxide layer 130 is in a semi-crystalline state and some atoms (e.g., La and / or Al) in the second gate oxide layer 130 diffuse into the first gate oxide layer 120.

[0065] In some embodiments of this application, the second gate oxide layer 130 includes a first aluminum oxide layer (Al2O3), a lanthanum oxide layer (La2O3), and a second aluminum oxide layer (Al2O3) sequentially located on the surface of the first gate oxide layer 120.

[0066] In some embodiments of this application, the thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

[0067] In other embodiments of this application, the second gate oxide layer 130 may also be a single-layer structure, such as a single-layer aluminum oxide layer or a single-layer lanthanum oxide layer. The second gate oxide layer 130 may also be a multilayer stacked layer composed of any number of aluminum oxide layers or lanthanum oxide layers.

[0068] In other embodiments of this application, the second gate oxide layer 130 may also be a single layer or stacked layer of any other suitable high dielectric constant material.

[0069] Continue to refer to Figure 5 As shown, in some embodiments of this application, the material of the gate 140 is doped polycrystalline silicon.

[0070] In the technical solution of this application, the surface of the epitaxial layer 102 does not have the first gate oxide layer 120 and the second gate oxide layer 130, which can reduce the parasitic capacitance on the surface of the epitaxial layer 102 and improve the reliability of the device.

[0071] This application provides a semiconductor structure and a method for forming the same, wherein the surface of the epitaxial layer does not have a high dielectric constant material layer, which can reduce the parasitic capacitance on the surface of the epitaxial layer and improve the reliability of the device.

[0072] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0073] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0074] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0075] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0076] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate, the epitaxial layer being made of silicon carbide, the epitaxial layer including a gate trench, and the exposed surface of the epitaxial layer at the bottom of the gate trench being a carbon surface of silicon carbide; A first gate oxide layer is formed at the bottom and sidewalls of the gate trench and on the surface of the epitaxial layer using a thermal oxidation process. The thickness of the first gate oxide layer at the bottom of the gate trench is greater than the thickness of the first gate oxide layer on the sidewall. A second gate oxide layer is formed on the surface of the first gate oxide layer. The second gate oxide layer includes a first aluminum oxide layer, a lanthanum oxide layer, and a second aluminum oxide layer sequentially located on the surface of the first gate oxide layer. The second gate oxide layer is semi-crystalline, and some atoms in the second gate oxide layer diffuse into the first gate oxide layer. The method for forming the second gate oxide layer includes: forming a second gate oxide layer on the surface of the first gate oxide layer, wherein the second gate oxide layer is semi-amorphous; performing an annealing process on the second gate oxide layer to transform the second gate oxide layer into a semi-crystalline state and to diffuse some atoms in the second gate oxide layer into the first gate oxide layer. The partial atoms include La and / or Al. The process parameters of the annealing process include: a process temperature below 800 degrees Celsius; and a process gas including O2. A gate is formed in the gate trench to fill the gate trench; Remove the first gate oxide layer and the second gate oxide layer located on the surface of the epitaxial layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The oxidation temperature of the thermal oxidation process is 1000 to 1200 degrees Celsius.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness ratio of the first gate oxide layer at the bottom of the gate trench to the thickness of the first gate oxide layer on the sidewall is (1.5-2.5):

1.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: The first gate oxide layer is subjected to an annealing process.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process parameters of the annealing process include: process temperature above 1300 degrees Celsius; process gas including NO or N2O, N2 or Ar or He.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

7. A semiconductor structure, characterized in that, Formed using any one of claims 1 to 6, comprising: The substrate includes a semiconductor substrate and an epitaxial layer located on the surface of the semiconductor substrate. The material of the epitaxial layer includes silicon carbide. The epitaxial layer includes a gate trench, and the exposed surface of the epitaxial layer at the bottom of the gate trench is a carbon surface of silicon carbide. The first gate oxide layer located at the bottom and sidewalls of the gate trench does not extend to the surface of the epitaxial layer, and the thickness of the first gate oxide layer at the bottom of the gate trench is greater than the thickness of the first gate oxide layer on the sidewalls; A second gate oxide layer located on the surface of the first gate oxide layer that does not extend to the surface of the epitaxial layer, the second gate oxide layer comprising a first aluminum oxide layer, a lanthanum oxide layer and a second aluminum oxide layer sequentially located on the surface of the first gate oxide layer, the second gate oxide layer being semi-crystalline and some atoms in the second gate oxide layer diffusing into the first gate oxide layer; A gate located in the gate trench that fills the gate trench.

8. The semiconductor structure as described in claim 7, characterized in that, The thickness ratio of the first gate oxide layer at the bottom of the gate trench to the thickness of the first gate oxide layer on the sidewall is (1.5-2.5):

1.

9. The semiconductor structure as described in claim 7, characterized in that, The thickness of the first alumina layer is 2 to 10 nanometers, the thickness of the lanthanum oxide layer is 10 to 20 nanometers, and the thickness of the second alumina layer is 2 to 10 nanometers.

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