Method for improving over-sized middle-of-line metal contact via size

Abstract

This application provides a method for improving the excessive size of mid-section metal contact vias, comprising: step S1, providing a substrate, on which shallow trench isolation, a gate structure, and an interlayer dielectric layer are formed, and a capping layer and a sacrificial material layer are sequentially formed on the interlayer dielectric layer; step S2, forming contact grooves connecting the source / drain of the device; step S3, forming a protective layer on the sidewalls of the contact grooves; step S4, forming a photoresist layer with a contact via pattern; step S5, forming contact vias connecting the gate structure; step S6, performing a pre-cleaning process on the contact grooves and contact vias; and step S7, forming a metal layer in the contact grooves and contact vias. This application effectively prevents CD expansion caused by wear on the sidewalls of the contact vias during pre-cleaning, minimizes damage to the work function metal layer in the gate structure during etching, and significantly reduces the load of polishing performed after forming the mid-section metal contact.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and specifically to a method for improving the excessive size of mid-section metal contact vias. Background Technology

[0002] The introduction of FinFET technology was a major advancement in the next-generation 22nm semiconductor industry. FinFET technology allows for more efficient control of the source / drain current at the transistor's gate. However, as the size shrinks, transistor fabrication becomes increasingly difficult. The FinFET process mainly includes Fin (fin-shaped silicon substrate), Poly (polysilicon gate), EPI (source / drain epitaxial growth), MG (metal gate), Contact (mid-section metal contact), and BEOL (back-end interconnect).

[0003] The middle section metal contact consists of MOA and MOP. MOA consists of grooves connecting to the source / drain, linking the source / drain to the subsequent wiring. MOP consists of vias connecting to the gate, linking the gate to the subsequent wiring. The via size refers to the MOP CD (Critical Dimension). Both local variations and global CDU (CD Uniformity) of the MOP CD are crucial. Poor MOP CDU can lead to excessively small MOP openings or insufficient spacing between MOP and MOA. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method to improve the excessive size of the intermediate metal contact through hole, so as to solve the problem of poor MOP CDU in the prior art.

[0005] To achieve the above and other related objectives, this application provides a method for improving the excessive size of intermediate metal contact through holes, comprising:

[0006] Step S1: A substrate is provided, on which a shallow trench isolation, a gate structure and an interlayer dielectric layer are formed, and a capping layer and a sacrificial material layer are sequentially formed on the interlayer dielectric layer.

[0007] Step S2: Form contact grooves to connect the source / drain of the device;

[0008] Step S3: Form a protective layer on the sidewall of the contact groove;

[0009] Step S4: Form a photoresist layer with a contact via pattern;

[0010] Step S5: Form a contact via for connecting the gate structure;

[0011] Step S6: Perform pre-cleaning treatment on the contact groove and contact through hole;

[0012] Step S7: Form a metal layer in the contact groove and the contact through hole.

[0013] Preferably, step S7 includes: forming a Ti / TiN adhesive layer on the sidewalls and bottom of the contact groove and contact via by a deposition process; filling the contact groove and contact via with a metal layer; and removing the sacrificial material layer and the metal layer in the sacrificial material layer by a grinding process until the cover layer is exposed.

[0014] Preferably, the thickness of the covering layer is 205 angstroms to 215 angstroms.

[0015] Preferably, the material of the capping layer is silicon nitride, and the material of the sacrificial material layer is oxide.

[0016] Preferably, the material of the protective layer is silicon nitride.

[0017] Preferably, step S4 includes: sequentially forming a spin-coated carbon layer, an anti-reflective coating, and a photoresist layer on the sacrificial material layer; and forming a contact via pattern in the photoresist layer by photolithography.

[0018] Preferably, step S5 includes: using a photoresist layer with a contact via pattern as a mask, etching an anti-reflective coating, a spin-coated carbon layer, a sacrificial material layer, a capping layer, and part of the interlayer dielectric layer to expose the top of the gate structure; and removing the photoresist layer, the anti-reflective coating, and the spin-coated carbon layer.

[0019] Preferably, the capping layer serves as the etch stop layer, ensuring that the top of all gate structures is exposed in one step during the final stage of the etching process, thus preventing damage to the work function metal layer in the gate structure.

[0020] Preferably, the pre-cleaning process is carried out using the SiCoNi process.

[0021] Preferably, the gate structure includes a high-k dielectric layer, a work function metal layer, and a metal gate stacked from bottom to top, and the sidewalls of the gate structure are formed with sidewall structures.

[0022] As described above, the method for improving the size of the intermediate metal contact via provided in this application has the following beneficial effects: it can effectively prevent the CD expansion phenomenon caused by the wear of the contact via sidewall due to the pre-cleaning process, and can also prevent the damage of the work function metal layer in the gate structure to the greatest extent by etching, and significantly improve the load of the polishing performed after the formation of the intermediate metal contact. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figures 1A-1E This is a schematic diagram of the cross-sectional structure of a device formed after the completion of each step in forming the mid-section metal contact using existing technology.

[0025] Figure 1F This diagram illustrates an excessively large MOP size in a mid-section metal contact formed using existing technology.

[0026] Figure 2 The flowchart shown is a method for improving the excessive size of the intermediate metal contact through hole provided in an embodiment of this application;

[0027] Figures 3A-3F The diagram shown is a cross-sectional view of the device formed after each step in the method for improving the size of the middle metal contact via provided in this application embodiment. Detailed Implementation

[0028] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this invention.

[0029] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," indicating orientation or positional relationships, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0031] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0032] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0033] like Figure 1A As shown, a shallow trench isolation (STI), a gate structure 101, and an interlayer dielectric layer 102 are formed on the substrate 100, and a contact groove (MOA) 103 for connecting the source / drain of the device is formed in the interlayer dielectric layer 102.

[0034] like Figure 1B As shown, a protective layer 105 is formed on the sidewalls and bottom of the contact groove 103 by a deposition process, and then the protective layer 105 located at the bottom of the contact groove 103 is removed by an etching process. The function of the protective layer 105 is to reduce the MOA CD, protect the gate structure 101, and reduce the risk of shortening of the spacing between the MOP and MOA. During subsequent pre-cleaning processes, the protective layer 105 can prevent the expansion of the MOA CD caused by damage to the sidewalls of the contact groove 103 during the cleaning process.

[0035] like Figure 1C As shown, a spin-coated carbon (SOC) layer 106, an anti-reflective coating (ARC) 107, and a photoresist layer 108 with a contact via (MOP) pattern are sequentially formed on the interlayer dielectric layer 102.

[0036] like Figure 1D As shown, using the photoresist layer 108 as a mask, contact vias 109 are formed in the interlayer dielectric layer 102 through an etching process. Then, the spin-coated carbon layer 106, the anti-reflective coating 107, and the photoresist layer 108 are removed.

[0037] Next, a pre-cleaning process is performed to remove etching residues and impurities from the contact groove 103 and contact through hole 109.

[0038] like Figure 1E As shown, a Ti / TiN adhesive layer (not shown in the illustration) is formed on the sidewalls and bottom of the contact groove 103 and the contact through hole 109, and then a metal layer 110 is filled in the contact groove 103 and the contact through hole 109.

[0039] In the above-described process of forming the contact groove 103 and the contact through hole 109 in the prior art, since a protective layer 105 is not formed on the sidewall of the contact through hole 109, the pre-cleaning process will damage the sidewall of the contact through hole 109, resulting in an excessively large CD of the contact through hole 109. Figure 1F As shown, the spacing between M0P and M0A decreases accordingly.

[0040] If a protective layer 105 is formed simultaneously on the sidewalls and bottom of the contact groove 103 and the contact through-hole 109 after the contact through-hole 109 is formed, it will cause more serious problems: Figure 1D Taking the device cross-sectional structure shown as an example, removing the protective layer 105 located at the bottom of the contact via 109 will damage the work function metal layer in the gate structure.

[0041] To address the aforementioned issues, this application provides a method for improving the excessive size of the intermediate metal contact through-hole.

[0042] Please see Figure 2 The flowchart illustrates a method for improving the excessive size of the intermediate metal contact through hole provided in an embodiment of this application.

[0043] like Figure 2 As shown, the method for improving the excessive size of the intermediate metal contact through hole includes the following steps:

[0044] Step S1: A substrate is provided, on which a shallow trench isolation, a gate structure and an interlayer dielectric layer are formed, and a capping layer and a sacrificial material layer are sequentially formed on the interlayer dielectric layer.

[0045] Step S2: Form contact grooves to connect the source / drain of the device;

[0046] Step S3: Form a protective layer on the sidewall of the contact groove;

[0047] Step S4: Form a photoresist layer with a contact via pattern;

[0048] Step S5: Form a contact via for connecting the gate structure;

[0049] Step S6: Perform pre-cleaning treatment on the contact groove and contact through hole;

[0050] Step S7: Form a metal layer in the contact groove and the contact through hole.

[0051] In step S1, as Figure 3AAs shown, the substrate 300 can be a semiconductor substrate, such as silicon (Si), germanium (Ge), SiGe substrate, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a multilayer structure, such as Si / SiGe. Those skilled in the art can select the constituent materials of the substrate according to the type of device structure formed on the substrate 300; therefore, the type of substrate 300 should not limit the scope of protection of this invention.

[0052] Shallow trench isolation (STI) is formed on substrate 300. Exemplarily, the shallow trench isolation is formed by a shallow trench isolation process, which includes, but is not limited to, shallow trench etching, oxide filling, and oxide planarization.

[0053] Shallow trench etching includes, but is not limited to, isolating oxide layers, nitride deposition, shallow trench isolation using masks, and STI shallow trench etching. STI oxide filling includes, but is not limited to, trench liner silicon oxide, trench CVD (chemical vapor deposition) oxide filling, or PVD (physical vapor deposition) oxide filling. Silicon wafer surface planarization can be achieved through various methods. Planarization can be achieved by using SOG (spin-on-glass) to fill the gaps. SOG can be composed of 80% solvent and 20% silicon dioxide. After deposition, the SOG is baked to evaporate the solvent, leaving the silicon dioxide in the gaps. Alternatively, the entire surface can be reverse-etched to reduce the overall wafer thickness. Planarization can also be effectively achieved through CMP (chemical mechanical polishing) processes, including but not limited to polishing the trench oxides (using chemical mechanical polishing) and nitride removal.

[0054] A gate structure 301 is formed on the substrate 300. Exemplarily, the gate structure 301 includes a high-k dielectric layer, a work function metal layer, and a metal gate stacked from bottom to top, and the sidewalls of the gate structure 301 are formed with sidewall structures.

[0055] An interlayer dielectric layer 302 is formed on the substrate 300. Optionally, the material of the interlayer dielectric layer 302 may include, but is not limited to: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated carbon silicon oxide (SiCOH), porous SiCOH, borosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicones) including silicon (Si), carbon (C), oxygen (O) and / or hydrogen (H) atoms, thermosetting polyarylene ether, or other materials with low dielectric constant (<3.9).

[0056] A capping layer 303 and a sacrificial material layer 305 are sequentially formed on the interlayer dielectric layer 302. Exemplarily, the capping layer 303 and the sacrificial material layer 305 are formed by a deposition process, preferably plasma-enhanced chemical vapor deposition (PECVD). The material of the capping layer 303 may be silicon nitride, and the material of the sacrificial material layer 305 may be an oxide.

[0057] The thickness of the capping layer 303 is the distance between the top of the subsequently formed mid-section metal contact and the top of the gate structure 301. Typically, the thickness of the capping layer 303 is 205 angstroms to 215 angstroms, preferably 210 angstroms.

[0058] In step S2, as Figure 3B As shown, a contact groove 306 is formed to connect the source / drain of the device. As an example, the step of forming the contact groove 306 includes: forming a mask layer with a pattern of contact groove 306; using the mask layer as a mask, etching the sacrificial material layer 305, the interlayer dielectric layer 302 of the capping layer 303 until the source / drain of the device is exposed; and removing the mask layer.

[0059] In step S3, as Figure 3C As shown, a protective layer 307 is formed on the sidewall of the contact groove 306. As an example, the steps of forming the protective layer 307 include: forming the protective layer on the sidewall and bottom of the contact groove 306 by a deposition process; and removing the protective layer located at the bottom of the contact groove 306 by an etching process. Exemplarily, the material of the protective layer 307 may be silicon nitride.

[0060] In step S4, as Figure 3D As shown, a photoresist layer 308 with a contact via pattern is formed. As an example, the steps of forming the photoresist layer 308 with a contact via pattern include: sequentially forming a spin-coated carbon (SOC) layer 311, an anti-reflective coating (ARC) 312, and a photoresist layer on a sacrificial material layer 305; and forming the contact via pattern in the photoresist layer by a photolithography process.

[0061] In step S5, as Figure 3EAs shown, a contact via 309 is formed to connect the gate structure 301. As an example, the steps for forming the contact via 309 include: using a photoresist layer 308 with a contact via pattern as a mask, etching the anti-reflective coating 312, spin-coated carbon layer 311, sacrificial material layer 305, capping layer 303, and part of the interlayer dielectric layer 302 until the top of the gate structure 301 is exposed; removing the photoresist layer 308, anti-reflective coating 312, and spin-coated carbon layer 311. During this etching process, the capping layer 303 can serve as an etching stop layer, exposing the entire top of the gate structure 301 in one step at the final stage of etching, thus minimizing damage to the work function metal layer in the gate structure 301 during etching.

[0062] In step S6, as Figure 3E As shown, a pre-cleaning process is performed on the contact groove 306 and the contact via 309 to remove etching residues and impurities. As an example, the pre-cleaning process is performed using the SiCoNi process. Since a protective layer 307 is formed on the sidewall of the contact groove 306, and the lower part of the sidewall of the contact via 309 is a capping layer 303 and the upper part is a sacrificial material layer 305, the SiCoNi process only causes wear on the upper part of the sidewall of the contact via 309. Without changing the mid-section metal contact height, the worn portion (i.e., the portion where CD expands) is removed by a grinding process during the subsequent metal layer formation.

[0063] In step S7, as Figure 3F As shown, a metal layer 310 is formed in the contact groove 306 and the contact via 309. As an example, the steps for forming the metal layer 310 include: forming a Ti / TiN adhesive layer (not shown in the illustration for simplicity) on the sidewalls and bottom of the contact groove 306 and the contact via 309 by a deposition process; filling the contact groove 306 and the contact via 309 with the metal layer 310; and removing the sacrificial material layer 305 and the metal layer 310 within it by a grinding process until the capping layer 303 is exposed. Compared to the prior art which requires grinding a thicker interlayer dielectric layer, this grinding only requires removing a thinner sacrificial material layer 305, thus significantly improving the grinding load.

[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] In summary, the method for improving the excessive size of the intermediate metal contact via provided in this application can effectively prevent CD expansion caused by the wear of the contact via sidewalls during pre-cleaning treatment. It can also minimize the damage to the work function metal layer in the gate structure caused by etching and significantly reduce the load on the polishing performed after the formation of the intermediate metal contact. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0066] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this invention should still be covered by the claims of this application.

Claims

1. A method for improving the excessive size of intermediate metal contact through holes, characterized in that, The method includes: Step S1: A substrate is provided, on which a shallow trench isolation, a gate structure and an interlayer dielectric layer are formed, and a capping layer and a sacrificial material layer are sequentially formed on the interlayer dielectric layer; Step S2: Form contact grooves to connect the source / drain of the device; Step S3: A protective layer is formed on the sidewall of the contact groove; Step S4: Form a photoresist layer with a contact via pattern; Step S5: Form a contact via to connect the gate structure; Step S6: Perform pre-cleaning treatment on the contact groove and the contact through hole; Step S7: A metal layer is formed in the contact groove and the contact through hole.

2. The method according to claim 1, characterized in that, Step S7 includes: forming a Ti / TiN adhesive layer on the sidewalls and bottom of the contact groove and the contact via through a deposition process; filling the contact groove and the contact via through a metal layer; and removing the sacrificial material layer and the metal layer in the sacrificial material layer through a grinding process until the cover layer is exposed.

3. The method according to claim 1 or 2, characterized in that, The thickness of the covering layer is 205 angstroms to 215 angstroms.

4. The method according to claim 1, characterized in that, The material of the capping layer is silicon nitride, and the material of the sacrificial material layer is oxide.

5. The method according to claim 1, characterized in that, The protective layer is made of silicon nitride.

6. The method according to claim 1, characterized in that, Step S4 includes: sequentially forming a spin-coated carbon layer, an anti-reflective coating, and a photoresist layer on the sacrificial material layer; and forming a contact via pattern in the photoresist layer by photolithography.

7. The method according to claim 6, characterized in that, Step S5 includes: using a photoresist layer with the contact via pattern as a mask, etching the anti-reflective coating, the spin-coated carbon layer, the sacrificial material layer, the capping layer, and part of the interlayer dielectric layer to expose the top of the gate structure; and removing the photoresist layer, the anti-reflective coating, and the spin-coated carbon layer.

8. The method according to claim 7, characterized in that, The capping layer serves as an etch stop layer, ensuring that the final stage of the etching exposes the top of all the gate structures in one step, preventing damage to the work function metal layer in the gate structures from the etching.

9. The method according to claim 1, characterized in that, The pre-cleaning process was carried out using the SiCoNi process.

10. The method according to claim 1, characterized in that, The gate structure includes a high-k dielectric layer, a work function metal layer, and a metal gate stacked from bottom to top, and the sidewalls of the gate structure are formed with sidewall structures.

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