Method of board level packaging of semiconductor structures

By using a cutout board to reconstruct the wafer structure on the board-level equipment, the high precision requirements of wafer-level packaging are achieved, solving the problems of high equipment cost and insufficient processing accuracy in the existing technology, reducing packaging costs and avoiding wafer breakage and pad oxidation.

CN117198897BActive Publication Date: 2026-07-21CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
Filing Date
2022-06-01
Publication Date
2026-07-21

AI Technical Summary

Technical Problem

Existing packaging technologies require both wafer-level and board-level equipment, resulting in high costs. Furthermore, traditional methods cannot achieve the high precision requirements of wafer-level packaging on board-level equipment and suffer from problems such as wafer breakage and solder pad oxidation.

Method used

By using a cutout board to reconstruct the wafer into a board-level structure, and then using board-level equipment for wafer-level packaging, a conductive structure is formed by rewiring and molding on the cutout board. Finally, the substructure is cut to obtain the structure, which avoids the high cost and wafer breakage problems of traditional methods.

Benefits of technology

The high precision requirements of wafer-level packaging were achieved on board-level equipment, reducing costs and avoiding wafer breakage and pad oxidation during the molding process, thus improving processing accuracy and reliability.

✦ Generated by Eureka AI based on patent content.

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    Figure CN117198897B_ABST
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Abstract

The application provides a board-level packaging method of a semiconductor structure, comprising the following steps: providing a plurality of wafers, a hollow plate and a first carrier plate, the hollow plate is provided with a plurality of hollow positions, the size of the hollow position is slightly larger than the wafer, the hollow plate is attached to the first carrier plate, the front surface of the wafer is provided with a plurality of first solder pads, the wafer is aligned with the hollow position and attached to the first carrier plate; forming a first plastic encapsulation layer which covers at least the side surface of the wafer; removing the first carrier plate to obtain a first plastic encapsulation structure and attaching the first plastic encapsulation structure to a second carrier plate; forming a conductive structure to obtain a semiconductor intermediate structure; and cutting the semiconductor intermediate structure to obtain a plurality of sub-structures. The wafer is reconfigured by the hollow plate to form a board level, and then the wafer level packaging is realized by the board-level packaging, that is, the wafer level packaging can be realized under the condition of only board-level equipment, thereby the cost can be reduced, and the problem of wafer fragmentation is avoided.
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