Semiconductor structure and method of manufacturing the same

Abstract

This disclosure provides a semiconductor structure and its fabrication method. The fabrication method includes: providing a substrate; forming a sacrificial dielectric layer on the substrate; patterning a portion of the sacrificial dielectric layer along a first direction; forming a plurality of first trenches spaced apart along a second direction in the sacrificial dielectric layer; patterning the sacrificial dielectric layer at the bottom of the first trenches and the substrate below the sacrificial dielectric layer; forming a plurality of second trenches spaced apart below the first trenches, the second trenches having a predetermined depth in the substrate; forming protective layers on the sidewalls of the first and second trenches; and forming bit line structures in the first and second trenches. The bit line structure formed by the fabrication method of this disclosure has a smaller critical dimension and does not twist or collapse. Furthermore, the sacrificial dielectric layer does not need to be removed and can be used in subsequent processes, saving costs.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and its preparation method. Background Technology

[0002] As semiconductor device density increases, the required pattern spacing and width gradually decrease, leading to a shrinking of the feature size of Dynamic Random Access Memory (DRAM). In related technologies, during the fabrication of DRAM bitline structures, the high aspect ratio of the bitline structures makes them prone to bending and deformation during etching.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute related technology known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, an embodiment of this disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate and forming a sacrificial dielectric layer on the substrate; patterning a portion of the sacrificial dielectric layer along a first direction and forming a plurality of first trenches spaced apart along a second direction in the sacrificial dielectric layer; patterning the sacrificial dielectric layer at the bottom of the first trenches and the substrate below the sacrificial dielectric layer, forming a plurality of second trenches spaced apart below the first trenches, the second trenches having a predetermined depth in the substrate; forming a protective layer on the sidewalls of the first trenches and the sidewalls of the second trenches; and forming bit line structures in the first trenches and the second trenches.

[0005] According to some embodiments of the present disclosure, forming a sacrificial dielectric layer on the substrate includes: forming a first sacrificial dielectric layer on the substrate; and forming a second sacrificial dielectric layer on the first sacrificial dielectric layer.

[0006] According to some embodiments of this disclosure, a portion of the sacrificial medium layer is patterned along a first direction, and a plurality of first trenches spaced apart along a second direction are formed in the sacrificial medium layer, including: patterning a second sacrificial medium layer along a first direction, forming a plurality of first trenches spaced apart along a second direction in the second sacrificial medium layer, wherein a portion of the first sacrificial medium layer is exposed at the bottom of the first trenches.

[0007] According to some embodiments of this disclosure, the sacrificial dielectric layer at the bottom of the first trench and the substrate below the sacrificial dielectric layer are patterned, and a plurality of spaced second trenches are formed below the first trench, including: patterning the first sacrificial dielectric layer exposed by the first trench and the substrate at the bottom of the first sacrificial dielectric layer, and forming the second trenches in the first sacrificial dielectric layer and the substrate, wherein the second trenches have a first depth in a direction perpendicular to the substrate.

[0008] According to some embodiments of this disclosure, forming a protective layer on the sidewalls of the first trench and the second trench includes: forming a first protective layer that simultaneously covers the surface of the first trench and the surface of the second trench; forming a second protective layer on the surface of the first protective layer; forming a third protective layer on the surface of the second protective layer; removing the first, second, and third protective layers located on the bottom surface of the first trench and the bottom surface of the second trench to expose the substrate located at the bottom of the second trench; retaining the first, second, and third protective layers located on the sidewalls of the first trench and the second trench, wherein the retained first, second, and third protective layers form the protective layer.

[0009] According to some embodiments of this disclosure, forming a bit line structure in the first trench and the second trench includes: forming a bit line contact layer in the second trench; forming a bit line conductive layer in the first trench, the bit line conductive layer being connected to the bit line contact layer; forming a bit line insulating layer in the first trench and on the bit line conductive layer; wherein the bit line contact layer, the bit line conductive layer, and the bit line insulating layer form the bit line structure.

[0010] According to some embodiments of this disclosure, in a direction perpendicular to the substrate, the thickness of the bit line contact layer is not less than a preset depth of the second trench in the substrate, and the thickness of the bit line contact layer is not greater than the first depth, and the top surface of the bit line insulating layer is not higher than the top surface of the second sacrificial dielectric layer.

[0011] According to some embodiments of this disclosure, after forming the bit line structure, the method further includes: forming a mask layer on the top surface of the second sacrificial dielectric layer, the bit line insulating layer, and the protective layer; patterning the mask layer to form a plurality of spaced patterned holes in the mask layer, the patterned holes exposing the top surface of the second sacrificial dielectric layer between adjacent bit line structures in the second direction, and the top surface of the second sacrificial dielectric layer between adjacent patterned holes in the first direction being covered by the mask layer; patterning the second sacrificial dielectric layer and the first sacrificial dielectric layer located below the second sacrificial dielectric layer along the patterned holes, forming a third trench in the first sacrificial dielectric layer and the second sacrificial dielectric layer, the bottom surface of the third trench exposing the surface of the substrate between adjacent bit line structures in the second direction; and forming a capacitive contact structure in the third trench.

[0012] According to some embodiments of this disclosure, after forming the bit line structure, the method further includes: forming a mask layer on the top surface of the second sacrificial dielectric layer, the bit line insulating layer, and the protective layer; patterning the mask layer to form a plurality of spaced patterned holes in the mask layer, the patterned holes exposing the top surface of the second sacrificial dielectric layer and the top surface of the protective layer between adjacent bit line structures in the second direction, the top surface of the second sacrificial dielectric layer between adjacent patterned holes in the first direction being covered by the mask layer; patterning the second sacrificial dielectric layer and the first sacrificial dielectric layer located below the second sacrificial dielectric layer along the patterned holes, forming a third trench in the first sacrificial dielectric layer and the second sacrificial dielectric layer, while removing the second protective layer in the protective layer, the bottom surface of the third trench exposing the surface of the substrate between adjacent bit line structures in the second direction; and forming a capacitive contact structure in the third trench.

[0013] According to some embodiments of this disclosure, patterning the mask layer to form a plurality of spaced-apart patterned holes includes: forming a first mask layer having a plurality of first patterns extending along a first direction and spaced-apart along a second direction, the first patterns covering the bit line structure; forming a second mask layer on the first mask layer, the second mask layer having a plurality of second patterns extending along the second direction and spaced-apart along the first direction; transferring the second patterns into the first mask layer, the portion of the first mask layer not covered by the first and second patterns being removed to form the patterned holes.

[0014] According to some embodiments of this disclosure, the first mask layer and the second sacrificial medium layer have the same material. The second sacrificial medium layer and the first sacrificial medium layer located below the second sacrificial medium layer are patterned along the patterned hole. When the third trench is formed in the first sacrificial medium layer and the second sacrificial medium layer, the first mask layer is removed simultaneously.

[0015] According to some embodiments of this disclosure, the method further includes: patterning the second sacrificial dielectric layer along the patterned hole, removing the second protective layer using a dry etching process, and then patterning the first sacrificial dielectric layer.

[0016] According to some embodiments of this disclosure, forming a capacitor contact structure in the third trench includes: forming a capacitor contact layer on the surface of the substrate at the bottom of the third trench; and forming a metal connection layer on the capacitor contact layer.

[0017] According to some embodiments of this disclosure, the second protective layer and the second sacrificial medium layer have the same material, and the first protective layer and the third protective layer have the same material.

[0018] According to another aspect of this disclosure, a semiconductor structure is provided, which is prepared by the method described in any of the above embodiments.

[0019] As can be seen from the above technical solution, this disclosure possesses at least one of the following advantages and positive effects: In this embodiment, a first trench and a second trench are first formed in the sacrificial dielectric layer and the semiconductor substrate, and then bit line structures are formed by filling the first and second trenches. Therefore, the bit line structures in this embodiment are not formed directly by etching, but by filling the trenches. This allows the bit line structures to have smaller critical dimensions, avoids sidewall oxidation of the bit line structures, and prevents the bit line structures from twisting or collapsing. Furthermore, after forming the bit line structures, the sacrificial dielectric layer does not need to be removed and can be used in subsequent processes for forming capacitor contact structures, saving costs. Attached Figure Description

[0020] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0021] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 2 This is a cross-sectional view of a semiconductor structure having a substrate and a sacrificial dielectric layer in a second direction, as shown in an embodiment of this disclosure. Figure 3This is a top view of a semiconductor structure with bit line patterns formed on photoresist, as shown in an embodiment of this disclosure; Figure 4 for Figure 3 A cross-sectional view along the middle AA (i.e., a cross-sectional view of the semiconductor structure in the second direction). Figure 5 This is a cross-sectional view in a second direction of a semiconductor structure in which a sidewall sacrificial material layer is formed on a photoresist, as shown in an embodiment of the present disclosure. Figure 6 This is a cross-sectional view in a second direction of a patterned sidewall sacrificial layer semiconductor structure shown in an embodiment of the present disclosure. Figure 7 This is a cross-sectional view in a second direction of a patterned sidewall sacrificial layer semiconductor structure shown in an embodiment of the present disclosure. Figure 8 This is a cross-sectional view in a second direction of a semiconductor structure in which a first trench is formed by patterning a second sacrificial dielectric layer, as shown in an embodiment of this disclosure. Figure 9 This is a top view of a semiconductor structure in which a second trench is formed after the first sacrificial dielectric layer is patterned, as shown in an embodiment of this disclosure. Figure 10 For along Figure 9 Cross-sectional view of AA (i.e., cross-sectional view of the semiconductor structure in the second direction). Figures 11 to 13 This is a cross-sectional view in a second direction of a semiconductor structure having a first protective layer, a second protective layer, and a third protective layer formed respectively, as shown in an embodiment of this disclosure. Figure 14 This is a top view of the semiconductor structure forming the second trench as shown in an embodiment of this disclosure; Figure 15 For along Figure 14 Sectional view of AA; Figures 16 to 17 This is a cross-sectional view in a second direction of a semiconductor structure forming a bit line contact layer, as shown in an embodiment of this disclosure. Figures 18 to 19 This is a cross-sectional view in a second direction of a semiconductor structure forming a bit line conductive layer, as shown in an embodiment of this disclosure. Figures 20 to 21 This is a cross-sectional view of a semiconductor structure forming a bit line insulating layer in a second direction, as shown in an embodiment of this disclosure. Figure 22 This is a cross-sectional view of a semiconductor structure forming a bit line structure shown in an embodiment of the present disclosure in a first direction; Figure 23 This is a cross-sectional view in a second direction of the semiconductor structure forming the mask layer shown in this embodiment of the present disclosure; Figure 24This is a top view showing the formation of patterned holes in the mask layer according to an embodiment of the present disclosure; Figure 25 This is a cross-sectional view in the second direction of the semiconductor structure forming the third trench shown in this embodiment of the present disclosure; Figure 26 This is a cross-sectional view in a second direction of the semiconductor structure forming a capacitive contact structure shown in this embodiment of the present disclosure.

[0022] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Sacrificial dielectric layer; 21. First sacrificial dielectric layer; 22. Second sacrificial dielectric layer; 23. Hard mask layer; 24. Etch stop layer; 25. Photolithography anti-reflection layer; 251. First photolithography anti-reflection layer; 252. Second photolithography anti-reflection layer; 26. Photoresist layer; 27. Sidewall sacrificial layer; 3. Protective layer; 31. First protective layer; 32. Second protective layer; 33. Third protective layer; 4. Bit line structure; 41. Bit line contact material layer; 2. Bit line contact layer; 43. Conductive material layer; 44. Bit line conductive layer; 45. Insulating material layer; 46. Bit line insulating layer; 5. Mask layer; 51. First mask layer; 52. Second mask layer; 6. Capacitor contact structure; 61. Capacitor contact layer; 62. Metal connection layer; L1. First direction; L2. Second direction; G1. First trench; G2. Second trench; G3. Third trench; d1. Preset depth; d2. First depth; h. Pattern hole. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0024] In the following description of various exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe various exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used merely as illustrative marks and are not intended to limit the numerical scope of the object.

[0025] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0026] Furthermore, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating location, which are used merely for clarity and are not intended to be limiting.

[0027] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided. For example... Figures 1 to 26 As shown. Among them, Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure is shown. Figures 2 to 26 A schematic diagram of the semiconductor structure in this fabrication method is shown. (See diagram below.) Figure 1 As shown, the method for fabricating the semiconductor structure according to an embodiment of this disclosure includes: Step S200: Provide substrate 1 and form sacrificial dielectric layer 2 on substrate 1.

[0028] Step S400: Pattern a portion of the sacrificial dielectric layer 2 along the first direction L1, and form a plurality of first trenches G1 arranged at intervals along the second direction L2 in the sacrificial dielectric layer 2.

[0029] Step S600: Pattern the sacrificial dielectric layer 2 at the bottom of the first trench G1 and the substrate 1 below the sacrificial dielectric layer 2, and form a plurality of second trenches G2 arranged at intervals below the first trench G1. The second trenches G2 have a preset depth d1 in the substrate 1.

[0030] Step S800: A protective layer 3 is formed on the sidewall of the first trench G1 and the sidewall of the second trench G2.

[0031] Step S1000: Form bit line structure 4 in the first trench G1 and the second trench G2.

[0032] In this embodiment, a first trench G1 and a second trench G2 are first formed in the sacrificial dielectric layer 2 and the semiconductor substrate 1. Then, the bit line structure 4 is formed by filling the first trench G1 and the second trench G2. Therefore, the bit line structure 4 in this embodiment is not formed directly by etching, but by filling the trenches. This allows the bit line structure 4 to have smaller critical dimensions and avoids sidewall oxidation, twisting, or collapse. Furthermore, after forming the bit line structure 4, the sacrificial dielectric layer 2 does not need to be removed and can be used in the subsequent process of forming the capacitor contact structure 6, saving costs.

[0033] The method for fabricating the semiconductor structure according to the embodiments of this disclosure will be described in detail below.

[0034] Step S200: Provide substrate 1 and form sacrificial dielectric layer 2 on substrate 1.

[0035] like Figure 2 As shown, the substrate 1 in this embodiment can be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, silicon-on-insulator, or germanium-on-insulator, etc. Depending on design requirements, certain dopant particles can be implanted into the substrate 1 to change its electrical parameters. Those skilled in the art can select the implantation process and dopant particles based on actual conditions, and these will not be described in detail here.

[0036] In some embodiments, a sacrificial dielectric layer 2 can be formed on a substrate 1 by a deposition process, including: forming a first sacrificial dielectric layer 21 on the substrate 1, and forming a second sacrificial dielectric layer 22 on the first sacrificial dielectric layer 21. The first and second sacrificial dielectric layers 21 and 22 can be formed by atomic layer vapor deposition, chemical vapor deposition, or physical vapor deposition. In some embodiments, the first sacrificial dielectric layer 21 can be made of silicon nitride (such as Si3N4), and the second sacrificial dielectric layer 22 can be made of spin-coated silicon oxide (such as SiO2), and the thickness of the first sacrificial dielectric layer 21 is less than the thickness of the second sacrificial dielectric layer 22 in the direction perpendicular to the substrate 1. The direction perpendicular to the substrate 1 can be understood as the stacking direction of the first and second sacrificial dielectric layers 21, or it can also be referred to as the vertical direction.

[0037] In some embodiments, such as Figure 2As shown, in addition to forming a first sacrificial dielectric layer 21 and a second sacrificial dielectric layer 22 on the substrate 1, a hard mask layer 23, an etch stop layer 24, a photolithography anti-reflection layer 25, and a photoresist layer 26 can be sequentially formed on the second sacrificial dielectric layer 22. The photolithography anti-reflection layer 25 may include a first photolithography anti-reflection layer 251 located on the etch stop layer 24 and a second photolithography anti-reflection layer 252 located on the first photolithography anti-reflection layer 251. Of course, the photolithography anti-reflection layer 25 may also consist of only one layer; no special limitation is made here. The etch stop layer 24 may be made of silicon nitride (such as SiON) or silicon oxynitride (such as Si3N4).

[0038] Step S400: Pattern a portion of the sacrificial dielectric layer 2 along the first direction L1, and form a plurality of first trenches G1 arranged at intervals along the second direction L2 in the sacrificial dielectric layer 2.

[0039] In some embodiments, such as Figure 3 and Figure 4 As shown, the photoresist layer is photolithographically etched and developed along the first direction L1 to form a photoresist layer 26 with a bit line pattern. In the direction perpendicular to the substrate 1, the portion covered by the bit line pattern is used to form the bit line structure 4 in subsequent processes. For example... Figure 5 As shown, using the photoresist layer 26 with the bit line pattern as a mask, the bit line pattern is transferred to the photolithographic anti-reflection layer 25, exposing the etch stop layer 24 that is not covered by the bit line pattern. (Continue to the previous section) Figure 5 A sidewall sacrificial layer 27 is formed on the surface of the exposed etch stop layer 24 and the surface of the patterned photolithographic antireflective layer 25. The sidewall sacrificial layer 27 can be formed by a deposition process and its material can be silicon oxide (SiO2) or silicon oxynitride (such as SiON).

[0040] like Figure 6 As shown, the sidewall sacrificial layer 27 located on the photolithographic anti-reflection layer 25 and the sidewall sacrificial layer 27 located on the exposed etch stop layer 24 surface are removed using a dry etching process, while retaining the sidewall sacrificial layer 27 located on the sidewall of the photolithographic anti-reflection layer 25. The photolithographic anti-reflection layer 25 is then removed using a dry ashing method, forming a layer as shown... Figure 6 The sidewall sacrificial layers 27 are shown in an intermittent distribution.

[0041] like Figure 7 As shown, using the aforementioned spaced sidewall sacrificial layer 27 as a mask, the pattern is transferred to the etch stop layer 24 and hard mask layer 23 located below it.

[0042] like Figure 8As shown, a second sacrificial dielectric layer 22 is patterned along a first direction L1, and multiple first trenches G1 are formed in the second sacrificial dielectric layer 22 at intervals along a second direction L2. A portion of the first sacrificial dielectric layer 21 is exposed at the bottom of the first trenches G1. The patterning of the second sacrificial dielectric layer 22 along the first direction L1 can be achieved using an etching process, which can be either wet etching or dry etching; no particular limitation is made here. The first trenches G1 are used to fill and form a portion of the bitline structure 4. Therefore, by controlling the critical dimensions of the first trenches G1, the critical dimensions of the bitline structure 4 can be precisely controlled, resulting in a bitline structure 4 with smaller critical dimensions. Furthermore, since the bitline structure 4 is filled in the first trenches G1, no further etching is required, and no distortion or collapse occurs when the critical dimensions of the formed bitline structure 4 are reduced.

[0043] It should be noted that, in this embodiment of the disclosure, patterning refers to removing portions of the semiconductor structure according to a certain pattern; for example, patterning can be performed using etching processes. Furthermore, the key dimensions of the bit line structure 4 in this embodiment of the disclosure refer to the dimensions of the bit line structure 4 along the second direction L2, such as... Figure 22 The dimensions of the bitline structure from left to right in the cross-sectional view shown are as follows. There is an angle between the first direction L1 and the second direction L2. In some embodiments, the first direction L1 is perpendicular to the second direction L2, but this is not specifically limited here.

[0044] Step S600: Pattern the sacrificial dielectric layer 2 at the bottom of the first trench G1 and the substrate 1 below the sacrificial dielectric layer 2, and form a plurality of second trenches G2 arranged at intervals below the first trench G1. The second trenches G2 have a preset depth d1 in the substrate 1.

[0045] like Figure 9 and Figure 10 As shown, a first sacrificial dielectric layer 21 exposed by a first trench G1 and a substrate 1 at the bottom of the first sacrificial dielectric layer 21 are patterned. A second trench G2 is formed in the first sacrificial dielectric layer 21 and the substrate 1, wherein the second trench G2 has a first depth d2 in a direction perpendicular to the substrate 1.

[0046] That is, a plurality of second trenches G2 are formed at intervals along the first direction L1 at the bottom of each first trench G1. In some embodiments, referencing Figure 9 In the top view, the multiple second grooves G2 are arranged in a matrix. Of course, in other embodiments, the multiple second grooves G2 may not be arranged in a matrix. The number of second grooves G2 distributed along the first direction L1 at the bottom of each first groove G1 may be equal or unequal, and can be set according to the actual situation. No special limitation is made here.

[0047] Additionally, it should be noted that the second trench G2 extends from the top surface of the first sacrificial dielectric layer 21 to a predetermined depth d1 of the substrate 1. This predetermined depth d1 is the depth etched downwards from the surface of the substrate 1, which can also be understood as the dimension of the substrate 1 etched in the direction perpendicular to the substrate 1. The first depth d2 is the dimension from the top surface of the first sacrificial dielectric layer 21 to the bottom surface of the substrate 1 with the predetermined depth d1, that is, the dimension of the entire second trench G2 in the direction perpendicular to the substrate 1. Therefore, the value of the first depth d2 is greater than the value of the predetermined depth d1. From a top view, the cross-section of the second trench G2 can be rectangular, square, or circular, without special limitation here. That is, the sidewalls of the second trench G2 surround the outer periphery of the bottom surface of the second trench G2; therefore, the shape of the second trench G2 can also be understood as a hole.

[0048] The second trench G2 is used to form the bit line contact layer 42 of the bit line structure 4. The bit line contact layer 42 can be made of polysilicon. Therefore, the polysilicon bit line contact layer 42 can be directly deposited in the second trench G2 through a deposition process without etching the bit line contact layer 42, thus avoiding sidewall oxidation and ensuring the stability of the bit line structure 4.

[0049] Step S800: A protective layer 3 is formed on the sidewall of the first trench G1 and the sidewall of the second trench G2.

[0050] like Figure 11 As shown, a first protective layer 31 is formed that simultaneously covers the surfaces of the first trench G1 and the second trench G2. Figure 12 As shown, a second protective layer 32 is formed on the surface of the first protective layer 31. Figure 13 As shown, a third protective layer 33 is formed on the surface of the second protective layer 32.

[0051] like Figure 14 and Figure 15 As shown, the first protective layer 31, the second protective layer 32, and the third protective layer 33 located on the bottom surface of the first trench G1 and the bottom surface of the second trench G2 are removed, exposing the substrate 1 located at the bottom of the second trench G2. The first protective layer 31, the second protective layer 32, and the third protective layer 33 located on the sidewalls of the first trench G1 and the second trench G2 are retained. The retained first protective layer 31, the second protective layer 32, and the third protective layer 33 form the aforementioned protective layer 3.

[0052] In some embodiments, a deposition process can be used to form a first protective layer 31, a second protective layer 32, and a third protective layer 33, respectively. The first protective layer 31 and the third protective layer 33 can be made of silicon nitride (such as Si3N4) or silicon oxynitride (SiON), and the second protective layer 32 can be made of silicon oxide (such as SiO2).

[0053] In some embodiments, the process used to remove the protective layer 3 located on the bottom surface of the first trench G1 and the bottom surface of the second trench G2 is a dry etching process. The etching gas used in the dry etching process can be hydrogen fluoride or chlorine gas, and the degree of etching can be controlled by controlling the amount of etching gas used.

[0054] Step S1000: Form bit line structure 4 in the first trench G1 and the second trench G2.

[0055] like Figure 16 As shown, a bit line contact material layer 41 can be formed in the second trench G2 and the first trench G1 using a deposition process. This deposition process can be atomic layer deposition (ALD). The material of the bit line contact material layer 41 can be doped polycrystalline silicon. Figure 17 As shown, the bit line contact material layer 41 is etched back into the second trench G2, forming a bit line contact layer 42 in the second trench G2. Specifically, in the direction perpendicular to the substrate 1, the thickness of the bit line contact layer 42 is not less than a predetermined depth d1 of the second trench G2 in the substrate 1, and the thickness of the bit line contact layer 42 is not greater than a first depth d2 of the second trench G2. That is, the top surface of the bit line contact layer 42 is not lower than the top surface of the substrate 1, and not higher than the top surface of the first sacrificial dielectric layer 21. This ensures that the bit line contact layer 42 is completely formed in the second trench G2. A dry etching process can be used to etch back the bit line contact material layer 41, controlling the remaining amount of bit line contact material layer 41 by fixing the etching time, to serve as the connection line of the bit line structure 4. Using a dry etching process to etch the bit line contact material layer 41 provides a higher selectivity for polysilicon bit line contact material layer 41 compared to the sacrificial dielectric layer 2, avoiding damage to the sacrificial dielectric layer 2 and the protective layer 3.

[0056] like Figure 18 As shown, a conductive material layer 43 is formed on the bit line contact layer 42. Specifically, it can be formed using a chemical vapor deposition process. The conductive material layer 43 can be made of tungsten, titanium, nickel, aluminum, or platinum, and those skilled in the art can choose according to the actual situation; no special limitation is made here.

[0057] like Figure 19 As shown, the conductive material layer 43 is etched back to form a bit line conductive layer 44 in the first trench G1, and the bit line conductive layer 44 is connected to the bit line contact layer 42. The top surface of the bit line conductive layer 44 is lower than the top surface of the second sacrificial dielectric layer 22, that is, the bit line conductive layer 44 is located within the first trench G1. In one embodiment, as... Figure 19 As shown, the thickness of the bit line conductive layer 44 in the direction perpendicular to the substrate 1 is less than the thickness of the bit line contact layer 42. The bit line conductive layer 44 is the effective conductive structure in the bit line structure 4.

[0058] In some embodiments, a dry etching process can be used to etch back the conductive material layer 43, and the remaining amount of the conductive material layer 43 can be controlled by adjusting the etching time. The dry etching process is not only simple to operate, but also has a higher etching selectivity for the conductive material layer 43 of the metal compared to the second sacrificial dielectric layer 22 and the protective layer 3, thus avoiding damage to the second sacrificial dielectric layer 22 and the protective layer 3.

[0059] like Figure 20 As shown, an insulating material layer 45 is formed on the bit line conductive layer 44. In some embodiments, the insulating material layer 45 can be formed by deposition using a furnace tube. The insulating material layer 45 can be made of silicon nitride (such as Si3N4). In some embodiments, the insulating material layer 45 can be made of the same material as the first sacrificial dielectric layer 21, which is silicon nitride.

[0060] like Figure 21 As shown, the insulating material layer 45 can be etched using a dry etching process, with the second sacrificial dielectric layer 22 as the etching stop layer, completely exposing the second sacrificial dielectric layer 22. A bit line insulating layer 46 is formed in the first trench G1 and on the bit line conductive layer 44. The top surface of the bit line insulating layer 46 is not higher than the top surface of the second sacrificial dielectric layer 22. In one embodiment, the top surface of the bit line insulating layer 46 is flush with the exposed top surface of the second sacrificial dielectric layer 22. The bit line contact layer 42, bit line conductive layer 44, and bit line insulating layer 46 in the above embodiment form the bit line structure 4. To illustrate the bit line structure 4 more clearly, refer to... Figure 22 It shows a cross-sectional view of a semiconductor structure in the first direction L1.

[0061] As can be seen from the above, the bit line structure 4 in this embodiment is formed by filling the second groove G2 and the first groove G1, where the protective layer 3 is formed on the sidewall. Since the dimensions of the first groove G1 and the second groove G2 can be controlled more precisely, the bit line structure 4 in this embodiment can have smaller critical dimensions and is less prone to deformation, thus improving stability.

[0062] After forming the bit line structure 4, the capacitor contact structure 6 can be formed. In some embodiments, the preparation method further includes steps S1200 to S1800.

[0063] Step S1200: Form mask layer 5, which is formed on the top surface of the second sacrificial dielectric layer 22, bit line insulating layer 46 and protective layer 3.

[0064] like Figure 23As shown, a mask layer 5 can be formed on the top surface of the second sacrificial dielectric layer 22, the top surface of the bit line insulating layer 46, and the top surface of the protective layer 3. This mask layer 5 can be formed using a chemical vapor deposition process. In some embodiments, such as... Figure 23 As shown, the mask layer 5 may include a first mask layer 51 and a second mask layer 52 stacked sequentially. In other embodiments, the mask layer 5 may also include only the first mask layer 51. The material of the first mask layer 51 may be silicon oxide (such as SiO2), and the material of the second mask layer 52 may be silicon nitride (such as Si3N4) or silicon oxynitride (such as SiON).

[0065] Step S1400: As Figure 24 As shown, a patterned mask layer 5 is formed in which a plurality of patterned holes h are spaced apart. The patterned holes h expose the top surface of the second sacrificial dielectric layer 22 between adjacent bit line structures 4 in the second direction L2, and the top surface of the second sacrificial dielectric layer 22 between adjacent patterned holes h in the first direction L1 is covered by the mask layer 5. In some embodiments, step S1400 may specifically include steps S1401 to S1403.

[0066] Step S1401: Form the first mask layer 51 described above. The first mask layer 51 has multiple first patterns that extend along the first direction L1 and are spaced apart along the second direction L2. The first patterns cover the bit line structure 4.

[0067] The first mask layer 51 is patterned. Specifically, the portion of the first mask layer 51 that is not covered by the bit line structure 4 is etched along the first direction L1. The remaining portion of the first mask layer 51 forms multiple first patterns extending along the first direction L1 and spaced apart along the second direction L2, such that the first patterns can completely cover the bit line structure 4 located below them. A temporary material (not shown in the figure) is filled between the spaced-apart first patterns. In some embodiments, the temporary material is different from the material of the first mask layer 51.

[0068] Step S1402: A second mask layer 52 is formed on the first mask layer 51. The second mask layer 52 has a plurality of second patterns that extend along the second direction L2 and are spaced apart along the first direction L1.

[0069] A second mask layer 52 is formed on the first mask layer 51. The second mask layer 52 is patterned. Specifically, a portion of the second mask layer 52 is etched along the second direction L2 to retain multiple second patterns that extend along the first direction L1 and are spaced apart along the second direction L2.

[0070] Step S1403: As Figure 24As shown, the second pattern is transferred to the first mask layer 51. The portion of the first mask layer 51 not covered by the first and second patterns is removed, forming a patterned hole h. This removes the temporary material corresponding to the patterned hole in the first mask layer 51. Since the temporary material and the first mask layer 51 are made of different materials and have different etching selectivity, the temporary material corresponding to the patterned hole can be removed using an etching process without damaging the remaining first mask layer 51. Figure 24 As shown, multiple pattern holes h can be arranged in a matrix and located between adjacent bit line structures 4.

[0071] In other embodiments, the mask layer 5 includes only one first mask layer 51. The aforementioned patterned aperture h can be formed directly on the first mask layer 51. That is, the pattern with the patterned aperture h can be directly transferred to the first mask layer 51. Regarding the transfer of patterns, those skilled in the art can obtain relevant information based on related technologies, and will not be elaborated here.

[0072] Step S1600: As Figure 25 As shown, the second sacrificial dielectric layer 22 and the first sacrificial dielectric layer 21 located below the second sacrificial dielectric layer 22 are patterned along the pattern hole h, and a third trench G3 is formed in the first sacrificial dielectric layer 21 and the second sacrificial dielectric layer 22. The bottom surface of the third trench G3 exposes the surface of the substrate 1 between the adjacent bit line structures 4 in the second direction L2.

[0073] Using an etching process, the second sacrificial dielectric layer 22 and the first sacrificial dielectric layer 21 located below the second sacrificial dielectric layer 22 are etched away along the patterned aperture h, thereby forming a third trench G3 in the first sacrificial dielectric layer 21 and the second sacrificial dielectric layer 22. In some embodiments, the patterned aperture h is arranged in a matrix, so the third trench G3 is also arranged in a matrix.

[0074] In some embodiments, the first mask layer 51 and the second sacrificial dielectric layer 22 have the same material, such as both being SiO2. The second sacrificial dielectric layer 22 and the first sacrificial dielectric layer 21 located below the second sacrificial dielectric layer 22 are patterned along the patterned hole h. When the third trench G3 is formed in the first sacrificial dielectric layer 21 and the second sacrificial dielectric layer 22, the first mask layer 51 is removed simultaneously, which can save process time and improve efficiency.

[0075] In some embodiments, after patterning the second sacrificial dielectric layer 22 along the patterned hole h, the second protective layer 32 can be removed using a dry etching process, and then the first sacrificial dielectric layer 21 can be patterned. After removing the second protective layer 32, an air gap can be formed between the first protective layer 31 and the third protective layer 33, that is, the protective layer 3 of the bit line structure 4 has an air gap, which can reduce the parasitic capacitance between the bit line structures 4 and obtain good electrical performance.

[0076] Step S1800: Form a capacitor contact structure 6 in the third trench G3.

[0077] In other embodiments, the preparation method further includes steps S1200'~S1800'.

[0078] Step S1200': Form mask layer 5, which is formed on the top surface of the second sacrificial dielectric layer 22, bit line insulating layer 46 and protective layer 3.

[0079] Step S1400': Pattern mask layer 5, forming a plurality of spaced pattern holes h in mask layer 5, the pattern holes h exposing the top surface of the second sacrificial dielectric layer 22 between adjacent bit line structures 4 in the second direction L2 and the top surface of the protective layer 3, the top surface of the second sacrificial dielectric layer 22 between adjacent pattern holes h in the first direction L1 is covered by mask layer 5.

[0080] Step S1400' differs from step S1400. In step S1400, the patterned hole h of the mask layer 5 only exposes the top surface of the second sacrificial medium layer 22. However, in step S1400', the patterned hole h of the mask layer 5 exposes not only the top surface of the second sacrificial medium layer 22 but also the top surface of the protective layer 3. In subsequent steps, the second protective layer 32 in the protective layer 3 can be removed while the second sacrificial medium layer 22 is being removed.

[0081] The process of forming the patterned hole h in step S1400' is the same as steps S1401 to S1403 in step S1400, and will not be repeated here.

[0082] Step S1600': Pattern the second sacrificial dielectric layer 22 and the first sacrificial dielectric layer 21 located below the second sacrificial dielectric layer 22 along the pattern hole h, form a third trench G3 in the first sacrificial dielectric layer 21 and the second sacrificial dielectric layer 22, and remove the second protective layer 32 in the protective layer 3. The bottom surface of the third trench G3 exposes the surface of the substrate 1 between the adjacent bit line structures 4 in the second direction L2.

[0083] Step S1600' differs from step S1600. In step S1600, since the protective layer 3 is not exposed by the pattern hole h, only the first sacrificial dielectric layer 21 and the second sacrificial dielectric layer 22 are removed during patterning to form the third trench G3; the second protective layer 32 is not removed. However, in step S1600', the top surface of the protective layer 3 is exposed by the pattern hole h. Therefore, the second protective layer 32 is removed simultaneously with the removal of the second sacrificial dielectric layer 22. That is, in step S1600', the second sacrificial dielectric layer 22 and the second protective layer 32 can be removed simultaneously. Compared to the above embodiment where the second sacrificial dielectric layer 22 is removed first and then the second protective layer 32, the process is simpler and saves time.

[0084] In this embodiment, the second protective layer 32 and the second sacrificial dielectric layer 22 have the same material, such as silicon oxide. The first protective layer 31 and the third protective layer 33 have the same material, such as silicon nitride. The second protective layer 32 and the second sacrificial dielectric layer 22 can be removed by etching. Because the second protective layer 32 is made of a different material than the first protective layer 31 and the third protective layer 33, the etchant or etching gas in the etching process has different etching selectivity for different materials. Therefore, the second protective layer 32 can be etched away without damaging the first protective layer 31 and the third protective layer 33.

[0085] After removing the second protective layer 32 and the second sacrificial dielectric layer 22, the first sacrificial dielectric layer 21 can be etched away. It should be noted that since the first sacrificial dielectric layer 21 can be made of silicon nitride, the etchant or etching gas needs to be replaced. Furthermore, when the first protective layer 31, the third protective layer 33, and the first sacrificial dielectric layer 21 are all made of silicon nitride, anisotropic etching can be used. This involves controlling the etching direction and etching away only the first sacrificial dielectric layer 21, without etching the first protective layer 31 and the third protective layer 33. This preserves the complete first protective layer 31 and the third protective layer 33, ultimately forming an air gap in the first protective layer 31 and the third protective layer 33. This air gap in the protective layer 3 of the final bit line structure 4 reduces the parasitic capacitance between the bit line structures 4, resulting in good electrical performance.

[0086] Step S1800': Form a capacitor contact structure 6 in the third trench G3.

[0087] Step S1200' is exactly the same as step S1200, and step S1800' is exactly the same as step S1800.

[0088] like Figure 26In steps S1800 and S1800', forming a capacitor contact structure 6 in the third trench G3 includes: forming a capacitor contact layer 61 on the surface of the substrate 1 at the bottom of the third trench G3, and forming a metal connection layer 62 on the capacitor contact layer 61.

[0089] Specifically, a capacitor contact material layer can be deposited first in the third trench G3, and then the capacitor contact material layer can be etched back to form a capacitor contact layer 61. The material of the capacitor contact layer 61 can be polysilicon. A metal interconnect layer 62 is deposited on the capacitor contact layer 61 in the third trench G3, and the metal interconnect layer 62 fills the third trench G3. Using a CMP (chemical mechanical polishing) process, the top surface of the metal interconnect layer 62, the top surface of the protective layer 3, and the top surface of the bit line insulating layer 46 are flush to facilitate the implementation of subsequent processes.

[0090] As can be seen from the above description, after the bit line structure 4 is formed, the sacrificial dielectric layer 2 located between the bit line structures 4 does not need to be removed, but can continue to be used in the subsequent capacitor contact structure 6 process to form the third trench G3 sacrificial dielectric layer 2. Therefore, it is not necessary to use spin coating process and chemical mechanical polishing process to prepare the above-mentioned sacrificial dielectric layer 2, thus saving costs.

[0091] In summary, in this embodiment of the present disclosure, a first trench G1 and a second trench G2 are first formed in the sacrificial dielectric layer 2 and the semiconductor substrate 1, and then the bit line structure 4 is formed by filling the first trench G1 and the second trench G2. Therefore, the bit line structure 4 in this embodiment of the present disclosure is not formed directly by etching, but by filling in the trenches. This allows the bit line structure to have a smaller critical dimension and avoids sidewall oxidation of the bit line structure 4, as well as distortion or collapse of the bit line structure 4. In addition, after the bit line structure 4 is formed, the sacrificial dielectric layer 2 does not need to be removed and can be used in the subsequent process of forming the capacitor contact structure 6, saving costs.

[0092] According to another aspect of this disclosure, a semiconductor structure is provided, including a substrate 1, a word line structure, a bit line structure 4, and a transistor. The transistor is disposed in the substrate 1 and has a gate, a drain, and a source. This semiconductor structure is fabricated by the fabrication method of any of the above embodiments, which will not be described further here.

[0093] The bit line structure 4 of the semiconductor structure in this embodiment can achieve smaller critical dimensions and is less prone to twisting or collapse, resulting in more stable electrical performance and lower cost.

[0094] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.

Claims

1. A method of fabricating a semiconductor structure, characterized by, include: A substrate is provided, on which a sacrificial dielectric layer is formed; The sacrificial dielectric layer is patterned along a first direction, and a plurality of first trenches are formed in the sacrificial dielectric layer at intervals along a second direction. The sacrificial dielectric layer at the bottom of the first trench and the substrate below the sacrificial dielectric layer are graphically represented. A plurality of second trenches are formed at intervals below the first trench, and the second trenches have a predetermined depth in the substrate. A protective layer is formed on the sidewalls of the first trench and the second trench; Bitline structures are formed in the first trench and the second trench.

2. The method of claim 1, wherein, Forming a sacrificial dielectric layer on the substrate includes: A first sacrificial dielectric layer is formed on the substrate; A second sacrificial medium layer is formed on the first sacrificial medium layer.

3. The method of claim 2, wherein, The second sacrificial medium layer is patterned along a first direction, and a plurality of first trenches are formed in the sacrificial medium layer at intervals along a second direction, including: patterning the second sacrificial medium layer along the first direction, forming a plurality of first trenches at intervals along the second direction in the second sacrificial medium layer, and exposing a portion of the first sacrificial medium layer at the bottom of the first trenches.

4. The method of claim 3, wherein, The process of patterning the sacrificial dielectric layer at the bottom of the first trench and the substrate below the sacrificial dielectric layer, and forming a plurality of spaced second trenches below the first trench, includes: patterning the first sacrificial dielectric layer exposed by the first trench and the substrate at the bottom of the first sacrificial dielectric layer, and forming the second trenches in the first sacrificial dielectric layer and the substrate, wherein the second trenches have a first depth in a direction perpendicular to the substrate.

5. The method of claim 2, wherein, A protective layer is formed on the sidewalls of the first trench and the second trench, comprising: A first protective layer is formed that simultaneously covers the surface of the first trench and the surface of the second trench; A second protective layer is formed on the surface of the first protective layer; A third protective layer is formed on the surface of the second protective layer; The first protective layer, the second protective layer, and the third protective layer located on the bottom surface of the first trench and the bottom surface of the second trench are removed to expose the substrate located at the bottom of the second trench. The first protective layer, the second protective layer, and the third protective layer located on the sidewalls of the first trench and the second trench are retained, and the retained first protective layer, the second protective layer, and the third protective layer form the protective layer.

6. The method of claim 5, wherein, Forming bitline structures in the first trench and the second trench includes: A bit line contact layer is formed in the second trench; A bit line conductive layer is formed in the first trench, and the bit line conductive layer is connected to the bit line contact layer; A bit line insulating layer is formed in the first trench and on the bit line conductive layer; wherein... The bit line contact layer, the bit line conductive layer, and the bit line insulating layer form the bit line structure.

7. The method of claim 6, wherein, In a direction perpendicular to the substrate, the second trench has a first depth, the thickness of the bit line contact layer is not less than a preset depth of the second trench in the substrate, and the thickness of the bit line contact layer is not greater than the first depth, and the top surface of the bit line insulating layer is not higher than the top surface of the second sacrificial dielectric layer.

8. The method of claim 7, wherein, After forming the bit line structure, the method further includes: A mask layer is formed on the top surface of the second sacrificial dielectric layer, the bit line insulating layer, and the protective layer; The mask layer is patterned, and a plurality of spaced patterned holes are formed in the mask layer. The patterned holes expose the top surface of the second sacrificial dielectric layer between adjacent bit line structures in the second direction, and the top surface of the second sacrificial dielectric layer between adjacent patterned holes in the first direction is covered by the mask layer. The second sacrificial dielectric layer and the first sacrificial dielectric layer located below the second sacrificial dielectric layer are patterned along the patterned hole, and a third trench is formed in the first sacrificial dielectric layer and the second sacrificial dielectric layer. The bottom surface of the third trench exposes the surface of the substrate between the adjacent bit line structures in the second direction. A capacitive contact structure is formed in the third trench.

9. The method of claim 7, wherein, After forming the bit line structure, the method further includes: A mask layer is formed on the top surface of the second sacrificial dielectric layer, the bit line insulating layer, and the protective layer; The mask layer is patterned, and a plurality of spaced patterned holes are formed in the mask layer. The patterned holes expose the top surface of the second sacrificial dielectric layer and the top surface of the protective layer between adjacent bit line structures in the second direction. The top surface of the second sacrificial dielectric layer between adjacent patterned holes in the first direction is covered by the mask layer. The second sacrificial dielectric layer and the first sacrificial dielectric layer located below the second sacrificial dielectric layer are patterned along the patterned hole, and a third trench is formed in the first sacrificial dielectric layer and the second sacrificial dielectric layer. At the same time, the second protective layer in the protective layer is removed, and the bottom surface of the third trench exposes the surface of the substrate between the adjacent bit line structures in the second direction. A capacitive contact structure is formed in the third trench.

10. The method according to claim 8 or 9, characterized in that, The mask layer is patterned to form a plurality of spaced-apart patterned holes, including: A first mask layer is formed, the first mask layer having a plurality of first patterns extending along the first direction and spaced apart along the second direction, the first patterns covering the bit line structure; A second mask layer is formed on the first mask layer, the second mask layer having a plurality of second patterns extending along the second direction and spaced apart along the first direction; The second pattern is transferred into the first mask layer, and the portion of the first mask layer not covered by the first and second patterns is removed to form the pattern hole.

11. The method according to claim 10, characterized in that, The first mask layer and the second sacrificial medium layer have the same material. The second sacrificial medium layer and the first sacrificial medium layer located below the second sacrificial medium layer are patterned along the patterned hole. When the third trench is formed in the first sacrificial medium layer and the second sacrificial medium layer, the first mask layer is removed at the same time.

12. The method according to claim 8, characterized in that, Also includes: After patterning the second sacrificial dielectric layer along the patterned holes, the second protective layer is removed using a dry etching process, and then the first sacrificial dielectric layer is patterned again.

13. The method according to claim 8 or 9, characterized in that, Forming a capacitive contact structure in the third trench includes: A capacitive contact layer is formed on the surface of the substrate at the bottom of the third trench; A metal connection layer is formed on the capacitor contact layer.

14. The method according to claim 9, characterized in that, The second protective layer and the second sacrificial medium layer have the same material, and the first protective layer and the third protective layer have the same material.

15. A semiconductor structure, characterized in that, Prepared by the method according to any one of claims 1 to 14.

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