A method for manufacturing a current monitoring unit integrated circuit based on a jfet device

Abstract

The application relates to a current monitoring unit integrated circuit manufacturing method based on a JFET device, a silicon epitaxial layer (4) is grown on a silicon substrate (1), one side of the silicon epitaxial layer is provided with a P-type buried layer (3), and the other side is provided with a P-channel region (16); the P-type buried layer is provided with a P-well (5), a P-type field region (8), an NLDD2 region (13), a lightly doped region NLDD1 region (14) and a PSUB region (15); the P-channel region is provided with a gate region (17) and a source-drain region (18); a silicon dioxide layer is provided with a metal interconnection structure (19) connected with corresponding devices; the P buried layer is processed below the NMOSFET and the PJFET device, the P-well is formed with a P-isolation ring at the same stage, the P buried layer and the P-isolation ring jointly enclose the active devices NMOSFET and PJFET, the parasitic NPN tube effect is fully inhibited, and the influence of the parasitic NPN tube on the circuit function is eliminated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, specifically a method for manufacturing an integrated circuit for a current monitoring unit based on a JFET device. Background Technology

[0002] Current monitoring units are commonly used to detect and control the current in circuits. For example, in a semiconductor solid-state self-resetting fuse circuit (patent application number 202111358866.6), the current monitoring unit is an important component of the circuit, connected in series in the protected circuit, and is used to monitor inrush current. When the current in the protected circuit reaches a set value, the current monitoring unit controls the normally open switch to close; when the current in the protected circuit is less than the set value, the current monitoring unit controls the normally open switch to open.

[0003] A search of existing patents revealed that the Chinese patent "A Manufacturing Method of a CMOS Low Dropout Voltage Regulator Integrated Circuit" does not have a buried P layer fabricated under the JFET and MOSFET devices, and the P isolation ring has not undergone high-temperature advancement, resulting in a very shallow junction depth. The isolation between devices mainly relies on the P well, which weakens the parasitic NPN transistor to some extent. However, due to the very low P well concentration, the reverse PN junction has a negligible effect on suppressing the parasitic NPN transistor. When one end of the circuit is subjected to a high voltage, the NMOS and PJFET on the other side will form a parasitic NPN transistor. When the voltage exceeds 0.5V, there is still a small current in the parasitic NPN transistor channel, causing abnormal circuit function. Summary of the Invention

[0004] The purpose of this invention is to provide a method for manufacturing an integrated circuit for a current monitoring unit based on a JFET device.

[0005] The present invention adopts the following technical solution: A method for manufacturing an integrated circuit for a current monitoring unit based on a JFET device includes the following steps: S1. A silicon oxide thin film of approximately 200 nm is grown on the surface of a silicon substrate using a thermal oxidation method; S2. A symmetrical P-type buried layer pattern is implanted on a silicon substrate using photolithography. S3. Etch the oxide layer on the surface of the silicon substrate to clean it, and then grow the silicon epitaxial layer; S4. An oxide film is formed on the surface of the epitaxial layer by thermal oxidation, and then photolithography and boron ion implantation are performed on one side of the oxide film to form a P-type well region; S5. Photolithography and boron ion implantation are performed on the silicon epitaxial layer to form symmetrically distributed P-type isolation rings. Two P-type isolation rings are provided on one side of the P-type well region, and two symmetrical P-type isolation rings are provided on the silicon epitaxial layer 4 on the other side. S6. High-temperature nitrogen pusher is used to ensure that the depth of the P-type well region and the P-type isolation ring junction reaches the design value; S7. Remove the oxide film, then grow a new buffer oxide layer by thermal oxidation, and deposit a silicon nitride film on top of the newly grown buffer oxide layer; S8. Using photolithography and etching processes, open up the active region on the silicon nitride layer; S9. Boron ions are implanted through the opened active region using photolithography and implantation processes to form two P-type field regions in the left P-type trap region; S10. Remove adhesive and clean, then use LOCOS local oxidation of silicon process to form isolation between each device; S11. Remove silicon nitride and silicon oxide from the surface of the epitaxial layer, and then perform NVT photolithography and implantation on the left P-type well region to form the NVT region; S12. Perform gate region oxidation to form an oxide layer; S13. A polysilicon layer with a thickness of 400nm is deposited on the surface of the oxide layer. P-type polysilicon and N-type polysilicon are formed by photolithography and implantation, respectively. Then, the designated area is patterned by photolithography and etching to form a P-type polysilicon resistor and an N-type polysilicon gate of an NMOS transistor. The N-type polysilicon gate corresponds to the NVT region, and the P-type polysilicon is set in the middle position. S14. Perform NLDD lightly doped drain implantation and drive-up. NLDD uses two photolithography and implantation processes. The first implantation is arsenic ions, which form two lightly doped regions of a certain width between the drain and the channel in the P-type well region, NLDD1 region. The second implantation is phosphorus ions, and the implanted region is farther away from the gate region than the arsenic ions, forming NLDD2 region. S15. A PSUB region and an N-type heavily doped NSD region are formed on a P-type well region on one side and a silicon epitaxial layer on the other side by photolithography and implantation, respectively. The PSUB region is used as the source and drain in an NMOS transistor on one side and as the back gate contact in a PJFET transistor on the other side. S16. Deposit and densify a silicon dioxide protective layer, perform photolithography and etching of silicon dioxide to form source and drain pre-etched holes and Pwell region pre-etched holes for N-channel MOSFET devices; on the other hand, open the active region of P-channel JFET devices. S17. After growing a silicon dioxide layer by thermal oxidation, the P-channel region, PSD source / drain region and JFET gate region of the P-channel JFET are formed on the silicon epitaxial layer on the other side by photolithography, etching and implantation steps. S18. After rapid annealing, a layer of TEOS (tetraethoxysilane) is deposited and densified. Finally, contact holes are etched on the surface, and metal is deposited and etched to form a metal interconnect structure.

[0006] The advantages of this invention are: This invention fabricates a P-buried layer beneath both NMOSFET and PJFET devices. Simultaneously, a P-isolation ring is formed during the same stage of P-well fabrication. Both undergo a long-term high-temperature process at 1200°C. The P-buried layer and the P-isolation ring together form a high-concentration closed loop that surrounds the active devices NMOSFET and PJFET, effectively suppressing the parasitic NPN transistor effect and eliminating the impact of the parasitic NPN transistor on circuit function.

[0007] This invention integrates three types of devices: a P-channel junction field-effect transistor (PJFET), an N-channel field-effect transistor (NMOSFET), and resistors. The source and drain regions of the PJFET are interchangeable. There is no explicitly defined minimum potential point in the circuit connection, and both ends of the circuit can withstand high voltage and high current surges. Current can flow bidirectionally, providing bidirectional monitoring characteristics; that is, it can monitor and control current regardless of whether it is input from the left or right side of the line. Therefore, this circuit can achieve bidirectional current monitoring and control, characterized by fast response speed and long service life. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of step 1 of the preparation method of the present invention; Figure 2 This is a schematic diagram of step 2 of the preparation method of the present invention; Figure 3 This is a schematic diagram of step 3 of the preparation method of the present invention; Figure 4 This is a schematic diagram of step 4 of the preparation method of the present invention; Figure 5 This is a schematic diagram of step 5 of the preparation method of the present invention; Figure 6 This is a schematic diagram of step 6 of the preparation method of the present invention; Figure 7 This is a schematic diagram of step 7 of the preparation method of the present invention; Figure 8 This is a schematic diagram of step 8 of the preparation method of the present invention; Figure 9 This is a schematic diagram of step 9 of the preparation method of the present invention; Figure 10 This is a schematic diagram of step 10 of the preparation method of the present invention; Figure 11 This is a schematic diagram of step 11 of the preparation method of the present invention; Figure 12 This is a schematic diagram of step 12 of the preparation method of the present invention; Figure 13 This is a schematic diagram of step 13 of the preparation method of the present invention; Figure 14 This is a schematic diagram of step 14 of the preparation method of the present invention; Figure 15 This is a schematic diagram of step 15 of the preparation method of the present invention; Figure 16 This is a schematic diagram of step 16 of the preparation method of the present invention; Figure 17 This is a schematic diagram of step 17 of the preparation method of the present invention; Figure 18 This is a schematic diagram of step 18 of the preparation method of the present invention; Figure 19 This is a schematic diagram of the current monitoring unit of a semiconductor solid-state self-resetting fuse (patent application number 202111358866.6). Detailed Implementation

[0009] This invention provides a method for manufacturing an integrated circuit for a current monitoring unit based on a JFET device, comprising the following manufacturing steps: 1. Use N-type <100> A silicon substrate 1 with a crystal orientation is on which a silicon oxide thin film 2 of approximately 200 nm is grown using a thermal oxidation method. Figure 1 As shown; 2. The pattern of the P-type buried layer 3 to be implanted is formed using photolithography, and buried layer implantation is performed. Impurity boron ions are implanted into the buried layer region of the silicon wafer at an energy of 90 keV and a dose of 1.7 E14 / cm2. Subsequently, buried layer annealing is performed under the following conditions: 1200℃, 500 minutes, N2. Figure 2 As shown; 3. Etch the oxide layer 2 on the surface of the silicon substrate to clean it, and then grow the silicon epitaxial layer 4, such as... Figure 3 As shown; 4. An oxide film 2-1 is formed on the surface of the epitaxial layer through thermal oxidation. Then, photolithography and boron ion implantation are performed on the left side of the oxide film 2-1. The implantation process conditions are: energy 200 keV, dose 1.5 E13 / cm2. A P-type well region 5 is formed in the silicon epitaxial layer 4. Figure 4 As shown; 5. Perform photolithography and implant boron ions. Implantation process conditions: energy 200keV, dose 9E15 / cm2. Form symmetrically distributed P-type isolation rings 6 on the silicon epitaxial layer 4. Two P-type isolation rings 6 are provided at the left P-type well region 5, and two symmetrical P-type isolation rings 6 are provided on the right silicon epitaxial layer 4. 6. A high-temperature push-in process using nitrogen (N2) at 1160℃ for 820 minutes was employed to ensure the junction depth of the P-type well region 5 and the P-type isolation ring 6 reached the design value; (e.g., ...) Figure 6 As shown; 7. Remove the oxide film 2-1 by wet etching, then grow a new buffer oxide layer 2-2 by thermal oxidation, and deposit a silicon nitride film 7 on top of the newly grown buffer oxide layer 2-2, as shown. Figure 7 As shown; 8. Using photolithography and etching processes, open up the active region in the silicon nitride layer, such as... Figure 8 The gap in the middle is shown; 9. By opening the active region, using photolithography and implantation processes, with implantation conditions of boron ions, energy of 50 keV, and dose of 5 E13 / cm2, two P-type field regions 8 are formed in the left P-type well region 5, as shown. Figure 9 As shown; 10. After removing the adhesive and cleaning, LOCOS (Local Oxidation of Silicon) process is used to form isolation between each device. Figure 10 Specifically, this involves the NMOSFET and PJFET devices forming isolation, such as... Figure 10 As shown, the process conditions for local oxidation of LOCOS silicon are 1040℃ for 30 min N2 + 10 min (H2 + O2). The patterned silicon nitride layer 7 is embedded downward into the oxide layer 2-2, and the oxide layer 2-2 below is embedded in the P-type field region 8 and each LOCOS region (the oxide layer 2-2 is also embedded downward in each isolation region in addition to 8).

[0010] 11. Remove the silicon nitride and silicon oxide from the epitaxial layer surface, leaving the remaining oxide layer 2-2 in the isolation region. Then, perform NVT photolithography and implantation on the left-side P-type well region 5 to form NVT region 9. The implantation conditions are boron impurities, energy 50 keV, and dose 1.5 E12 / cm2. This step is used to adjust the threshold voltage of the N-type MOSFET, such as... Figure 11 As shown; 12. Perform gate region oxidation to form an oxide layer 2-3, such as... Figure 12 As shown.

[0011] 13. Polysilicon with a thickness of 400 nm is deposited on the surface of oxide layer 2-3. P-type polysilicon and N-type polysilicon are formed by photolithography and implantation, respectively. Then, the designated area is patterned by photolithography and etching to form the P-type polysilicon resistor 10 and the N-type polysilicon gate 11 of the NMOS transistor, as shown below. Figure 13 As shown; from Figure 3 It can be seen that the N-type polysilicon gate 11 corresponds to the NVT region 9, and the P-type polysilicon 10 is set in the middle position.

[0012] 14. Perform NLDD lightly doped drain implantation and propulsion, such as... Figure 14As shown. NLDD employs two photolithography and implantation processes. The first implantation involves arsenic ions at an energy of 100 keV, a dose of 3E14 / cm², and an implantation angle of 0°. This creates two lightly doped regions of a certain width, NLDD1 region 14, between the drain and the channel (i.e., on the P-type well region 5), thereby reducing the peak electric field near the drain and weakening the hot carrier injection effect of the NMOS device, thus improving the drain breakdown voltage. The second implantation involves phosphorus ions at an energy of 100 keV, a dose of 5E13 / cm², and an implantation angle of 0°. This implanted region is further away from the gate region than the arsenic-implanted region, forming NLDD2 region 13. Because the first LDD arsenic ion implantation region acts as a connection between the source / drain active region and the channel, increasing the parasitic resistance of the source and drain, a second LDD photolithography and phosphorus ion implantation is used to reduce this parasitic resistance.

[0013] 15. Using photolithography and implantation, a PSUB region 15 and an N-type heavily doped NSD region 12 are formed on the left P-type well region 5 and the right silicon epitaxial layer 4, respectively. These regions serve as the source and drain in the left NMOS transistor and as the back gate contact in the right PJFET transistor. The NSD implantation conditions are arsenic ions: energy 100 keV, dose 5E15 / cm². The PSUB implantation conditions are boron ions: energy 50 keV, dose 3.5E15 / cm². Subsequently, an oxidation-progression process is performed with the following conditions: 980℃ for 10 min O₂ + 30 min (DCE + O₂) + 10 min O₂. Figure 15 As shown; 16. Deposit a 2-3 layer of silicon dioxide protective layer and densify it. Perform photolithography and etching of the silicon dioxide to form pre-etched holes for the source / drain of the N-channel MOSFET device and pre-etched holes for the Pwell region. Simultaneously, open the active region of the P-channel JFET device, such as... Figure 16 As shown, this process is crucial and ingenious. Removing all silicon dioxide layers from the active region surface of the P-channel JFET device, directly exposing the silicon surface, allows for precise control of the junction depth and concentration of the JFET's channel and gate regions during subsequent processing by injecting energy and dosage. This enables control over characteristic parameters such as the pinch-off voltage and saturation leakage current of the P-channel JFET. Simultaneously, if a thick silicon dioxide layer remains on the surface of the N-channel MOSFET device, the lead holes of the N-channel MOSFET and the P-channel JFET will not be on the same plane during subsequent lead hole photolithography, making it difficult to focus the lead hole photolithography process. Therefore, this process also removes the thick silicon dioxide protective layer from the source / drain region and Pwell region surface of the N-channel MOSFET device as a pre-etched hole.

[0014] 17. After growing a silicon dioxide layer by thermal oxidation, the PSD source / drain region 18 of the P-channel JFET, as well as the P-channel region 16 and the gate region 17 of the JFET, are formed on the right-side silicon epitaxial layer 4 through photolithography, etching, implantation, and other steps. Figure 17 As shown; the PSD source-drain region 18 is horizontally enclosed by the PSUB region 15, and the two are at the same center, so the vertical depth relationship is irrelevant; the gate region 17 of the JFET is embedded in the P-channel region 16, and the depth is determined according to the pinch-off voltage, saturation leakage current and other parameters of the JFET device. 18. After rapid annealing, a layer of TEOS (tetraethoxysilane) is deposited and densified. Finally, contact holes are etched on the surface, and metal is deposited and etched to form a metal interconnect structure. 19. Figure 18 As shown.

[0015] This invention integrates a P-channel junction field-effect transistor (PJFET), an N-channel field-effect transistor (NMOS), and polysilicon resistors on a CMOS process. Specifically, a P-buried layer is fabricated in the PJFET and NMOS regions before epitaxy. Simultaneously, a P-isolation ring is formed during P-well fabrication, which, together with the P-buried layer, forms a closed isolation ring, preventing the formation of parasitic NPN transistors from the NMOS and PJFET. The JFET channel region is fabricated separately after the MOSFET's LDD (Lightly Doped Drain) and NSD regions are fully formed, reducing fabrication difficulty and improving the process window. The NMOS transistor employs a double LDD process, improving both the device's breakdown voltage and reducing parasitic source and drain resistances. After the NMOS device is formed, the JFET's channel and gate regions are fabricated, facilitating precise control of the JFET's pinch-off voltage and saturation leakage current. This ensures that when the protected circuit current reaches a set value, the current monitoring unit controls the normally-on switch to achieve the protection function.

[0016] After testing and verification, the current monitoring unit integrated circuit based on JFET devices manufactured using this invention can avoid the formation of parasitic NPN between NMOS and PJFET in the current monitoring unit. The specific testing method is as follows: According to the patent for a semiconductor solid-state self-resetting fuse (patent application number 202111358866.6), the basic schematic diagram of the current monitoring unit is as follows: 1. In this current monitoring unit, there exists a parasitic NPN transistor, such as... Figure 19 The gate of the PJFET in the middle is the collector of the parasitic NPN, the P-well of the NMOS transistor (short-circuited to the source) is the base of the parasitic NPN, and the drain of the NMOS transistor is the emitter of the parasitic NPN. A schematic diagram of the parasitic NPN is shown in the attached figure.

[0017] 2. Ground S2 terminal, connect S1 terminal to 1V, connect the collector C terminal of the parasitic NPN transistor to 4V~8V respectively, so that the JFET transistor is pinched off, and the other terminals are left floating. Use a B1500A semiconductor device analyzer or a similar instrument to measure the collector current IC of the parasitic NPN transistor.

[0018] Table 3: Comparison of Parasitic Transistor Effect Test Data

[0019] 3. As shown in the table above, without this method, the parasitic NPN transistor collector current IC reaches 40.8μA~46.6μA. With this method, the parasitic NPN transistor collector current IC is only 3.4μA~5.8μA, a significant reduction. This indicates that the patented method can effectively reduce the conduction capability of parasitic NPN transistors and weaken the impact of parasitic interference on circuit performance.

Claims

1. A method for manufacturing an integrated circuit for a current monitoring unit based on a JFET device, characterized in that... Includes the following steps: S1. A silicon oxide thin film (2) is grown on the surface of a silicon substrate (1) by thermal oxidation. S2. A symmetrical P-type buried layer (3) pattern is implanted on a silicon substrate (1) using photolithography; S3. Etch the oxide layer on the surface of the silicon substrate (2), and then grow a silicon epitaxial layer on the silicon substrate (4). S4. A thin oxide film is formed on the surface of the epitaxial layer by thermal oxidation (2-1), and then photolithography and boron ion implantation are performed on one side of the epitaxial layer to form a P-type well region (5). S5. Photolithography and boron ion implantation are performed on the silicon epitaxial layer (4) to form symmetrically distributed P-type isolation rings (6), wherein two P-type isolation rings (6) are provided on one side of the P-type well region (5) and two symmetrical P-type isolation rings (6) are provided on the other side of the silicon epitaxial layer (4). S6. High-temperature nitrogen gas is used to push the trap, so that the junction depth of the P-type trap region (5) and the P-type isolation ring (6) reaches the design value; S7. Remove the oxide film (2-1), then grow a new buffer oxide layer (2-2) by thermal oxidation, and deposit a silicon nitride film (7) on top of the newly grown buffer oxide layer (2-2). S8. Using photolithography and etching processes, open the active region on the silicon nitride layer (7); S9. Boron ions are implanted through the open active region using photolithography and implantation processes to form two P-type field regions (8) in the left P-type trap region (5). S10. Remove adhesive and clean, then use LOCOS silicon local oxidation isolation process to form isolation between each device; S11. Remove silicon nitride and silicon oxide from the surface of the epitaxial layer, and then perform NVT lithography and implantation on the left P-type well region (5) to form the NVT region (9). S12. Perform gate region oxidation to form an oxide layer (2-3). S13. A polysilicon layer is deposited on the surface of the oxide layer (2-3). P-type polysilicon and N-type polysilicon are formed by photolithography and implantation, respectively. Then, the designated area is patterned by photolithography and etching to form a P-type polysilicon resistor (10) and an N-type polysilicon gate (11) of the NMOS transistor. The N-type polysilicon gate (11) corresponds to the NVT region (9). The P-type polysilicon (10) is set in the middle of the substrate. S14. Perform NLDD light doping implantation and propulsion. NLDD uses two photolithography and implantation processes. The first implantation is arsenic ions, which form two lightly doped regions of a certain width between the drain and the channel in the P-type well region (5), NLDD1 region (14). The second implantation is phosphorus ions, which are implanted in regions further away from the gate region than arsenic ions, forming NLDD2 region (13). S15. Using photolithography and implantation, a PSUB region (15) and an N-type heavily doped NSD region (12) are formed on a P-type well region (5) on one side and a silicon epitaxial layer (4) on the other side, respectively. The PSUB region is used as the source and drain in the NMOS transistor on one side of the P-type well region and as the contact region of the back gate in the PJFET transistor on the other side. S16. Deposit and densify the silicon dioxide protective layer (2-3), perform photolithography and etching of silicon dioxide, on the one hand forming the source and drain pre-etched holes and Pwell region pre-etched holes of the N-channel MOSFET device; on the other hand, open the active region of the P-channel JFET device. S17. After growing a silicon dioxide layer by thermal oxidation, the P-channel region (16), PSD source / drain region (18) and gate region (17) of the P-channel JFET are formed on the silicon epitaxial layer (4) on the other side by photolithography, etching and implantation steps. S18. After rapid annealing, a layer of tetraethoxysilane is deposited and densified. Finally, contact holes are etched on the surface, metal is deposited and metal interconnect structure is formed by etching (19).

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