3D CMOS Devices and Their Fabrication Methods

Abstract

A 3D CMOS device and its fabrication method are disclosed. The 3D CMOS device includes: a first insulating layer; a first vertical gate and a second vertical gate disposed on the front surface of the first insulating layer; a second insulating layer covering the front surface of the first insulating layer; a first via penetrating the second insulating layer, the first vertical gate, and the first insulating layer; and a second via penetrating the second insulating layer, the second vertical gate, and the first insulating layer; a first active region and a second active region filling the first via and the second via; a first source / drain region located at the top of the first and second active regions in the first via; a second source / drain region located at the top of the first and second active regions in the second via; a third source / drain region located at the bottom of the first and second active regions in the first via; and a fourth source / drain region located at the bottom of the first and second active regions in the second via; and a metal interconnect layer connecting the third and fourth source / drain regions located on the back surface of the first insulating layer. The 3D CMOS device of the present invention improves the integration density.

Description

Technical Field

[0001] This application relates to the field of semiconductor CMOS, and more particularly to a 3D CMOS device and a method for forming the same. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) transistors are the basic units in modern logic circuits, which contain a PMOS transistor and an NMOS transistor connected together. Each PMOS transistor (or NMOS transistor) includes: a doped well region located in a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate; an N-type (or N-type) source region and a drain region located on both sides of the gate structure in the semiconductor substrate; and a channel located between the source and drain regions.

[0003] Existing CMOS fabrication processes generally include: providing a semiconductor substrate, the semiconductor substrate including an N-type well region and a P-type well region; forming a gate structure of a PMOS transistor (the gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer) on the N-type well region; forming a gate structure of an NMOS transistor (the gate structure includes a gate dielectric layer and a gate electrode located on the gate dielectric layer) on the P-type well region; forming P-type source and drain regions in the N-type well regions on both sides of the gate structure of the PMOS transistor; forming N-type source and drain regions in the P-type well regions on both sides of the gate structure of the NMOS transistor; forming a bottom dielectric layer on the semiconductor substrate; and forming a metal interconnect structure in the bottom dielectric layer connecting the drain of the PMOS transistor and the drain of the NMOS transistor.

[0004] However, in existing CMOS, the gate and source / drain regions of PMOS and NMOS transistors are horizontally arranged, occupying a large area of ​​the semiconductor substrate, which is not conducive to improving the device integration density. Summary of the Invention

[0005] Some embodiments of this application provide a method for forming a 3D CMOS device, the 3D CMOS device including electrically connected PMOS transistors and NMOS transistors, comprising:

[0006] Provide semiconductor substrates;

[0007] A vertical first active region and a second active region are formed on the semiconductor substrate, as well as a first vertical gate surrounding the middle portion of the first active region and a second vertical gate surrounding the middle portion of the second active region. A first gate dielectric layer is provided between the first vertical gate and the sidewall of the first active region, and a second gate dielectric layer is provided between the second vertical gate and the sidewall of the second active region. A first insulating layer is provided between the bottom of the first vertical gate and the second vertical gate and the semiconductor substrate.

[0008] A first insulating layer is formed on the surface of the semiconductor substrate;

[0009] A first source / drain region is formed at the top of the first active region, and a second source / drain region is formed at the top of the second active region. The types of impurity ions doped in the first source / drain region and the second source / drain region are opposite.

[0010] Remove the semiconductor substrate to expose the bottom surfaces of the first and second active regions;

[0011] A third source / drain region is formed at the bottom of the first active region, and a fourth source / drain region is formed at the bottom of the second active region. The third source / drain region is doped with the same type of impurity ions as the first source / drain region, and the fourth source / drain region is doped with the same type of impurity ions as the second source / drain region.

[0012] A metal connection layer connecting the third source / drain region and the fourth source / drain region is formed on the back side of the first insulating layer.

[0013] In some embodiments, the formation process of the first vertical gate, the second vertical gate, the first active region, and the second active region includes:

[0014] A first insulating layer is formed on the semiconductor substrate;

[0015] A discrete first vertical gate and a second vertical gate are formed on the front side of the first insulating layer.

[0016] A second insulating layer is formed covering the first vertical gate, the second vertical gate, and the first insulating layer;

[0017] The second insulating layer, the first vertical gate, the second vertical gate, and the first insulating layer are etched to form a first via penetrating the second insulating layer, the first vertical gate, and the first insulating layer, and a second via penetrating the second insulating layer, the second vertical gate, and the first insulating layer;

[0018] A first gate dielectric layer is formed on the sidewall surface of the first through hole, and a second gate dielectric layer is formed on the sidewall surface of the second through hole;

[0019] The first and second vias are filled with semiconductor material to form the first active region and the second active region, respectively.

[0020] In some embodiments, the formation process of the first vertical gate, the second vertical gate, the first active region, and the second active region includes:

[0021] Discrete first and second active regions are formed on the semiconductor substrate;

[0022] A first insulating layer is formed on the semiconductor substrate, covering the bottom portion sidewalls of the first active region and the second active region, wherein the top surface of the first insulating layer is lower than the top surface of the first active region and the second active region.

[0023] A first gate dielectric layer is formed on the sidewall surface of the first active region; a second gate dielectric layer is formed on the sidewall surface of the second active region;

[0024] A first vertical gate is formed around the middle portion of the first active region on the surface of the first gate dielectric layer and a portion of the surface of the first insulating layer, and the top surface of the first vertical gate is lower than the top surface of the first active region; a second vertical gate is formed around the middle portion of the second active region on the surface of the second gate dielectric layer and a portion of the surface of the first insulating layer, and the top surface of the second vertical gate is lower than the top surface of the second active region.

[0025] A second insulating layer is formed covering the first vertical gate, the second vertical gate, and the first insulating layer, the second insulating layer exposing the top surfaces of the first active region and the second active region.

[0026] In some embodiments, the method further includes: forming an interlayer dielectric layer on the second insulating layer, forming a first metal wiring layer and a second metal wiring layer in the interlayer dielectric layer, wherein the first metal wiring layer is electrically connected to the first source / drain region, and the second metal wiring layer is electrically connected to the second source / drain region.

[0027] In some embodiments, before removing the semiconductor substrate, the process further includes: forming a top silicon oxide layer on the surface of the interlayer dielectric layer; bonding a carrier plate to the surface of the top silicon oxide layer; after bonding the carrier plate, flipping the semiconductor substrate and then removing the semiconductor substrate.

[0028] In some embodiments, after removing the semiconductor substrate, the method further includes: sequentially etching the first insulating layer, the second insulating layer, and the interlayer dielectric layer along the back side direction of the first insulating layer until the surfaces of the first metal wiring layer and the second metal wiring layer are exposed; forming a third via that exposes the bottom surface of the first metal wiring layer and a fourth via that exposes the bottom surface of the second metal wiring layer in the first insulating layer, the second insulating layer, and the interlayer dielectric layer; filling the third via with metal to form a first via connection structure; and filling the fourth via with metal to form a second via connection structure.

[0029] In some embodiments, the process of removing the semiconductor substrate to expose the bottom surfaces of the first active region and the second active region and forming a metal interconnect layer includes: removing the entire semiconductor substrate to expose the back side of the first insulating layer and the bottom surfaces of the first active region and the second active region; and forming a metal interconnect layer connecting the third source / drain region and the fourth source / drain region on the exposed back side surface of the first insulating layer.

[0030] In some embodiments, the process of removing the semiconductor substrate to expose the bottom surfaces of the first and second active regions and forming a metal interconnect layer includes: removing a portion of the semiconductor substrate; etching the remaining semiconductor substrate to form vias in the remaining semiconductor substrate that expose the bottom surfaces of the first and second active regions; and forming a metal interconnect layer connecting the third and fourth source / drain regions on the surface of the remaining semiconductor substrate on the back surface of the first insulating layer and in the vias.

[0031] In some embodiments, the first active region and the second active region are made of single-crystal semiconductor material, and the first active region and the second active region are formed by epitaxial process.

[0032] In some embodiments, the doped impurity ions in the third source / drain region and the first source / drain region are of type N, and the doped impurity ions in the fourth source / drain region and the second source / drain region are of type P.

[0033] In some embodiments, the doped impurity ions in the third source / drain region and the first source / drain region are of the P-type, and the doped impurity ions in the fourth source / drain region and the second source / drain region are of the N-type.

[0034] In some embodiments, the first source / drain region and the second source / drain region are formed by a first ion implantation process and a second ion implantation process, respectively, and the types of impurity ions implanted by the first ion implantation process and the second ion implantation process are opposite.

[0035] In some embodiments, the third source / drain region and the fourth source / drain region are formed by a third ion implantation process and a fourth ion implantation process, respectively, and the types of impurity ions implanted by the third ion implantation process and the fourth ion implantation process are opposite.

[0036] Some embodiments of this application also provide a 3D CMOS device, including:

[0037] A first insulating layer, the first insulating layer comprising a front surface and a back surface opposite to the front surface;

[0038] A first vertical gate and a second vertical gate are separated on the front surface of the first insulating layer.

[0039] A second insulating layer covering the front surface of the first vertical gate, the second vertical gate, and the first insulating layer;

[0040] A first active region located in the second insulating layer, the first vertical gate, and the first insulating layer, and a second via located in the second insulating layer, the second vertical gate, and the first insulating layer;

[0041] A first gate dielectric layer located between the first active region and the first vertical gate, and a second gate dielectric layer located between the second active region and the second vertical gate;

[0042] The first source / drain region is located at the top of the first active region, and the second source / drain region is located at the top of the second active region. The types of impurity ions doped in the first source / drain region and the second source / drain region are opposite.

[0043] The third source / drain region is located at the bottom of the first active region, and the fourth source / drain region is located at the bottom of the second active region. The third source / drain region is doped with the same type of impurity ions as the first source / drain region, and the fourth source / drain region is doped with the same type of impurity ions as the second source / drain region.

[0044] A metal bonding layer connecting the third and fourth source / drain regions located on the back surface of the first insulating layer.

[0045] In some embodiments, the invention further includes: an interlayer dielectric layer located on the second insulating layer, a first metal wiring layer and a second metal wiring layer located in the interlayer dielectric layer, wherein the first metal wiring layer is electrically connected to the first source / drain region, and the second metal wiring layer is electrically connected to the second source / drain region.

[0046] In some embodiments, the system further includes: a top silicon oxide layer located on the surface of the interlayer dielectric layer; a carrier plate located on the top silicon oxide layer and bonded to the top silicon oxide layer; a third via located in the first insulating layer, the second insulating layer, and the interlayer dielectric layer, exposing the bottom surface of the first metal wiring layer and a fourth via located in the second metal wiring layer; a first via connection structure located in the third via and a second via connection structure located in the fourth via.

[0047] In some embodiments, the first gate dielectric layer and the second gate dielectric layer are made of silicon oxide or a high-k dielectric material, the first vertical gate and the second vertical gate are made of polycrystalline silicon or metal, and the first active region and the second active region are made of single-crystal semiconductor material.

[0048] In some embodiments, the doped impurity ions in the third source / drain region and the first source / drain region are of type N, and the doped impurity ions in the fourth source / drain region and the second source / drain region are of type P.

[0049] In some embodiments, the doped impurity ions in the third source / drain region and the first source / drain region are of the P-type, and the doped impurity ions in the fourth source / drain region and the second source / drain region are of the N-type.

[0050] Compared with the prior art, the advantages of the technical solution of this application are as follows:

[0051] The 3D CMOS device in some of the foregoing embodiments of this application includes a first insulating layer, the first insulating layer including a front surface and a back surface opposite to the front surface; a first vertical gate and a second vertical gate disposed on the front surface of the first insulating layer; a second insulating layer covering the first vertical gate, the second vertical gate and the front surface of the first insulating layer; a first via penetrating the second insulating layer, the first vertical gate and the first insulating layer, and a second via penetrating the second insulating layer, the second vertical gate and the first insulating layer; a first gate dielectric layer located on the sidewall surface of the first via, and a gate dielectric layer located on the sidewall surface of the second via; a first gate dielectric layer filling the first via. The device comprises a source region and a second active region filling the second via; a first source / drain region located at the top of the first active region, and a second source / drain region located at the top of the second active region, wherein the impurity ion types doped in the first and second source / drain regions are opposite; a third source / drain region located at the bottom of the first active region, and a fourth source / drain region located at the bottom of the second active region, wherein the third source / drain region has the same impurity ion type as the first source / drain region, and the fourth source / drain region has the same impurity ion type as the second source / drain region; and a metal interconnect layer connecting the third and fourth source / drain regions located on the back surface of the first insulating layer. Since the gate, active region, and source / drain regions of the two interconnected transistors (PMOS and NMOS transistors) in the aforementioned 3D CMOS device are vertically arranged, the lateral area of ​​the semiconductor substrate occupied by the gate, active region, and source / drain region is reduced, thereby reducing the overall lateral area of ​​the semiconductor substrate occupied by the 3D CMOS device, improving the integration density of the 3D CMOS device. Furthermore, the metal interconnect layer is formed on the back surface of the first insulating layer, simplifying the metal wiring structure. Attached Figure Description

[0052] Figures 1-12 This is a schematic diagram of the formation process of a 3D CMOS device in some embodiments of this application. Detailed Implementation

[0053] The specific embodiments of this application will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this application in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0054] One embodiment of this application provides a method for forming a 3D CMOS device, referring to... Figure 1 A semiconductor substrate 201 is provided, and a first insulating layer 202 is formed on the surface of the semiconductor substrate 201.

[0055] The semiconductor substrate 200 serves as a platform for subsequent processes. In some embodiments, the semiconductor substrate 200 may be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the semiconductor substrate 200 is made of silicon.

[0056] The first insulating layer 202 serves as isolation between devices. In some embodiments, the material of the first insulating layer 202 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. In this embodiment, the material of the first insulating layer 202 is silicon oxide, which is formed by furnace oxidation of the semiconductor substrate 200. In other embodiments, the first insulating layer 202 may also be formed by a deposition process.

[0057] refer to Figure 2 A discrete first vertical gate 203 and a second vertical gate 204 are formed on the front side of the first insulating layer 202.

[0058] The first vertical gate 203 and the second vertical gate 204 serve as gates for two transistors of different types. In one embodiment, when the first vertical gate 203 serves as the gate of a PMOS transistor, the corresponding second vertical gate 204 serves as the gate of an NMOS transistor. In other embodiments, when the first vertical gate 203 serves as the gate of an NMOS transistor, the corresponding second vertical gate 204 serves as the gate of a PMOS transistor.

[0059] In one embodiment, the first vertical gate 203 and the second vertical gate 204 are made of polysilicon. The formation process of the first vertical gate 203 and the second vertical gate 204 includes: forming a gate material layer (not shown in the figure), such as a polysilicon layer, on the first insulating layer 202; forming a patterned mask layer (not shown in the figure) on the gate material layer; and etching the gate material layer using the patterned mask layer as a mask to form discrete first vertical gate 203 and second vertical gate 204 on the first insulating layer 202.

[0060] In some embodiments, the formed first vertical gate 203 and second vertical gate 204 are solid structures.

[0061] In some embodiments, the formed first vertical gate and second vertical gate are annular structures, that is, the first vertical gate and the second vertical gate have hollow portions that penetrate the thickness of the first vertical gate and the second vertical gate. The hollow portions can be directly used as part of the first via or the second via. The first via and the second via are subsequently used to form the first active region and the second active region, respectively. When the second insulating layer, the first vertical gate (or the second vertical gate) and the first insulating layer are subsequently etched to form the first via (or the second via), it is not necessary to etch the first vertical gate (or the second vertical gate) again. It is only necessary to remove the second insulating layer material that fills the hollow portion of the first vertical gate (or the second vertical gate). Therefore, the etching difficulty when forming the first via and the second via can be reduced, the uniformity of the sidewall morphology and the uniformity of the size of the formed first via and the second via can be improved, and the electrical performance of the device can be improved.

[0062] In other embodiments, the first vertical gate 203 and the second vertical gate 204 are made of metal, which may be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The formation process of the first vertical gate 203 and the second vertical gate 204 may include: forming a patterned hard mask layer (not shown in the figure) on the first insulating layer, the patterned mask layer having a first opening and a second opening exposing the surface of the first insulating layer 202; forming a metal material layer in the first opening and the second opening and on the surface of the patterned hard mask layer; removing the metal material layer above the surface of the patterned mask layer using a chemical mechanical polishing process; forming the first vertical gate 203 in the first opening and the second vertical gate 204 in the second opening; and removing the hard mask layer. In some embodiments, both the first opening and the second opening are annular openings, and the formed first vertical gate and second vertical gate are annular vertical gates. After removing the hard mask layer, the annular vertical gate has a hollow portion that penetrates the annular vertical gate. The hollow portion can be directly used as part of the first via or the second via. The first via and the second via are subsequently used to form the first active region and the second active region, respectively. When etching the second insulating layer, the first vertical gate (or the second vertical gate), and the first insulating layer to form the first via (or the second via) in the subsequent process, it is not necessary to etch the vertical gate of metal material again. Only the material of the second insulating layer filling the hollow portion of the vertical gate needs to be removed. Therefore, the etching difficulty of forming the first via and the second via in the vertical metal gate process can be reduced, the uniformity of the sidewall morphology and size of the formed first via and the second via can be improved, and the electrical performance of the device can be improved.

[0063] refer to Figure 3A second insulating layer 205 is formed covering the first vertical gate 203, the second vertical gate 204, and the first insulating layer 202.

[0064] The second insulating layer 205 serves as isolation between devices, and the surface of the formed second insulating layer 205 is higher than the surfaces of the first vertical gate 203 and the second vertical gate 204. In some embodiments, the material of the second insulating layer 205 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. In this embodiment, the material of the second insulating layer 205 is silicon oxide. The second insulating layer 205 is first formed into a film by chemical vapor deposition, and then its surface is flattened by chemical mechanical polishing.

[0065] refer to Figure 4 The second insulating layer 205, the first vertical gate 203, the second vertical gate 204 and the first insulating layer 202 are etched to form a first via 206 penetrating the second insulating layer 205, the first vertical gate 203 and the first insulating layer 202, and a second via 207 penetrating the second insulating layer 205, the second vertical gate 204 and the first insulating layer 202.

[0066] The first active region and the second active region of an NMOS transistor or a PMOS transistor are subsequently formed in the first via 206 and the second via 207, respectively.

[0067] In one embodiment, the etching process includes an anisotropic dry etching process, which can be an anisotropic plasma etching process.

[0068] refer to Figure 5 A first gate dielectric layer 208 is formed on the sidewall surface of the first through hole 206, and a second gate dielectric layer 209 is formed on the sidewall surface of the second through hole 207.

[0069] In some embodiments, when the materials of the first vertical gate 203 and the second vertical gate 204 are polysilicon, the materials of the first gate dielectric layer 208 and the second gate dielectric layer 209 are silicon oxide. The first gate dielectric layer 208 and the second gate dielectric layer 209 are formed by furnace tube oxidation or deposition process. Subsequently, before the first active region and the second active region are formed in the first via 206 and the second via 207, respectively, the silicon oxide layer on the surface of the semiconductor substrate 201 at the bottom of the first via 206 and the second via 207 needs to be removed by etching process.

[0070] In another embodiment, when the materials of the first vertical gate 203 and the second vertical gate 204 are metals, the materials of the first gate dielectric layer 208 and the second gate dielectric layer 209 are high-k dielectric materials. The first gate dielectric layer 208 and the second gate dielectric layer 209 are formed by a deposition process. Subsequently, before the first active region and the second active region are formed in the first via 206 and the second via 207, respectively, the high-k dielectric material layer on the surface of the semiconductor substrate 201 at the bottom of the first via 206 and the second via 207 needs to be removed by an etching process. In some embodiments, the high-k dielectric material is one or more of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO.

[0071] refer to Figure 6 The first and second vias are filled with semiconductor material to form the first active region 210 and the second active region 211, respectively.

[0072] A first active region 210 is formed by filling the first via with semiconductor material, and a second active region 211 is formed by filling the second via with semiconductor material.

[0073] In this application, since the formed 3D CMOS includes a PMOS transistor and an NMOS transistor connected together, the channel region and source / drain region in the first active region 210 and the second active region 211 are subsequently used for two different types of transistors (PMOS transistor or NMOS transistor).

[0074] The first active region 210 and the second active region 211 are made of single-crystal semiconductor materials. In one embodiment, the materials of the first active region 210 and the second active region 211 can be single-crystal silicon or single-crystal germanium. In other embodiments, the materials of the first active region 210 and the second active region 211 can also be silicon-germanium (GeSi) or silicon carbide (SiC). The first active region 210 and the second active region 211 are formed by epitaxial processes, specifically including selective epitaxy processes.

[0075] The impurity ions doped in the third source / drain region and the first source / drain region are of type N, and the impurity ions doped in the fourth source / drain region and the second source / drain region are of type P.

[0076] In some embodiments, the first active region 210 and the second active region 211 may be doped with different types of impurity ions depending on the type of transistor formed. In a specific embodiment, when the first active region 210 and the second active region 211 are doped with different types of impurity ions, the first active region 210 and the second active region 211 are formed by epitaxial processes with different steps.

[0077] In some other embodiments, the first active region 210 and the second active region 211 may be formed prior to the first vertical gate 203 and the second vertical gate 204. Specifically, the process includes: forming discrete first and second active regions on the semiconductor substrate; forming a first insulating layer on the semiconductor substrate covering the bottom portion sidewalls of the first and second active regions, the top surface of the first insulating layer being lower than the top surfaces of the first and second active regions; forming a first gate dielectric layer on the sidewall surface of the first active region; forming a second gate dielectric layer on the sidewall surface of the second active region; forming a first vertical gate surrounding the middle portion of the first active region on the surface of the first gate dielectric layer and a portion of the surface of the first insulating layer, the top surface of the first vertical gate being lower than the top surface of the first active region; forming a second vertical gate surrounding the middle portion of the second active region on the surface of the second gate dielectric layer and a portion of the surface of the first insulating layer, the top surface of the second vertical gate being lower than the top surface of the second active region; and forming a second insulating layer covering the first vertical gate, the second vertical gate, and the first insulating layer, the second insulating layer exposing the top surfaces of the first and second active regions.

[0078] refer to Figure 7 A first source / drain region 212 is formed at the top of the first active region 210 in the first via, and a second source / drain region 213 is formed at the top of the second active region 211 in the second via. The impurity ions doped in the first source / drain region 212 and the second source / drain region 213 are of opposite types.

[0079] The first source / drain region 212 and the second source / drain region 213 serve as source / drain regions for different types of transistors. When the first source / drain region 212 serves as the source or drain region of a PMOS transistor, the doped impurity ions in the first source / drain region 212 are of P-type. Correspondingly, when the second source / drain region 213 serves as the source or drain region of an NMOS transistor, the doped impurity ions in the second source / drain region 213 are of N-type. In other embodiments, when the first source / drain region 212 serves as the source or drain region of an NMOS transistor, the doped impurity ions in the first source / drain region 212 are of N-type. Correspondingly, when the second source / drain region 213 serves as the source or drain region of a PMOS transistor, the doped impurity ions in the second source / drain region 213 are of P-type.

[0080] The first source / drain region 212 and the second source / drain region 213 are formed through an ion implantation process. Specifically, the formation of the first source / drain region 212 and the second source / drain region 213 is performed using a first ion implantation process and a second ion implantation process, respectively, with the types of impurity ions implanted in the first and second ion implantation processes being opposite. Specifically, when the impurity ions implanted in the first ion implantation process are P-type, the corresponding impurity ions implanted in the second ion implantation process are N-type. When the impurity ions implanted in the first ion implantation process are N-type, the corresponding impurity ions implanted in the second ion implantation process are P-type. It should be noted that during the first or second ion implantation process, areas that do not need to be implanted can be covered by a mask layer (such as a photoresist layer), and the corresponding mask layer is removed after implantation.

[0081] In some embodiments, the P-type impurity ion is one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ion includes one or more of phosphorus ions, arsenic ions, or antimony ions.

[0082] In some embodiments, forming the first source / drain region 212 and the second source / drain region 213 may further include: forming a metal silicide layer on the surface of the first source / drain region 212 and the second source / drain region 213; forming an interlayer dielectric layer 216 on the second insulating layer 205; forming a first metal wiring layer 214 and a second metal wiring layer 215 in the interlayer dielectric layer 216; the first metal wiring layer 214 being electrically connected to the first source / drain region 212; and the second metal wiring layer 215 being electrically connected to the second source / drain region 213.

[0083] In some embodiments, the material of the interlayer dielectric layer 216 may be silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicon glass (FSG), a low dielectric constant material, other suitable materials, and / or combinations thereof. The first metal wiring layer 214 and the second metal wiring layer 215 include at least one metal plug connected to the source / drain region (first source / drain region 212 or second source / drain region 213) and a metal wire connected to the metal plug.

[0084] In some embodiments, the method further includes: forming a top silicon oxide layer 217 on the surface of the interlayer dielectric layer 216; Reference Figure 9 A carrier plate 221 is bonded to the surface of the top silicon oxide layer 217. The function of forming the top silicon oxide layer 217 is to bond the carrier plate 221 using a direct bonding process or a diffusion bonding process. The function of forming the carrier plate 221 is to support and protect the entire formed stacked structure during subsequent back-side processes (removal of the semiconductor substrate and formation of the metal interconnect layer). In other embodiments, the carrier plate 221 may be bonded to the top silicon oxide layer 217 using other bonding processes.

[0085] In some embodiments, the carrier plate 221 may be made of silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or other materials.

[0086] refer to Figure 10 Remove the semiconductor substrate to expose the bottom surfaces of the first active region 210 and the second active region 211.

[0087] In this embodiment, the entire semiconductor substrate is removed to expose the back side of the first insulating layer 202 and the bottom surfaces of the first active region 210 and the second active region 211. Subsequently, a metal interconnect layer connecting the third source / drain region and the fourth source / drain region can be directly formed on the exposed back side surface of the first insulating layer.

[0088] The semiconductor substrate 201 can be removed using a combination of etching and chemical mechanical polishing processes.

[0089] In some embodiments, when removing the semiconductor substrate, the carrier plate 221 may be flipped downwards according to the actual process.

[0090] In some other embodiments, when removing the semiconductor substrate, only a portion of the semiconductor substrate thickness is removed, leaving a portion of the semiconductor substrate thickness remaining. The remaining semiconductor substrate can then be etched to form bottom surface vias exposing the first and second active regions. A metal interconnect layer connecting the third and fourth source / drain regions is formed on the surface of the remaining semiconductor substrate on the back surface of the first insulating layer and in the vias.

[0091] refer to Figure 11 A third source / drain region 218 is formed at the bottom of the first active region 210, and a fourth source / drain region 219 is formed at the bottom of the second active region 211. The third source / drain region 218 is doped with the same type of impurity ions as the first source / drain region 212, and the fourth source / drain region 219 is doped with the same type of impurity ions as the second source / drain region 213.

[0092] In one embodiment, the first source-drain region 212 and the third source-drain region 218 formed in the top and bottom of the first active region 210 serve as the source region or drain region of a PMOS transistor, respectively. Correspondingly, the second source-drain region 213 and the fourth source-drain region 219 formed in the top and bottom of the second active region 211 serve as the source region or drain region of an NMOS transistor, respectively.

[0093] In another embodiment, the first source-drain region 212 and the third source-drain region 218 formed in the top and bottom of the first active region 210 serve as the source region or drain region of the NMOS transistor, respectively. Correspondingly, the second source-drain region 213 and the fourth source-drain region 219 formed in the top and bottom of the second active region 211 serve as the source region or drain region of the PMOS transistor, respectively.

[0094] The third source / drain region 218 is doped with the same type of impurity ions as the first source / drain region 212, and the fourth source / drain region 219 is doped with the same type of impurity ions as the second source / drain region 213; that is, the types of impurity ions doped in the third source / drain region 218 and the fourth source / drain region 219 are opposite. In one specific embodiment, when the impurity ions doped in the third source / drain region 218 and the first source / drain region 212 are P-type, then the impurity ions doped in the fourth source / drain region 219 and the second source / drain region 213 are N-type. In another specific embodiment, when the impurity ions doped in the third source / drain region 218 and the first source / drain region 212 are N-type, then the impurity ions doped in the fourth source / drain region 219 and the second source / drain region 213 are P-type.

[0095] The third source / drain region 218 and the fourth source / drain region 219 are formed by ion implantation. In a specific embodiment, the third source / drain region 218 and the fourth source / drain region 219 are formed by a third ion implantation process and a fourth ion implantation process, respectively, and the types of impurity ions implanted by the third ion implantation process and the fourth ion implantation process are opposite. Specifically, when the impurity ion type implanted by the third ion implantation process is P-type, the corresponding impurity ion type implanted by the fourth ion implantation process is N-type. When the impurity ion type implanted by the third ion implantation process is N-type, the corresponding impurity ion type implanted by the fourth ion implantation process is P-type. It should be noted that during the third or fourth ion implantation process, areas that do not need to be implanted can be covered by a mask layer (such as a photoresist layer), and the corresponding mask layer is removed after implantation.

[0096] In some embodiments, the P-type impurity ion is one or more of boron ions, gallium ions, or indium ions, and the N-type impurity ion includes one or more of phosphorus ions, arsenic ions, or antimony ions.

[0097] In this application, after removing the semiconductor substrate, the third source / drain region 218 and the fourth source / drain region 219 are formed by ion implantation, which simplifies the formation of the third source / drain region 218 and the fourth source / drain region 219, and the concentration of doped ions in the third source / drain region 218 and the fourth source / drain region 219 can be controlled more accurately.

[0098] refer to Figure 12 A metal connection layer 220 is formed on the back side of the first insulating layer 202 to connect the third source / drain region 218 and the fourth source / drain region 219.

[0099] In this embodiment, a metal interconnect layer 220 for the third source / drain region 218 and the fourth source / drain region 219 is formed directly on the surface of the exposed first insulating layer 202. In other embodiments, when a portion of the semiconductor substrate remains, the remaining semiconductor substrate is etched to form bottom surface vias exposing the first and second active regions; a metal interconnect layer connecting the third and fourth source / drain regions is formed on the surface of the remaining semiconductor substrate on the back surface of the first insulating layer and in the vias. The metal interconnect layer 220 is made of metal, and in some embodiments, the material of the metal interconnect layer 220 can be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. In some embodiments, the metal interconnect layer 220 can be formed by electroplating or by sputtering and etching.

[0100] The metal interconnect layer 220 connects the third source / drain region 218 and the fourth source / drain region 219, enabling electrical connection between two different types of transistors (PMOS transistor and NMOS transistor) in the 3D CMOS of this application. Since the gate, active region and source / drain region of the two different types of transistors formed above are vertically arranged, the lateral area of ​​the semiconductor substrate occupied by the gate, active region and source / drain region will be reduced, thereby reducing the lateral area of ​​the semiconductor substrate occupied by the 3D CMOS device as a whole, improving the integration of the 3D CMOS device. Furthermore, the metal interconnect layer 220 is formed on the back side of the first insulating layer, simplifying the metal wiring structure.

[0101] In some embodiments, continue to refer to Figure 12 After removing the semiconductor substrate, the process further includes: sequentially etching the first insulating layer 202, the second insulating layer 205, and the interlayer dielectric layer 216 along the back side direction of the first insulating layer 201 until the back surfaces of the first metal wiring layer 214 and the second metal wiring layer 215 are exposed; forming a third via exposing the back surface of the first metal wiring layer and a fourth via exposing the back surface of the second metal wiring layer in the first insulating layer 202, the second insulating layer 205, and the interlayer dielectric layer 216; filling the third via with metal to form a first via connection structure 222, and filling the fourth via with metal to form a second via connection structure 223. This allows the unconnected source or drain regions of two different types of transistors in the 3D CMOS device to be brought to the back surface of the first insulating layer 202, facilitating connection with other devices.

[0102] In some embodiments, after forming the first through-hole connection structure 222 and the second through-hole connection structure 223, a passivation layer 226 is further formed covering the back surface of the metal connection layer 220 and the first insulating layer 202. A first metal bump 224, such as a solder ball, is formed in the passivation layer 226 to connect to the first through-hole connection structure 222, and a second metal bump 225, such as a solder ball, is formed to connect to the second through-hole connection structure 223.

[0103] After the first metal bump 224 and the second metal bump 225 are formed, the carrier plate 221 can be retained as part of the 3D CMOS device. In other embodiments, the carrier plate 221 can also be removed.

[0104] Some embodiments of this application also provide a 3D CMOS device, see reference. Figure 12 ,include:

[0105] The first insulating layer 202 includes a front surface and a back surface opposite to the front surface;

[0106] A first vertical gate 203 and a second vertical gate 204 are separated on the front surface of the first insulating layer 202.

[0107] A second insulating layer 205 covering the front surface of the first vertical gate 203, the second vertical gate 204, and the first insulating layer 202;

[0108] The first active region 210 is located in the second insulating layer 205, the first vertical gate 203 and the first insulating layer 202, and the second active region 211 is located in the second insulating layer 205, the second vertical gate 204 and the first insulating layer 202;

[0109] A first gate dielectric layer 208 is located between the first active region 210 and the first vertical gate 203, and a gate dielectric layer 209 is located between the second active region 211 and the second vertical gate 204.

[0110] The first source / drain region 212 is located at the top of the first active region 210, and the second source / drain region 213 is located at the top of the second active region 211. The types of impurity ions doped in the first source / drain region 212 and the second source / drain region 213 are opposite.

[0111] The third source / drain region 218 is located at the bottom of the first active region 210, and the fourth source / drain region 219 is located at the bottom of the second active region 211. The third source / drain region 218 is doped with the same type of impurity ions as the first source / drain region 212, and the fourth source / drain region 219 is doped with the same type of impurity ions as the second source / drain region 213.

[0112] A metal bonding layer 220 is located on the back surface of the first insulating layer 202, connecting the third source / drain region 218 and the fourth source / drain region 219.

[0113] In some embodiments, the invention further includes: an interlayer dielectric layer 216 located on the second insulating layer 205, a first metal wiring layer 214 and a second metal wiring layer 215 located in the interlayer dielectric layer 216, wherein the first metal wiring layer 214 is electrically connected to the first source / drain region 212, and the second metal wiring layer 215 is electrically connected to the second source / drain region 213.

[0114] In some embodiments, the system further includes: a top silicon oxide layer 217 located on the surface of the interlayer dielectric layer 216; a carrier plate 221 located on the top silicon oxide layer and bonded to the top silicon oxide layer 217; a third via exposed to the bottom surface of the first metal wiring layer and a fourth via exposed to the bottom surface of the second metal wiring layer in the first insulating layer 202, the second insulating layer 205 and the interlayer dielectric layer 216; a first via connection structure 222 located in the third via; and a second via connection structure 223 located in the fourth via.

[0115] In some embodiments, the first gate dielectric layer 208 and the second gate dielectric layer 209 are made of silicon oxide or a high-k dielectric material, the first vertical gate 203 and the second vertical gate 204 are made of polycrystalline silicon or metal, and the first active region 210 and the second active region 211 are made of single-crystal semiconductor material.

[0116] In some embodiments, the doped impurity ions in the third source / drain region 218 and the first source / drain region 212 are of type N, and the doped impurity ions in the fourth source / drain region 219 and the second source / drain region 213 are of type P.

[0117] In some embodiments, the doped impurity ions in the third source / drain region 218 and the first source / drain region 212 are P-type, and the doped impurity ions in the fourth source / drain region 219 and the second source / drain region 213 are N-type.

[0118] It should be noted that other limitations or descriptions in this embodiment (3D CMOS device) that are the same as or similar to those in the foregoing embodiments (method of forming 3D CMOS device) will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the foregoing embodiments for details.

[0119] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming a 3D CMOS device, the 3D CMOS device comprising electrically connected PMOS transistors and NMOS transistors, characterized in that, include: Provide semiconductor substrates; A first active region and a second active region are formed vertically on the semiconductor substrate, as well as a first vertical gate surrounding the middle portion of the first active region and a second vertical gate surrounding the middle portion of the second active region. A first gate dielectric layer is provided between the first vertical gate and the sidewall of the first active region, and a second gate dielectric layer is provided between the second vertical gate and the sidewall of the second active region. A first insulating layer is formed on the surface of the semiconductor substrate, and the bottom of the first vertical gate and the second vertical gate are provided with the first insulating layer between them and the semiconductor substrate. A first source / drain region is formed at the top of the first active region, and a second source / drain region is formed at the top of the second active region. The types of impurity ions doped in the first source / drain region and the second source / drain region are opposite. Remove the semiconductor substrate to expose the bottom surfaces of the first and second active regions; A third source / drain region is formed at the bottom of the first active region, and a fourth source / drain region is formed at the bottom of the second active region. The third source / drain region is doped with the same type of impurity ions as the first source / drain region, and the fourth source / drain region is doped with the same type of impurity ions as the second source / drain region. A metal connection layer connecting the third source / drain region and the fourth source / drain region is formed on the back side of the first insulating layer.

2. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The formation process of the first vertical gate, the second vertical gate, the first active region, and the second active region includes: A first insulating layer is formed on the semiconductor substrate; A discrete first vertical gate and a second vertical gate are formed on the front side of the first insulating layer. A second insulating layer is formed covering the first vertical gate, the second vertical gate, and the first insulating layer; The second insulating layer, the first vertical gate, the second vertical gate, and the first insulating layer are etched to form a first via penetrating the second insulating layer, the first vertical gate, and the first insulating layer, and a second via penetrating the second insulating layer, the second vertical gate, and the first insulating layer; A first gate dielectric layer is formed on the sidewall surface of the first through hole, and a second gate dielectric layer is formed on the sidewall surface of the second through hole; The first and second vias are filled with semiconductor material to form the first active region and the second active region, respectively.

3. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The formation process of the first vertical gate, the second vertical gate, the first active region, and the second active region includes: Discrete first and second active regions are formed on the semiconductor substrate; A first insulating layer is formed on the semiconductor substrate, covering the bottom portion sidewalls of the first active region and the second active region, wherein the top surface of the first insulating layer is lower than the top surface of the first active region and the second active region. A first gate dielectric layer is formed on the sidewall surface of the first active region; a second gate dielectric layer is formed on the sidewall surface of the second active region; A first vertical gate is formed around the middle portion of the first active region on the surface of the first gate dielectric layer and a portion of the surface of the first insulating layer, and the top surface of the first vertical gate is lower than the top surface of the first active region; a second vertical gate is formed around the middle portion of the second active region on the surface of the second gate dielectric layer and a portion of the surface of the first insulating layer, and the top surface of the second vertical gate is lower than the top surface of the second active region. A second insulating layer is formed covering the first vertical gate, the second vertical gate, and the first insulating layer, the second insulating layer exposing the top surfaces of the first active region and the second active region.

4. The method for forming a 3D CMOS device as described in claim 2 or 3, characterized in that, Also includes: An interlayer dielectric layer is formed on the second insulating layer, and a first metal wiring layer and a second metal wiring layer are formed in the interlayer dielectric layer. The first metal wiring layer is electrically connected to the first source-drain region, and the second metal wiring layer is electrically connected to the second source-drain region.

5. The method for forming a 3D CMOS device as described in claim 4, characterized in that, Before removing the semiconductor substrate, the method further includes: forming a top silicon oxide layer on the surface of the interlayer dielectric layer; bonding a carrier plate to the surface of the top silicon oxide layer; after bonding the carrier plate, flipping the semiconductor substrate and then removing the semiconductor substrate.

6. The method for forming a 3D CMOS device as described in claim 5, characterized in that, After removing the semiconductor substrate, the method further includes: sequentially etching the first insulating layer, the second insulating layer, and the interlayer dielectric layer along the back side direction of the first insulating layer until the surfaces of the first metal wiring layer and the second metal wiring layer are exposed; forming a third via that exposes the bottom surface of the first metal wiring layer and a fourth via that exposes the bottom surface of the second metal wiring layer in the first insulating layer, the second insulating layer, and the interlayer dielectric layer; filling the third via with metal to form a first via connection structure; and filling the fourth via with metal to form a second via connection structure.

7. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The process of removing the semiconductor substrate to expose the bottom surfaces of the first active region and the second active region and forming a metal interconnect layer includes: removing the entire semiconductor substrate to expose the back side of the first insulating layer and the bottom surfaces of the first active region and the second active region; and forming a metal interconnect layer connecting the third source / drain region and the fourth source / drain region on the exposed back side surface of the first insulating layer.

8. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The process of removing the semiconductor substrate to expose the bottom surfaces of the first and second active regions and forming a metal interconnect layer includes: removing a portion of the semiconductor substrate; etching the remaining semiconductor substrate to form vias in the remaining semiconductor substrate that expose the bottom surfaces of the first and second active regions; and forming a metal interconnect layer connecting the third and fourth source / drain regions on the surface of the remaining semiconductor substrate on the back surface of the first insulating layer and in the vias.

9. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The first active region and the second active region are made of single-crystal semiconductor material, and the first active region and the second active region are formed by epitaxial process.

10. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The impurity ions doped in the third source / drain region and the first source / drain region are of type N, and the impurity ions doped in the fourth source / drain region and the second source / drain region are of type P.

11. The method for forming a 3D CMOS device as described in claim 1, characterized in that, The impurity ions doped in the third source / drain region and the first source / drain region are of type P, and the impurity ions doped in the fourth source / drain region and the second source / drain region are of type N.

12. The method for forming a 3D CMOS device as described in claim 10 or 11, characterized in that, The first source / drain region and the second source / drain region are formed by a first ion implantation process and a second ion implantation process, respectively, and the types of impurity ions implanted by the first ion implantation process and the second ion implantation process are opposite.

13. The method for forming a 3D CMOS device as described in claim 12, characterized in that, The third and fourth source / drain regions are formed by a third ion implantation process and a fourth ion implantation process, respectively, and the types of impurity ions implanted by the third and fourth ion implantation processes are opposite.

14. A 3D CMOS device, characterized in that, include: A first insulating layer, the first insulating layer comprising a front surface and a back surface opposite to the front surface; A first vertical gate and a second vertical gate are separated on the front surface of the first insulating layer. A second insulating layer covering the front surface of the first vertical gate, the second vertical gate, and the first insulating layer; A first active region located in the second insulating layer, the first vertical gate and the first insulating layer, and a second via located in the second insulating layer, the second vertical gate and the first insulating layer; A first gate dielectric layer located between the first active region and the first vertical gate, and a second gate dielectric layer located between the second active region and the second vertical gate; The first source / drain region is located at the top of the first active region, and the second source / drain region is located at the top of the second active region. The types of impurity ions doped in the first source / drain region and the second source / drain region are opposite. The third source / drain region is located at the bottom of the first active region, and the fourth source / drain region is located at the bottom of the second active region. The third source / drain region is doped with the same type of impurity ions as the first source / drain region, and the fourth source / drain region is doped with the same type of impurity ions as the second source / drain region. A metal bonding layer connecting the third and fourth source / drain regions located on the back surface of the first insulating layer.

15. The 3D CMOS device as claimed in claim 14, characterized in that, Also includes: An interlayer dielectric layer is located on the second insulating layer, and a first metal wiring layer and a second metal wiring layer are located in the interlayer dielectric layer. The first metal wiring layer is electrically connected to the first source-drain region, and the second metal wiring layer is electrically connected to the second source-drain region.

16. The 3D CMOS device as claimed in claim 15, characterized in that, It also includes: a top silicon oxide layer located on the surface of the interlayer dielectric layer; a carrier plate located on the top silicon oxide layer and bonded to the top silicon oxide layer; a third via located in the first insulating layer, the second insulating layer and the interlayer dielectric layer, exposing the bottom surface of the first metal wiring layer and a fourth via located in the second metal wiring layer; a first via connection structure located in the third via and a second via connection structure located in the fourth via.

17. The 3D CMOS device as claimed in claim 14, characterized in that, The first gate dielectric layer and the second gate dielectric layer are made of silicon oxide or high-k dielectric material, the first vertical gate and the second vertical gate are made of polycrystalline silicon or metal, and the first active region and the second active region are made of single-crystal semiconductor material.

18. The 3D CMOS device as claimed in claim 14, characterized in that, The impurity ions doped in the third source / drain region and the first source / drain region are of type N, and the impurity ions doped in the fourth source / drain region and the second source / drain region are of type P.

19. The 3D CMOS device as claimed in claim 14, characterized in that, The impurity ions doped in the third source / drain region and the first source / drain region are of type P, and the impurity ions doped in the fourth source / drain region and the second source / drain region are of type N.

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