Semiconductor structure and semiconductor memory

Abstract

The present disclosure provides a semiconductor structure and a semiconductor memory, and relates to the technical field of semiconductor technology. The semiconductor structure comprises a substrate, a plurality of active pillars, a plurality of word lines and a dielectric layer covering the active pillars and the word lines. The plurality of active pillars are arranged on the substrate in a spaced manner. The plurality of word lines are arranged on the substrate in a spaced manner along a second direction, and each word line extends along a first direction. Each word line is connected to an active pillar located in the first direction. In any two adjacent word lines, at least one surface of the word line faces the other word line and has a groove. The dielectric layer between the adjacent word lines has an air gap. The present disclosure increases the distance between the adjacent word lines, reduces the dielectric constant of the dielectric layer between the adjacent word lines, maximally reduces the parasitic capacitance between the adjacent word lines, reduces the interference of the parasitic capacitance on the semiconductor structure, and improves the stability of I / O data transmission of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor structure and a semiconductor memory. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data, and is widely used in data storage devices. DRAM typically consists of multiple memory cells, each of which usually includes a capacitor and a transistor. The gate of the transistor is electrically connected to the word line (WL), and one of the transistor's source or drain is electrically connected to the bit line (BL).

[0003] However, as dynamic random access memory (DRAM) moves towards integration, it causes large parasitic capacitances between adjacent word lines, reducing the performance of DRAM. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a semiconductor structure and a semiconductor memory to reduce the parasitic capacitance between adjacent word lines and improve the performance of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure comprising:

[0006] Base;

[0007] Multiple active columns are spaced apart on the substrate, and each active column extends in a direction perpendicular to the substrate.

[0008] Multiple character lines are spaced apart on the substrate along a second direction, and each character line extends along a first direction, wherein the first and second directions intersect, and each character line connects to the active post located in the first direction; in any two adjacent character lines, at least one character line has a groove on its surface facing the other character line, and the groove penetrates the character line in a direction perpendicular to the substrate;

[0009] A dielectric layer is disposed on the substrate and covers a plurality of active posts and a plurality of word lines; wherein an air gap is present in the dielectric layer between adjacent word lines.

[0010] In some embodiments, the word line includes a plurality of first segments and second segments connected in sequence and arranged alternately; the first segment surrounds the active post;

[0011] At least one of the second segments is provided with the groove, and the air gap is provided in the dielectric layer between adjacent first segments along the second direction.

[0012] In some embodiments, in the second direction, the second segment has a first surface and a second surface disposed opposite to each other; the groove is provided on both the first surface and the second surface.

[0013] In some embodiments, the cross-section is a section parallel to the base, and the cross-sectional shape of the groove includes a rectangle, a trapezoid, or a semicircle.

[0014] In some embodiments, when the cross-sectional shape of the groove is trapezoidal, the distance between the two sidewalls of the groove gradually decreases from the groove opening to the bottom of the groove.

[0015] In some embodiments, the ratio of the depth of the groove to the width of the character line along the extension direction perpendicular to the character line is between 1 / 10 and 1 / 4.

[0016] In some embodiments, along a direction perpendicular to the substrate, the top surface of the air gap is flush with or higher than the top surface of the letter line.

[0017] In some embodiments, the width of the air gap ranges from 5 nm to 10 nm along the extension direction perpendicular to the letter line.

[0018] In some embodiments, the longitudinal section is a section perpendicular to the substrate, and the longitudinal section shape of the air gap is elliptical.

[0019] In some embodiments, the substrate may further include a plurality of bit lines spaced apart along a first direction, the bit lines extending along a second direction, and each bit line connecting to an active post located in the same second direction.

[0020] In some embodiments, a plurality of capacitors are also included, each of which corresponds to one of the plurality of active posts and is disposed on the active posts accordingly.

[0021] In some embodiments, the active post includes a channel region and a source region and a drain region respectively disposed on both sides of the channel region;

[0022] A portion of the letter line surrounds the channel area;

[0023] One of the source region and the drain region is connected to the capacitor, and the other of the source region and the drain region is connected to the bit line.

[0024] In some embodiments, a gate oxide layer is disposed between the word line and the channel region.

[0025] In some embodiments, the capacitor has a columnar structure, comprising a columnar first electrode and a dielectric layer and a second electrode sequentially surrounding the first electrode, wherein the first electrode is in electrical contact with the active column.

[0026] This disclosure also provides a semiconductor memory, which includes at least the semiconductor structure described above.

[0027] The semiconductor structure and semiconductor memory provided in this disclosure have a groove on the surface of at least one word line facing the other word line in any two adjacent word lines, which increases the distance between adjacent word lines, thereby reducing the parasitic capacitance between adjacent word lines and improving the performance of the semiconductor structure.

[0028] In addition, air gaps are present in the dielectric layer between adjacent word lines to reduce the dielectric constant of the dielectric layer between adjacent word lines, thereby reducing the parasitic capacitance between adjacent word lines and improving the performance of the semiconductor structure.

[0029] In addition to the technical problems solved by the embodiments of this disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and semiconductor memory provided by the embodiments of this disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of the semiconductor structure provided in the embodiments of this disclosure. Figure 1 ;

[0032] Figure 2 for Figure 1 A cross-sectional view along the AA direction;

[0033] Figure 3 for Figure 1 Cross-sectional view along the BB direction;

[0034] Figure 4 Schematic diagram of the semiconductor structure provided in the embodiments of this disclosure Figure 2 ;

[0035] Figure 5 Schematic diagram of word lines provided for embodiments of this disclosure Figure 1 ;

[0036] Figure 6 A schematic diagram of the word lines provided in the embodiments of this disclosure. Figure 2 ;

[0037] Figure 7 Schematic diagram of the semiconductor structure provided in the embodiments of this disclosure Figure 3 ;

[0038] Figure 8 Schematic diagram of the semiconductor structure provided in the embodiments of this disclosure Figure 4 ;

[0039] Figure 9 This is a schematic diagram of a capacitor provided in an embodiment of this disclosure.

[0040] Figure label:

[0041] 10: Substrate; 11: Well region; 12: Shallow trench isolation structure; 20: Active pillar; 21: Channel region; 22: Source region; 23: Drain region; 30: Word line; 31: First segment; 32: Second segment; 321: First surface; 322: Second surface; 33: Groove; 40: Dielectric layer; 41: Air gap; 50: Bit line; 60: Capacitor; 61: First electrode; 62: Dielectric layer; 63: Second electrode; 70: Gate oxide layer. Detailed Implementation

[0042] As described in the background section, semiconductor structures in related technologies suffer from large parasitic capacitance. The inventors have discovered that this problem arises because, as the integration density of semiconductor structures continues to increase, the spacing between semiconductor devices becomes smaller. For example, parasitic capacitance is formed between adjacent word lines. The parasitic capacitance is directly proportional to the dielectric constant of the dielectric layer between adjacent word lines and inversely proportional to the distance between adjacent word lines. Therefore, as the distance between adjacent word lines decreases, the parasitic capacitance increases, thereby increasing the risk of signal interference between adjacent word lines and reducing the performance of the semiconductor structure.

[0043] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and a semiconductor memory. By having a groove on the surface of at least one word line facing the other word line in any two adjacent word lines, the distance between adjacent word lines is increased, thereby reducing the parasitic capacitance between adjacent word lines and improving the performance of the semiconductor structure.

[0044] In addition, air gaps are present in the dielectric layer between adjacent word lines to reduce the dielectric constant of the dielectric layer between adjacent word lines, thereby reducing the parasitic capacitance between adjacent word lines and improving the performance of the semiconductor structure.

[0045] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0046] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0047] Please refer to the attached document. Figure 1 To be continued Figure 9 The present disclosure provides a semiconductor structure including: a substrate 10, a plurality of active pillars 20, a plurality of word lines 30 and a dielectric layer 40.

[0048] The substrate 10 is used to support semiconductor devices disposed thereon, such as active pillars 20 and word lines 30. The substrate 10 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate, etc.

[0049] Please refer to the attached document. Figure 2 and attached Figure 3 The substrate 10 includes a well region 11. If a P-type region is diffused on an N-type semiconductor substrate, it is called a P-well; if an N-type region is diffused on a P-type semiconductor substrate, it is called an N-well. No limitation is made here. In some embodiments, a shallow trench isolation (STI) structure 12 can be provided between multiple bit lines 50 to separate the multiple bit lines 50, ensuring that each bit line 50 is independent and insulated from each other.

[0050] In forming the shallow trench isolation structure 12, shallow trenches can be formed within the substrate using a patterning process, and insulating material can be filled within the shallow trenches. This defines multiple bitline regions to be formed within the substrate 10, separated by the shallow trench isolation structure 12. The patterning process can be either Self-Aligned Double Patterning (SADP) or Self-Aligned Quadruple Patterning (SAQP). The insulating material can be silicon oxide.

[0051] Multiple active pillars 20 are arranged in multiple rows and columns on the substrate 10, that is, multiple active pillars 20 are arranged in a regular rectangular array, wherein each active pillar 20 extends in a direction perpendicular to the substrate 10 to facilitate the subsequent formation of VGG transistors.

[0052] Multiple word lines 30 are spaced apart on the base 10 along a second direction, each word line 30 extends along a first direction, wherein the first direction and the second direction intersect, and each word line 30 is connected to an active column 20 located in the first direction.

[0053] In one example, please refer to the appendix. Figure 1 The first direction can be understood as the attached direction. Figure 1 In the X direction, the second direction can be understood as the appendix. Figure 1 The Y direction. Each word line 30 extends along the first direction to connect all active posts 20 located in the same first direction.

[0054] In another example, please refer to the appendix. Figure 4 The first direction can be understood as the attached direction. Figure 4 In the Y direction, the second direction can be understood as the appendix. Figure 4 The X direction is defined in the first direction. Each word line 30 extends along the first direction to connect all active pillars 20 located in the same first direction. In this way, one word line 30 can control all active pillars 20 in the same first direction, improving the control accuracy of the semiconductor structure.

[0055] In any two adjacent character lines 30, at least one character line 30 has a groove 33 on its surface facing the other character line 30, the groove 33 penetrating the character line 30 in a direction perpendicular to the base 10. In one example, please refer to the appendix. Figure 5 One of the character lines 30 has a groove 33 on its surface facing the other character line 30. For example, in two adjacent character lines 30, from top to bottom, the surface of the first character line 30 facing the second character line 30 has a groove 33. Or, for another example, the surface of the second character line 30 facing the first character line 30 has a groove 33.

[0056] In another example, please refer to the appendix. Figure 1 Grooves 33 are provided on the opposing surfaces of the two word lines 30. Compared with the related art where the surface of the word lines 30 is flat, this increases the spacing between adjacent word lines 30, reduces the parasitic capacitance between adjacent word lines 30, and thus reduces the parasitic capacitance of the semiconductor structure.

[0057] Please continue to refer to the appendix. Figure 2 The semiconductor structure also includes a dielectric layer 40, which is disposed on the substrate 10 and covers the plurality of active pillars 20 and the plurality of word lines 30. This provides insulation between the active pillars 20 and the word lines 30, preventing electrical connections between them and improving the yield of the semiconductor structure. The dielectric layer 40 may be made of silicon oxide or silicon nitride, but is not limited to these materials.

[0058] An air gap 41 is provided in the dielectric layer 40 located between adjacent word lines 30. This reduces the dielectric constant of the dielectric layer 40 located between adjacent word lines 30, thereby reducing the parasitic capacitance between adjacent word lines and improving the performance of the semiconductor structure.

[0059] This embodiment reduces the dielectric constant of the dielectric layer 40 located between adjacent word lines 30 while simultaneously reducing the spacing between adjacent word lines 30. This minimizes the parasitic capacitance between adjacent word lines 30, reduces the interference of parasitic capacitance on the semiconductor structure, and improves the stability of I / O data transmission in the semiconductor structure.

[0060] In one possible implementation, please refer to the appendix. Figure 6 Each character line 30 includes multiple first segments 31 and multiple second segments 32, which are alternately arranged and connected to each other.

[0061] The first segment 31 surrounds the active pillar 20 and forms a transistor with the active pillar 20. The second segment 32 connects to the adjacent first segment 31 so that the plurality of second segments 32 and the plurality of first segments 31 are interconnected to form a word line 30 extending along a first direction.

[0062] The groove 33 can be disposed on either the first segment 31 or the second segment 32. For example, the groove 33 can be disposed on the second segment 32. This avoids damage to the active pillars, improving the yield of the semiconductor structure. Furthermore, by positioning the groove 33 away from the active pillars, its depth can be maximized. This increases the distance between adjacent word lines 30 at the location of the groove 33, thereby reducing the parasitic capacitance between adjacent word lines 30.

[0063] In this embodiment, the groove 33 is disposed on at least one second segment 32. In one example, there is one groove 33, which can be disposed on one of the second segments 32. In another example, there are multiple grooves 33, which are less than the number of second segments 32, so that the grooves 33 can be disposed on some of the second segments 32. In yet another example, the number of grooves 33 is the same as the number of second segments 32, with one groove 33 disposed on each second segment 32. This minimizes the parasitic capacitance generated between adjacent word lines 30, thereby reducing the interference of parasitic capacitance on the semiconductor structure and improving the stability of I / O data transmission in the semiconductor structure.

[0064] In this embodiment, the groove 33 can be disposed on one surface of the second segment 32, or simultaneously on both surfaces of the second segment 32. Exemplarily, in the second direction Y, the second segment 32 has a first surface 321 and a second surface 322 disposed opposite to each other, for attachment... Figure 6 Taking the orientation shown as an example, the first surface 321 is the upper surface of the second segment 32, and the second surface 322 is the lower surface of the second segment 32.

[0065] Both the first surface 321 and the second surface 322 are provided with grooves 33, and the grooves 33 penetrate the word line 30 in a direction perpendicular to the substrate 10, so that the grooves 33 are through slots that penetrate the thickness of the word line 30. In this way, the distance between the word line 30 and any adjacent word line 30 is increased, ensuring that there is a small parasitic capacitance between adjacent word lines 30 and improving the performance of the semiconductor structure.

[0066] It should be noted that the number of grooves 33 on the second segment 32 can be one or two. When there are two grooves 33, the two grooves 33 are spaced apart on the second segment 32.

[0067] Please refer to the attached document. Figure 1 Appendix Figure 7 and attached Figure 8 With the cross-section parallel to the base 10 as the cross-section, the cross-sectional shape of the groove 33 can be a regular shape, such as a rectangle, trapezoid, or semicircle. The cross-sectional shape of the groove 33 can also be an irregular shape, such as a serrated shape.

[0068] When the cross-sectional shape of the groove 33 is a regular shape, it is convenient to prepare the groove 33 and reduce the difficulty of preparing the character line 30.

[0069] In one possible implementation, when the cross-sectional shape of the groove 33 is trapezoidal, the distance between the two sidewalls of the groove 33 gradually decreases from the groove opening to the bottom; that is, the cross-sectional shape of the groove 33 is an inverted trapezoid. This configuration reduces parasitic capacitance between adjacent word lines while avoiding excessive reduction in word line width, thus preventing an increase in word line resistance and improving signal transmission stability on the word lines.

[0070] In this embodiment, the distance between the two sidewalls of the groove 33 can be understood as the approximate distance between the two sidewalls. Figure 6 L in the middle.

[0071] In one possible implementation, along the extension direction perpendicular to the letter line 30, that is, along the attached... Figure 6 In the Y direction shown, the ratio of the depth H of the groove 33 to the width of the letter line 30 is between 1 / 10 and 1 / 4.

[0072] If the ratio of the depth of the groove 33 to the width of the word line 30 is less than 1 / 10, the depth of the groove 33 will be too small. This will not effectively reduce the parasitic capacitance formed by adjacent word lines 30, and will not achieve the effect of improving the performance of the semiconductor structure.

[0073] If the ratio of the depth of the groove 33 to the width of the word line 30 is greater than 1 / 4, the depth of the groove 33 will be too large, which will reduce the width of the word line 30, increase the resistance of the word line 30, and thus reduce the stability of signal transmission data in the semiconductor structure.

[0074] Therefore, in this embodiment, the ratio of the depth of the groove 33 to the width of the word line 30 is between 1 / 10 and 1 / 4. On the one hand, this increases the distance between adjacent word lines 30, reduces the parasitic capacitance generated by adjacent word lines 30, thereby reducing the interference of parasitic capacitance and improving the stability of semiconductor structure I / O data transmission.

[0075] On the other hand, it will not excessively reduce the width of word line 30, thus improving the stability and timeliness of signal transmission data in the semiconductor structure.

[0076] In one possible implementation, an air gap 41 is disposed within the dielectric layer 40 between the first segments 31. This prevents the formation of grooves 33 on the first segments 31, avoiding an increase in the resistance of the word lines 30. Simultaneously, by utilizing the lower dielectric constant of the air gap 41 compared to the dielectric layer 40, the dielectric constant of the dielectric layer 40 located between adjacent first segments 31 is reduced, thereby reducing the parasitic capacitance generated between adjacent word lines 30 and improving the performance of the semiconductor structure.

[0077] In one possible implementation, the longitudinal section perpendicular to the base 10 is used as the longitudinal section, and the longitudinal section shape of the air gap 41 is elliptical. It should be noted that the cross-sectional shape of the air gap 41 can also be other regular shapes, such as rectangles, squares, trapezoids, or circles, to facilitate the fabrication of the air gap 41. Of course, under different process parameters, the cross-sectional shape of the air gap 41 may also be other irregular shapes.

[0078] In one possible implementation, please continue to refer to the appendix. Figure 2 Along a direction perpendicular to the substrate 10, the top surface of the air gap 41 is flush with or higher than the top surface of the word line 30. That is, the air gap 41 is entirely located within the dielectric layer 40 between adjacent word lines 30, or a portion of the air gap 41 is located within the dielectric layer 40 between adjacent word lines 30.

[0079] In one possible implementation, the width of the air gap 41 ranges from 5 nm to 10 nm along the extension direction perpendicular to the word line 30.

[0080] If the width of the air gap 41 is less than 5nm, the width of the air gap 41 will be too small, which will result in the volume of the air gap 41 being too small, making it difficult to reduce the dielectric constant of the dielectric layer 40 located between adjacent word lines 30.

[0081] If the width of the air gap 41 is greater than 10nm, it will result in the air gap 41 being too wide, which in turn will result in the dielectric layer 40 between adjacent word lines 30 being too narrow, and may even cause electrical connection between adjacent word lines 30, reducing the yield of the semiconductor structure.

[0082] Therefore, in this embodiment, the width of the air gap is in the range of 5nm to 10nm. On the one hand, this can reduce the dielectric constant of the dielectric layer 40 located between adjacent word lines 30, reduce the parasitic capacitance generated by adjacent word lines 30, thereby reducing the interference of parasitic capacitance and improving the stability of semiconductor structure I / O data transmission.

[0083] On the other hand, it will not excessively reduce the width of the dielectric layer 40 located between adjacent word lines 30, preventing electrical connections between adjacent word lines 30 and improving the yield of the semiconductor structure.

[0084] In one possible implementation, the semiconductor structure further includes a plurality of bit lines 50, wherein the plurality of bit lines 50 are spaced apart within the substrate 10 along a first direction, and each bit line 50 extends along a second direction for connecting all active pillars 20 located in the same second direction.

[0085] When forming bit lines 50, a conductive layer of a certain thickness can be deposited on the substrate 10. Then, the conductive layer is patterned to remove part of the conductive layer, and the remaining conductive layer forms multiple bit lines. The material of bit lines 50 may include silicon germanide. Compared with the related technology that uses titanium nitride and tungsten as bit lines, the high mobility of germanium can reduce the resistance of bit lines 50 and improve the performance of the semiconductor structure. In addition, in this embodiment, bit lines 50 are formed together with the fabrication of active pillars 20, which can simplify the semiconductor structure fabrication process.

[0086] The semiconductor structure also includes multiple capacitors 60, which correspond one-to-one with multiple active pillars 20 and are disposed on the active pillars 20. That is, the number of capacitors 60 is equal to the number of active pillars 20, and one capacitor 60 is disposed on each active pillar 20.

[0087] Please refer to the attached document. Figure 9 The capacitor 60 has a columnar structure, including a columnar first electrode 61 and a dielectric layer 62 and a second electrode 63 sequentially surrounding the first electrode 61. The first electrode 61 is electrically connected to the active pillar 20. This increases the volume and strength of the first electrode 61, thereby reducing the fabrication difficulty of the first electrode 61 and preventing its collapse, thus improving the yield of the semiconductor structure.

[0088] It should be noted that in this example, the first electrode 61 and the second electrode 63 are made of the same material, for example, they may include tungsten metal or titanium nitride, but are not limited to these.

[0089] The dielectric layer 62 can be made of a dielectric material with a high dielectric constant. For example, the dielectric material can include at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx. That is, the dielectric layer 62 can be made of one of the above materials or a mixture of the above materials. Optionally, the dielectric layer 62 can be a stacked structure. For example, the dielectric layer 62 can include a three-layer structure, and the materials of the three layers are zirconium oxide-aluminum oxide-zirconia, respectively. The dielectric layer 62 can include a zirconium oxide layer, an aluminum oxide layer, and a zirconium oxide layer stacked sequentially.

[0090] This embodiment, by limiting the material of the dielectric layer 62, can increase the storage capacity of the subsequently formed capacitor structure and improve the performance of the semiconductor structure.

[0091] In this embodiment, one end of the active post 20 is connected to the bit line 50, and the other end of the active post 20 is connected to the capacitor 60. In this way, data can be written into the capacitor 60 through the bit line 50, or data in the capacitor 60 can be read out through the bit line 50, so as to realize the reading function of the semiconductor structure.

[0092] In this embodiment, the capacitor 60 can be fabricated as follows: multiple capacitor holes can be formed in the dielectric layer 40, each capacitor hole exposing at least the top surface of each active pillar 20, and then the capacitor 60 can be formed in the capacitor holes using a deposition process.

[0093] In one possible implementation, please continue to refer to the appendix. Figure 2 The active post 20 includes a channel region 21, a source region 22, and a drain region 23, with the source region 22 and drain region 23 respectively located on both sides of the channel region 21. Specifically, from top to bottom, the area between the top of the active post 20 and the first dashed line is the source region 22, the area between the first and second dashed lines is the channel region 21, and the area between the second dashed line and the bottom of the active post 20 is the drain region 23.

[0094] The dopant ions in source region 22 and drain region 23 are of the same type, but different from the dopant ions in channel region 21. In one example, the dopant ions in source region 22 and drain region 23 may include N-type ions, such as elements in Group VA of the periodic table, like phosphorus (P); the dopant ions in channel region 21 may include P-type ions, such as boron (B) or gallium (Ga) from Group IIIA elements, such as gallium (Ga), to form an NPN type active pillar 20. In another example, the dopant ions in source region 22 and drain region 23 may include P-type ions, such as boron (B) or gallium (Ga) from Group IIIA elements; the dopant ions in channel region 21 may include N-type ions, such as phosphorus (P) from Group VA of the periodic table, to form a PNP type active pillar 20.

[0095] In this embodiment, the fabrication process of the active pillar 20 can be carried out as follows: In one example, an active layer can be formed on the substrate 10, and then a plurality of first trenches and a plurality of second trenches can be formed in the active layer by etching. The plurality of first trenches are spaced apart along a second direction and extend along a first direction; the plurality of second trenches are spaced apart along the first direction and extend along the second direction. The active layer is divided into multiple pillar-like structures by the plurality of first trenches and second trenches.

[0096] Subsequently, the columnar structure can be doped using ion implantation or ion diffusion processes to form active columns 20.

[0097] In another example, a first active layer, a second active layer, and a third active layer may be formed on the substrate 10 in a stacked manner. The dopant ions of the first active layer and the third active layer are of the same type and are used to form the subsequent source and drain regions. The dopant ions of the second active layer are of a different type than those of the first active layer and are used to form the subsequent channel region.

[0098] Subsequently, the first active layer, the second active layer, and the third active layer are graphically visualized to form a plurality of active pillars 20 arranged in an array on the substrate 10.

[0099] It should be noted that in this example, the first active layer, the second active layer, and the third active layer can all be prepared using in-situ doping processes. For example, a silicon layer can be formed on the substrate 10 using an epitaxial growth process. At the same time, N-type ions, such as phosphorus ions, are introduced into the deposition equipment during the growth process, so that the N-type ions are doped into the silicon layer to form the first active layer.

[0100] A portion of the word line 30 is wrapped around the channel region 21, that is, the first segment 31 is wrapped around the channel region 21, so that the first segment 31 and the active pillar 20 form a transistor, and the voltage on the first segment 31 is used to control whether the source region 22 and the drain region 23 of the active pillar 20 are connected or disconnected.

[0101] A gate oxide layer 70 is disposed between the word line 30 and the channel region 21. The gate oxide layer 70 has a high dielectric constant to increase the charge storage capacity of the gate oxide layer 70, prevent electrons generated by the word line 30 or a small number of current carriers from entering the drain region 23 of the active pillar 20 through the gate oxide layer 70, reduce the gate-induced drain leakage current, and improve the performance of the semiconductor structure.

[0102] One of the source region 22 and the drain region 23 is connected to the capacitor 60, and the other of the source region 22 and the drain region 23 is connected to the bit line 50. In one example, if the source region 22 is connected to the capacitor 60, then the drain region 23 is connected to the bit line 50. In another example, if the source region 22 is connected to the bit line 50, then the drain region 23 is connected to the capacitor 60.

[0103] When the external circuit applies a high potential to the word line 30, the word line 30 will apply the potential to the channel region 21, thereby controlling the connection between the source region 22 and the drain region 23 of the active pillar 20, thereby realizing the access function of the semiconductor structure.

[0104] This disclosure also provides a semiconductor memory, which includes the semiconductor structure described in the above embodiments. The structure and beneficial effects of the semiconductor structure have been described in detail in the above embodiments, and will not be repeated here.

[0105] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0106] In the description of this specification, references to terms such as “one embodiment,” “some embodiments,” “illustrative embodiment,” “example,” “specific example,” or “some examples” refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure.

[0107] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0108] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Base; Multiple active columns are spaced apart on the substrate, and each active column extends in a direction perpendicular to the substrate. Multiple character lines are spaced apart on the substrate along a second direction, and each character line extends along a first direction, wherein the first and second directions intersect, and each character line connects to the active post located in the first direction; in any two adjacent character lines, at least one character line has a groove on its surface facing the other character line, and the groove penetrates the character line in a direction perpendicular to the substrate; A dielectric layer is disposed on the substrate and covers a plurality of active posts and a plurality of word lines; wherein an air gap is present in the dielectric layer between adjacent word lines.

2. The semiconductor structure according to claim 1, characterized in that, The word line includes multiple first segments and second segments connected sequentially and arranged alternately; the first segment surrounds the active column; At least one of the second segments is provided with the groove, and the air gap is provided in the dielectric layer between adjacent first segments along the second direction.

3. The semiconductor structure according to claim 2, characterized in that, In the second direction, the second segment has a first surface and a second surface that are disposed opposite to each other; the groove is provided on both the first surface and the second surface.

4. The semiconductor structure according to any one of claims 1-3, characterized in that, With a cross section parallel to the base as the cross section, the cross section shape of the groove includes a rectangle, a trapezoid, or a semicircle.

5. The semiconductor structure according to claim 4, characterized in that, When the cross-sectional shape of the groove is trapezoidal, the distance between the two sidewalls of the groove gradually decreases from the groove opening to the bottom of the groove.

6. The semiconductor structure according to any one of claims 1-3, characterized in that, Along the extension direction perpendicular to the character line, the ratio of the depth of the groove to the width of the character line is between 1 / 10 and 1 / 4.

7. The semiconductor structure according to any one of claims 1-3, characterized in that, Along a direction perpendicular to the base, the top surface of the air gap is flush with or higher than the top surface of the letter line.

8. The semiconductor structure according to claim 6, characterized in that, Along the extension direction perpendicular to the character line, the width of the air gap ranges from 5 nm to 10 nm.

9. The semiconductor structure according to claim 7, characterized in that, The longitudinal section of the air gap is elliptical, with the section perpendicular to the base as the longitudinal section.

10. The semiconductor structure according to any one of claims 1-3, characterized in that, It also includes a plurality of bit lines spaced apart in the substrate along a first direction, each bit line extending along a second direction, and each bit line connecting to the active post located in the same second direction.

11. The semiconductor structure according to claim 10, characterized in that, It also includes multiple capacitors, each of which corresponds to one of the multiple active posts and is disposed on the active posts accordingly.

12. The semiconductor structure according to claim 11, characterized in that, The active post includes a channel region and a source region and a drain region respectively disposed on both sides of the channel region; A portion of the letter line surrounds the channel area; One of the source region and the drain region is connected to the capacitor, and the other of the source region and the drain region is connected to the bit line.

13. The semiconductor structure according to claim 12, characterized in that, A gate oxide layer is provided between the word line and the channel region.

14. The semiconductor structure according to claim 12, characterized in that, The capacitor has a columnar structure, comprising a columnar first electrode and a dielectric layer and a second electrode that surround the first electrode in sequence, wherein the first electrode is in electrical contact with the active column.

15. A semiconductor memory, characterized in that, The semiconductor memory includes at least the semiconductor structure as described in any one of claims 1 to 14.

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