Packaging structures and their fabrication methods, semiconductor devices

Abstract

This disclosure provides a packaging structure and its fabrication method, as well as a semiconductor device. The packaging structure includes: N first pads, each first pad being an interconnect layer exposed by a via; N redistribution layers, each redistribution layer covering an isolation layer and electrically connected to a corresponding first pad among the N first pads; a portion of the first pads are arranged side-by-side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side-by-side along the first direction near a second edge of the semiconductor functional structure; the exposed portion of each redistribution layer includes a second pad and a third pad; wherein the offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal; the relative positions between the second pads and third pads in a portion of the redistribution layer are different from the relative positions between the second pads and third pads in the other portion of the redistribution layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and includes, but is not limited to, a packaging structure and its manufacturing method, and semiconductor devices. Background Technology

[0002] With the rapid increase in the penetration rate of electronic devices and the booming development of the electronic device market, there is an increasing demand for electronic products to evolve towards miniaturization and thinning while possessing high performance, multifunctionality, high reliability, and convenience. This demand places higher requirements on semiconductor device packaging, demanding better, lighter, thinner packaging, higher packaging density, better electrical and thermal performance, higher reliability, and higher cost-effectiveness.

[0003] To ensure that the performance of semiconductor devices meets the corresponding requirements, ports for testing and performing functional interactions need to be fabricated on the package structure. Summary of the Invention

[0004] Based on this, in order to solve one or more of the related technical problems, this disclosure provides a packaging structure and its manufacturing method, as well as a semiconductor device.

[0005] According to one aspect of the embodiments of this disclosure, a packaging structure is provided, including:

[0006] An isolation layer having multiple vias covers the surface of an interconnect layer, the vias exposing portions of the interconnect layer, the interconnect layer being disposed on the surface of a semiconductor functional structure;

[0007] N first pads, each first pad consisting of an interconnect layer exposed by one of the vias; where N is a positive integer greater than 1;

[0008] N redistribution layers, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; a portion of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0009] A first insulating layer covers and exposes a portion of each of the redistribution layers;

[0010] Each exposed portion of the redistribution layer includes a second pad and a third pad; wherein the center point of each second pad is offset from the center point of the corresponding first pad in both direction and distance; the relative positions between the second pad and the third pad in some redistribution layers are different from those in other redistribution layers; the first pad and the second pad are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad.

[0011] In the above scheme, the second pad and the third pad included in each of the N redistribution layers are arranged side by side along a second direction, which is perpendicular to the first direction.

[0012] In the above scheme, the orthographic projection of the center point of each second pad on the plane where the interconnect layer is located is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

[0013] In the above scheme, the shape of the orthographic projection of each redistribution layer onto the plane where the interconnect layer is located includes a strip shape.

[0014] In the above scheme, the first end of a portion of the first pad near the first edge and the second end of a portion of the redistribution layer near the first edge are substantially flush along a third direction, and the third direction is perpendicular to both the first direction and the second direction;

[0015] The third end of another portion of the first pad near the second edge is substantially flush with the fourth end of another portion of the redistribution layer near the second edge along the third direction.

[0016] In the above scheme, the second pad in part of the redistribution layer is located near the second end, and the third pad is located away from the second end;

[0017] In another portion of the redistribution layer, the second pad is located near the fourth end, and the third pad is located away from the fourth end.

[0018] In the above scheme, each of the redistribution layers further includes a first region for making a conductive connection with the first pad;

[0019] In some redistribution layers, the second pad and the third pad are both located on one side of the first region; in other redistribution layers, the second pad and the third pad are both located on both sides of the first region.

[0020] In the above scheme, the redistribution layer is in direct contact with the corresponding first pad;

[0021] or,

[0022] The packaging structure further includes a conductive pillar located between the redistribution layer and the corresponding first pad, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillar.

[0023] In the above scheme, the encapsulation structure includes the conductive pillars, and the number of conductive pillars is multiple, with multiple conductive pillars arranged side by side along a first direction.

[0024] In the above scheme, the redistribution layer is in direct contact with the corresponding first pad, and the packaging structure further includes:

[0025] A second insulating layer is located within the groove formed by each of the redistribution layers, and the hardness of the material of the second insulating layer is less than that of the material of the redistribution layer.

[0026] According to another aspect of the present disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the present disclosure.

[0027] In the above scheme, the semiconductor device further includes:

[0028] substrate;

[0029] Multiple stacked dies; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure;

[0030] Each die is electrically connected to the substrate via a lead on the third pad in the package structure.

[0031] According to another aspect of the present disclosure, a method for manufacturing an encapsulation structure is provided, comprising:

[0032] A semiconductor functional structure is provided, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure;

[0033] An isolation layer with multiple vias is formed, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1;

[0034] After completing the first type of test, N redistribution layers are formed on the N first pads and the isolation layer. Each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads. A portion of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side by side along a first direction near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0035] A first insulating layer is formed to cover and expose a portion of the redistribution layer, with the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad is offset in both direction and distance relative to the center point of the corresponding first pad; the relative positions between the second pad and the third pad in a portion of the redistribution layer are different from the relative positions between the second pad and the third pad in another portion of the redistribution layer; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

[0036] In various embodiments of this disclosure, N first pads are provided in the top metal layer to perform a test on the semiconductor functional structure at a first operating speed. A portion of the first pads are arranged side-by-side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side-by-side along the first direction near a second edge of the semiconductor functional structure. After the test at the first operating speed is completed, second pads corresponding one-to-one with the first pads are provided in a redistribution layer on the first pads to perform a test on the semiconductor functional structure at a second operating speed. The relative positions between the second and third pads in a portion of the redistribution layer are different from those in the other portion of the redistribution layer. The relative positions between them are different; here, by setting the center point of each second pad to be offset in the same direction and by the same distance relative to the center point of the corresponding first pad, the N first pads and N second pads maintain the same relative position; at the same time, by setting the positions between the second pads and the third pads located at different edge positions to be different, the redistribution layers located at the two edge positions have a large fault tolerance, and can be close to the edge but not beyond the edge. In this way, it can be ensured that the first pads and the second pads are in advantageous positions that save the total area. At the same time, the same set of probe cards can be used to achieve the above two different running speed tests. Compared with using two sets of probe cards to perform tests separately, the test cost and test time are saved, and the production cycle and manufacturing cost are reduced. Attached Figure Description

[0037] Figure 1 This is a cross-sectional schematic diagram of an encapsulation structure provided in an embodiment of this disclosure;

[0038] Figure 2a This is a cross-sectional schematic diagram of another packaging structure provided in an embodiment of this disclosure;

[0039] Figure 2b for Figure 2a A top-down view;

[0040] Figure 2c This is a cross-sectional schematic diagram of a packaging structure with conductive pillars provided in an embodiment of this disclosure;

[0041] Figure 3 A schematic diagram showing the relative positions of the first and second pads provided in the embodiments of this disclosure;

[0042] Figure 4 This is a schematic diagram showing the relative positions of the second and third pads provided in the embodiments of this disclosure;

[0043] Figure 5This is a schematic flowchart illustrating a method for manufacturing a packaging structure according to an embodiment of this disclosure;

[0044] Figures 6a-6d This is a schematic diagram illustrating the manufacturing process of a packaging structure provided in an embodiment of this disclosure.

[0045] Explanation of reference numerals in the attached figures

[0046] 101-Top metal layer; 102-First type pad; 103-Redistribution layer; 104-Second type pad; 105-Third type pad; 200-Semiconductor functional structure; 201-Semiconductor functional layer; 202-Interconnect layer; 203-Isolation layer; 204-Via; 205-First pad; 2051-First portion of first pad; 2052-Second portion of first pad; 2051a-First end of first pad; 2052a-Third end of first pad; 206-Redistribution layer; 206a-Second end of redistribution layer; 206b - Fourth end of redistribution layer; 207 - Conductive pillar; 208 - First insulating layer; 209 - Groove; 210 - Second insulating layer; 211 - Second pad; 212 - Third pad; 213 - First region; 600 - Semiconductor functional structure; 601 - Semiconductor functional layer; 602 - Interconnect layer; 603 - Isolation layer; 604 - Via; 605 - First pad; 606 - Redistribution layer; 608 - First insulating layer; 609 - Groove; 610 - Second insulating layer; 611 - Second pad; 612 - Third pad.

[0047] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0048] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0049] The embodiments of this disclosure are described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of this disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this disclosure.

[0050] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0051] In the embodiments of this disclosure, the term "A and B connected" includes the case where A and B are in direct contact, or the case where A and B are in indirect contact through an intermediate conductive structure; the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0052] In the embodiments of this disclosure, the term "layer" refers to a portion of material including a region of thickness. A layer may extend onto the lower or upper surface of a structure, and its area may be less than or equal to the area of ​​the extending surface. It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0053] The semiconductor functional structure disclosed herein is a part of the process that will be used in subsequent manufacturing processes to form the final semiconductor device, and is a core component for realizing the main functions of the semiconductor device. Here, the final semiconductor device may include, but is not limited to, memory.

[0054] In the design of packaging structures for semiconductor devices such as Dynamic Random Access Memory (DRAM), pads (also known as solder pads) can be set in two ways: one is by opening windows in the top metal layer; the other is by opening windows in the redistribution layer (RDL).

[0055] The aforementioned top-layer metal windowing refers to forming a passivation layer or insulating layer on the top-layer metal layer of the semiconductor functional structure to protect it from damage. Then, a window area is formed on the passivation layer or insulating layer to expose a portion of the top-layer metal layer, forming a pad. Probe pin piercing tests can be performed on this pad to test the electrical performance of the semiconductor functional structure; bonding wires can also be led out on this pad to electrically expose the semiconductor functional structure.

[0056] The redistribution layer windowing refers to forming a redistribution layer on the top metal layer of the semiconductor functional structure, forming a passivation layer or insulating layer on the redistribution layer, and then forming a window area on the passivation layer or insulating layer to expose part of the redistribution layer, forming two pads arranged side by side. One of these pads is used for probe pin insertion testing, and the other is used for the lead-out of bonding wires on the pad. Here, the redistribution layer in the semiconductor device can adjust the position of the pads and also enhance the power supply network.

[0057] Understandably, the top metal layer is relatively thin and has a pad structure underneath, allowing for probe jacking testing on the same windowed metal area before wire bonding encapsulation at the packaging plant, without affecting the wire bonding yield. The redistribution layer, typically made of metal, is thicker than the top metal layer. Probe jacking leaves deeper and rougher pin marks, which affect the wire bonding yield. Therefore, the pads used for testing and those used for wire bonding in the redistribution layer need to be separate. Regardless of the windowing method used in the packaging structure, it doesn't significantly impact the function of the semiconductor device. Windowing in the redistribution layer improves performance but increases production cycle time and costs.

[0058] In related technologies, one of the two windowing methods mentioned above is generally chosen to design the packaging structure based on the actual needs of the semiconductor device. However, in practical applications, the needs in the semiconductor device manufacturing process are not singular; multiple needs often exist. Several examples of multiple needs are given below:

[0059] For example, before the mass production of semiconductor devices (or "products"), there is a lengthy functional debugging process. During this debugging process, testing is conducted at a low operating speed of the semiconductor functional structure. At this time, only the top-layer metal windowing method is needed to complete the packaging and testing of the semiconductor functional structure. However, after the product's manufacturing process matures, when it is necessary to test the state of the semiconductor functional structure under high-speed operation, a redistribution layer windowing method is required for packaging and testing.

[0060] Based on this, the present disclosure provides a packaging structure, referencing Figure 1 The packaging structure includes a top metal window method and a redistribution layer window method. In the top metal window method, a first type of pad 102 is provided in the top metal layer 101. The first type of pad 102 can be used to perform low-speed testing and lead out bonding wires. In the redistribution layer window method, two types of pads (a second type of pad 104 and a third type of pad 105) are provided in the redistribution layer 103. The second type of pad 104 is used to perform high-speed testing, and the third type of pad 105 is used to lead out bonding wires.

[0061] Here, on the one hand, when performing low-speed testing using the first type of pad 102, the test probe card needs to simultaneously hit the center point of all the first type of pads 102; on the other hand, when performing high-speed testing using the second type of pad 104, the test probe card needs to simultaneously hit the center point of all the second type of pads 104. However, from Figure 1 It can be seen that the first type of pad 102 and the second type of pad 104 are located in different layers of the packaging structure, and the relative positions of each first type of pad 102 and each second type of pad 104 in different layers are different. Thus, in order to meet the requirements of low-speed testing and high-speed testing, it is necessary to manufacture two sets of test probe cards, which will greatly increase the testing cost and testing time.

[0062] On the other hand, when there are many test points, it may be impossible to place all the first-type pads 102 at one edge of the semiconductor functional structure. In this case, the first-type pads need to be placed at two opposite edges of the semiconductor functional structure. Correspondingly, the redistribution layer 103 also needs to be placed at two opposite edges of the semiconductor functional structure. However, since the area occupied by the second-type pads 104 and the third-type pads 105 together is larger than the area occupied by the first-type pads 102, the redistribution layer 103 at at least one edge may extend beyond the edge.

[0063] Based on this, in order to further solve the above problems, this disclosure provides a packaging structure, a method for manufacturing the same, and a semiconductor device. The packaging structure includes: an isolation layer having multiple vias, the isolation layer covering the surface of an interconnect layer, the vias exposing a portion of the interconnect layer, and the interconnect layer disposed on the surface of a semiconductor functional structure; N first pads, each first pad being formed by one interconnect layer exposed by a via; N being a positive integer greater than 1; N redistribution layers, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; a portion of the first pads are arranged side-by-side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side-by-side along the first direction near the semiconductor functional structure. At the location of the second edge, the first edge and the second edge are two opposite edges of the semiconductor functional structure; a first insulating layer covers and exposes a portion of each redistribution layer; the exposed portion of each redistribution layer includes a second pad and a third pad; wherein the center point of each second pad is offset in both direction and distance relative to the center point of the corresponding first pad; the relative position between the second pad and the third pad in a portion of the redistribution layers is different from the relative position between the second pad and the third pad in another portion of the redistribution layers; the first pad and the second pad are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad.

[0064] It should be noted that the first direction involved in this embodiment is parallel to the surface of the semiconductor functional structure, the second direction involved in this embodiment is parallel to the semiconductor functional structure and perpendicular to the first direction, and the third direction involved in this embodiment is perpendicular to both the first and second directions. In some embodiments, the first direction may be parallel to the X-axis, the second direction may be parallel to the Y-axis, and the third direction may be parallel to the Z-axis.

[0065] Here, for reference Figure 2a The packaging structure includes: a substrate ( Figure 2a (Not shown in the image), the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI).

[0066] A semiconductor functional structure 200 is located on a substrate. Specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnect layer 202 located on the surface of the semiconductor functional layer 201. Various functional structures can be disposed in the semiconductor functional layer 201 according to actual needs. Correspondingly, the interconnect layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to operate the functional structures. In some embodiments, the interconnect layer 202 includes a top metal layer, which not only extracts the electrical signals from the functional structures but also supports the semiconductor functional structure 200.

[0067] It should be noted that any signals connected by the redistribution layer formed in subsequent processes are connected to the interconnect layer 202, which ensures that the function of the semiconductor functional structure 20 is complete even without the redistribution layer. Figure 2a The interconnect layer 202 shown is a cross-sectional view of a section after a portion has been removed. In actual applications, the parts of the interconnect layer are not cut off, but interconnected. That is, the parts of the interconnect layer may be continuous on other sections.

[0068] An isolation layer 203 covers the surface of the interconnect layer 202 and is used to isolate the interconnect layer 202 and the subsequently formed redistribution layer 205 in a partial area. A via 204 is provided in the isolation layer 203, exposing a portion of the interconnect layer 202. The via 204 can be cylindrical, inverted trapezoidal, or any suitable shape. The constituent materials of the isolation layer 203 include, but are not limited to, tetraethyl orthosilicate (TEOS).

[0069] A first pad 205 is formed by the interconnect layer 202 exposed by one of the vias 204; the isolation layer 203 may contain multiple vias 204, thereby forming a plurality of first pads 205 exposed by the vias 204. Here, the first pad 205 can be used for performing a first type of test on the one hand, and on the other hand, it can also be used to perform functional interactions corresponding to the content of the first type of test on the other hand.

[0070] For example, the first type of test can be understood as performing some tests on the semiconductor functional structure at a lower operating speed. It should be noted that in memory, the operating speed refers to the memory read / write speed. The functional interaction corresponding to the content of the first type of test can be understood as leading bonding wires onto the first pad. That is, when performing the first type of test, the first pad 205 can be used to contact the probe card, and multiple probes in the probe card correspond one-to-one with N first pads to achieve electrical connection between the interconnect layer and other test systems.

[0071] In practical applications, when there are many test points, it may be impossible to place all the first pads 205 at one edge of the semiconductor functional structure. In this case, the first pads 205 can be placed at two opposite edges of the semiconductor functional structure, as shown in the reference. Figure 2b Of the N first pads 205, each first pad is divided into two parts: a first part of first pads 2051 and a second part of first pads 2052. The first part of first pads 2051 includes M1 first pads, which are arranged side-by-side along a first direction near the first edge 20a of the semiconductor functional structure. The second part of first pads 2052 includes M2 first pads, which are arranged side-by-side along the first direction near the second edge 20b of the semiconductor functional structure. The first edge 20a and the second edge 20b are two opposite edges of the semiconductor functional structure. Here, M1 + M2 = N.

[0072] It should be noted that, Figure 2a This is a partial cross-sectional schematic diagram of the packaging structure in which the first pad 205 is in direct contact with the redistribution layer 206; Figure 2b Here is an example of a top view of an encapsulation structure, where, in Figure 2b To more clearly show the position and arrangement of the first pad, the other layers are hidden; Figure 2c This is a partial cross-sectional view of the encapsulation structure in which the first pad 205 is indirectly in contact with the redistribution layer 206 through the conductive post 207.

[0073] In some embodiments, the number of first pads 2051 in the first portion and the number of first pads 2052 in the second portion may be the same or different.

[0074] Specifically, Figure 2b The six first pads are divided into a first part first pad 2051 and a second part first pad 2052. The first part first pad 2051 includes three first pads arranged side by side along the first direction near the first edge 20a of the semiconductor functional structure. The second part first pad 2052 includes three first pads arranged side by side along the first direction near the second edge 20b of the semiconductor functional structure.

[0075] refer to Figure 2a N redistribution layers 206 are located on the surface of the isolation layer 203 and on the via 204. Here, each redistribution layer 206 covers the isolation layer 203; and the N redistribution layers 206 are in direct contact with the corresponding first pad 205 among the N first pads 205.

[0076] The redistribution layer 206 and the first pad 205 can be in direct contact (see reference). Figure 2a Indirect contact is also possible, i.e., a conductive material layer is disposed between the redistribution layer 206 and the first pad 205 (see reference). Figure 2b , Figure 2c For example, conductive post 207). The material of the conductive post 207 can be the same as or different from the material of the redistribution layer 206. It should be noted that the height of the conductive post 207 can be less than or equal to the depth of the via 204. Figure 2c The case shown is where the height of the conductive post 207 is equal to the depth of the via 204.

[0077] In some embodiments, the encapsulation structure includes the conductive pillars 207, and the number of conductive pillars includes a plurality of conductive pillars arranged side by side along a first direction.

[0078] In the above embodiments, the number of conductive posts 207 in the same via 204 may include one or more, and adjacent conductive posts 207 are isolated by insulating material; correspondingly, each conductive post 207 corresponds to a first pad 205, that is, when the number of conductive posts 207 is multiple, the bottom of the same via 204 has multiple first pads 205.

[0079] It is understood that when there are multiple conductive posts 207, all of them are connected to the redistribution layer 206 and the interconnection layer 202, which can increase the reliability of the electrical connection between the redistribution layer 206 and the interconnection layer 202.

[0080] It is understandable that by setting multiple first pads 205 while keeping the bottom area of ​​the via constant, it is beneficial to reduce the total area of ​​all first pads 205 at the bottom of the same via 204, thereby reducing the parasitic capacitance between the first pads 205 and the surrounding conductive material, which is beneficial to further optimize signal transmission performance.

[0081] refer to Figure 2a The first insulating layer 208 is located on the redistribution layer 206.

[0082] The first insulating layer 208 covers the surface of the redistribution layer 206. The thickness of the redistribution layer 206 on the exposed portion of the interconnect layer 202 can be the same as the thickness of the redistribution layer 206 on the surface of the isolation layer 203. In some embodiments, when the diameter of the via 204 is greater than twice the thickness of the redistribution layer 206, the redistribution layer 206 covers the sidewalls and bottom of the via 204, and the redistribution layer 206 forms a groove 209.

[0083] In some embodiments, reference Figure 2aThe redistribution layer 206 is in direct contact with the corresponding first pad 205. The encapsulation structure further includes a second insulating layer 210 located within the groove 209 formed by each redistribution layer. The hardness of the material of the second insulating layer 210 is less than that of the material of the redistribution layer 206. In this way, on the one hand, the stress of the encapsulation structure can be reduced and the reliability of the encapsulation structure can be increased; on the other hand, compared with using the redistribution layer 206 to fill the groove 208, using the material of the second insulating layer 210 to fill the groove 208 can avoid generating more parasitic capacitance.

[0084] In some embodiments, the second insulating layer 210 and the first insulating layer 208 can be an integral structure or a separate structure. When they are separate structures, their materials can be different. Figure 2a The diagram shows a case where the second insulating layer 210 and the first insulating layer 208 are integrally formed. The constituent materials of the second insulating layer 210 include, but are not limited to, polyimide (PI).

[0085] refer to Figure 2a At least some of the redistribution layers 206 have exposed portions including the second pad 211 and the third pad 212.

[0086] Here, each of the N redistribution layers 206 has a second pad 211 and a third pad 212; in other words, the N second pads 211 and N third pads 212 correspond one-to-one. The second pad 211 is used for performing a second type of test, and the third pad 212 is used to perform functional interactions corresponding to the content of the second type of test. The second type of test can be understood as some tests performed on the semiconductor functional structure at high operating speeds. The performance of functional interactions corresponding to the content of the second type of test can be understood as leading bonding wires on the third pad and performing signal interactions.

[0087] It should be noted that the second pad 211 and the third pad 212 can be continuously arranged, that is, there is no partition between the second pad 211 and the third pad 212; or they can be spaced apart, that is, there is a partition between the second pad 211 and the third pad 212.

[0088] Here, when the second pad 211 and the third pad 212 are continuously arranged, damage to the probe card caused by the partition wall can be avoided during the test process if the probe is misaligned, thereby extending the service life of the probe card; at the same time, the generation of impurities is reduced, thereby improving the test efficiency; in addition, the damage to the partition wall caused by the probe card is reduced, thus improving the overall reliability of the packaging structure.

[0089] When a partition wall is provided between the second pad 211 and the third pad 212, the machine's recognition accuracy for each pad can be improved during the test.

[0090] In the following embodiments, the example of a partition wall being provided between the second pad 211 and the third pad 212 is used for illustration. However, it should be understood that the following description of the partition wall is only for illustrating the present invention and is not intended to limit the scope of the present invention.

[0091] To ensure that each probe in the probe card corresponds to a second pad when performing the second type of test, in this embodiment of the disclosure, the center point of each second pad 211 is offset by the same direction and the same distance relative to the center point of the corresponding first pad 205. This ensures that the N first pads and N second pads maintain the same relative position. Thus, after performing the first type of test, the same set of probe cards can be moved a certain distance in a certain direction from the center point of the first pad 205 to align with the center point of all the second pads 211. In other words, the probe card can directly perform the second type of test on all the second pads that need to be tested without replacing the probe card.

[0092] Meanwhile, by setting the positions of the second pad 211 and the third pad 212, which are located at different edge positions, it is possible to ensure that both are close to the edge but do not exceed the edge. The following example illustrates the specific method of setting the positions of the first pad and the second pad.

[0093] In some embodiments, the second pad and the third pad included in each of the N redistribution layers are arranged side by side along a second direction, which is perpendicular to the first direction.

[0094] Here, the first pads 205 are distributed at two oppositely positioned edges of the semiconductor functional structure, for example, referring to... Figure 3 , Figure 3 The left side of the middle arrow shows an example of the arrangement of the first pad 205, which is similar to... Figure 2b The same applies, so I won't go into details here.

[0095] Similarly, the N second pads are divided into two parts, namely a third part and a fourth part; wherein the third part includes M1 second pads; the fourth part includes M2 second pads; the M1 second pads in the third part are arranged side by side along a first direction near the first edge of the semiconductor functional structure; the M2 second pads in the fourth part are arranged side by side along a second direction near the second edge of the semiconductor functional structure. Similarly, the N third pads are divided into two parts, namely a fifth part and a sixth part; wherein the fifth part includes M1 third pads; the sixth part includes M2 third pads; the M1 third pads and M1 second pads in the fifth part are arranged side by side along a second direction near the first edge of the semiconductor functional structure; the M2 third pads and M2 second pads in the sixth part are arranged side by side along a second direction near the second edge of the semiconductor functional structure.

[0096] For example, Figure 3 The right side of the middle arrow shows an example of the arrangement of the redistribution layers 206. Specifically, the six redistribution layers 206 are divided into two parts, each part including three redistribution layers. The three redistribution layers 206 in each part are arranged side by side along the X-axis. Each redistribution layer 206 includes a second pad 211 and a corresponding third pad 212. The second pad 211 and the third pad 212 are arranged side by side along the Y-axis. Figure 3 The dashed line in the diagram shows the straight line where the center point of the first pad 205 is located.

[0097] In some embodiments, the first pad 205, the second pad 211, and the third pad 212 are all elongated strips, and the shape of the orthographic projection of each redistribution layer 206 onto the plane containing the interconnect layer includes an elongated strip shape. The width of each first pad 205 along the first direction may be the same as the width of each second pad 211 and the third pad 212 along the first direction, and the length of each first pad 205 along the second direction may be different from the length of each second pad 211 and the third pad 212 along the second direction.

[0098] In some embodiments, the orthographic projection of the center point of each of the second pads onto the plane of the interconnect layer is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

[0099] For example, refer to Figure 3 At the first edge 20a, the center point O2 of each of the second pads is offset by a first distance H1 relative to the center point O1 of the corresponding first pad along the Y-axis; at the same time, at the second edge 20b, the center point O2 of each of the second pads is offset by a first distance H1 relative to the center point O1 of the corresponding first pad along the Y-axis.

[0100] In some embodiments, a portion of the first end of the first pad near the first edge and a portion of the second end of the redistribution layer near the first edge are substantially flush along a third direction, the third direction being perpendicular to both the first and second directions;

[0101] The third end of another portion of the first pad near the second edge is substantially flush with the fourth end of another portion of the redistribution layer near the second edge along the third direction.

[0102] In some embodiments, the second pad in a portion of the redistribution layer is located near the second end, and the third pad is located away from the second end;

[0103] In another portion of the redistribution layer, the second pad is located near the fourth end, and the third pad is located away from the fourth end.

[0104] In some embodiments, the third pad in a portion of the redistribution layer is located near the second end, and the second pad is located away from the second end; in another portion of the redistribution layer, the third pad is located near the fourth end, and the second pad is located away from the fourth end.

[0105] In other words, provided that the offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal, the second pad can also be set at a distance far from the first pad.

[0106] It is understood that, compared to a partial redistribution layer where the second pad is located near the second end and another partial redistribution layer where the second pad is located near the fourth end, the probe travels a shorter distance during the second test, thus improving testing efficiency and reducing the probability of errors. In some embodiments, each redistribution layer further includes a first region for conductively connecting with the first pad.

[0107] In some redistribution layers, the second pad and the third pad are both located on one side of the first region; in other redistribution layers, the second pad and the third pad are both located on both sides of the first region.

[0108] It should be understood that when the conductive post 207 is provided in the encapsulation structure, reference is made to... Figure 3 , Figure 4The first region 213 contacts the conductive post 207 and is located around the conductive post, serving to achieve electrical connection between the first pad and the redistribution layer. When the conductive post 207 is not provided in the packaging structure, the first region 213 is located within the via 204. The material of the first region 213 can be the same as or different from the material of the redistribution layer 206, or it can be any suitable conductive material.

[0109] In this embodiment of the disclosure, the relative positional relationship between the second and third pads is different, such as... Figure 4 In one portion of the package structure shown, the second pad is located between the conductive post and the third pad. In another portion of the package structure, the conductive post 207 is located between the second pad 211 and the third pad 212. Based on this, the position of the first region 213 can be set between the corresponding second pad 211 and the third pad 212, or it can be set on one side of the corresponding second pad 211 and the third pad 212.

[0110] Additionally, it should be understood that when the conductive post 207 and / or the first region 213 are disposed between the corresponding second pad 211 and the third pad 212, a partition wall may be disposed between the corresponding second pad 211 and the third pad 212.

[0111] It should be noted that, in order to more clearly demonstrate the relative positional relationship between the first, second, and third pads, Figure 4 Only one redistribution layer is shown near the first edge 20a, and one redistribution layer is shown near the second edge 20b; and, Figure 3 , Figure 4 The diagram only schematically shows the redistribution layer near the first edge 20a. The distance between the redistribution layer near the corresponding second edge 20b does not represent the actual distance between the two in actual application. The actual distance can be set according to actual needs.

[0112] In the various embodiments of this disclosure, by setting the positions between the second and third pads located at different edge positions to be different, the same set of probe cards can be used to perform the tests at the two different operating speeds. Compared with using two sets of probe cards for separate testing, this saves testing costs and testing time, and reduces production cycle and manufacturing costs.

[0113] According to another aspect of the present disclosure, a semiconductor device is provided, including: a semiconductor functional structure and a packaging structure as described in the above embodiments of the present disclosure.

[0114] In some embodiments, the semiconductor device further includes: a substrate; a plurality of stacked dies; each die including a semiconductor functional structure and a package structure located on the semiconductor functional structure; each die being electrically connected to the substrate via a lead on a third pad in the package structure.

[0115] According to another aspect of the embodiments of this disclosure, a method for manufacturing an encapsulation structure is provided, such as... Figure 5 As shown, the manufacturing method of the packaging structure provided in this embodiment includes the following steps:

[0116] Step S501: Provide a semiconductor functional structure, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure;

[0117] Step S502: Form an isolation layer with multiple vias, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1;

[0118] Step S503: After completing the first type of test, N redistribution layers are formed on the N first pads and the isolation layer. Each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads. A portion of the first pads are arranged side by side along the first direction near the first edge of the semiconductor functional structure, and another portion of the first pads are arranged side by side along the first direction near the second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0119] Step S504: A first insulating layer is formed that covers and exposes a portion of the redistribution layer, the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad has the same offset direction and offset distance relative to the center point of the corresponding first pad; the relative position between the second pad and the third pad in the partial redistribution layer is different from the relative position between the second pad and the third pad in the other partial redistribution layer; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

[0120] It should be understood that Figure 5 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 5The steps shown can be adjusted in order according to actual needs. Figures 6a to 6d This is a cross-sectional schematic diagram illustrating the fabrication process of a packaging structure provided in an embodiment of this disclosure. The following is in conjunction with... Figure 5 , Figures 6a to 6d The method for manufacturing the packaging structure provided in the embodiments of this disclosure will be described in detail.

[0121] In step S501, refer to Figure 6a A semiconductor functional structure 600 is provided, the semiconductor functional structure 600 including a semiconductor functional layer 601 and an interconnect layer 602. Providing the semiconductor functional structure 600 includes: providing a substrate (…). Figure 6a (Not shown in the image), a semiconductor functional layer 601 is formed on the substrate, and an interconnect layer 602 is formed on the semiconductor functional layer.

[0122] Specifically, the semiconductor functional layer 601 comprises a single or multiple thin films, and has a conductive layer and / or a dielectric layer. Depending on actual needs, various functional structures can be disposed in the semiconductor functional layer 601. Correspondingly, the interconnect layer 602 is used to extract the electrical signals of the functional structures in the semiconductor functional layer 601 to operate the functional structures. In some embodiments, the interconnect layer 602 includes a top metal layer, which not only extracts the electrical signals of the functional structures but also supports the semiconductor functional structure 600.

[0123] In some embodiments, the method further includes: removing a portion of the interconnect layer 602 to reduce the area of ​​the interconnect layer, thereby reducing the parasitic capacitance generated by the interconnect layer. Figure 6a The image shown is a cross-sectional view of a section of interconnect layer 602 after a portion has been removed. In practical applications, the parts of the interconnect layer are not cut off but interconnected. That is, the parts of the interconnect layer may be continuous on other sections.

[0124] In step S502, refer to Figure 6b An isolation layer 603 is formed on the interconnect layer 602. The composition of the isolation layer includes, but is not limited to, tetraethyl orthosilicate.

[0125] Next, a portion of the isolation layer is removed to form a plurality of vias 604. Each via exposes a portion of the interconnect layer, and each exposed portion of the interconnect layer serves as a first pad 605, forming N first pads 605. The via 604 can be cylindrical, inverted trapezoidal, or any suitable shape. The cross-sectional area of ​​the via includes the area of ​​its orthographic projection onto the plane of the interconnect layer. For example, if the via is an inverted trapezoid, then the cross-sectional area of ​​the first pad is the minimum cross-sectional area of ​​the via.

[0126] The first pad 605 can be used to perform a first type of test; it can also be used to perform functional interactions corresponding to the content of the first type of test, such as leading out bond lines and performing signal interactions. The first type of test can be understood as performing some tests on the semiconductor functional structure at a lower operating speed. It should be noted that, in memory, the operating speed refers to the read and write speed of the memory.

[0127] In step S503, refer to Figure 6c A redistribution layer 606 is formed in the isolation layer 603 and the via 604.

[0128] The specific method for forming the redistribution layer 606 on the isolation layer 603 includes: forming a new conductor pattern on the isolation layer by exposure and development, and then forming the redistribution layer according to the new conductor pattern using electroplating technology. The redistribution layer includes new conductor paths, which are electrically connected to the interconnect layer.

[0129] Here, each wiring layer 606 covers the isolation layer 603 and is electrically connected to a corresponding first pad 605 among the N first pads; it should be noted that the first pad 605 includes a first part of the first pad and a second part of the first pad. The first part of the first pad is arranged side by side along a first direction near the first edge of the semiconductor functional structure, and the second part of the first pad is arranged side by side along the first direction near the second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0130] In step S504, refer to Figure 6d A first insulating layer 608 is formed on the redistribution layer 606.

[0131] Next, a portion of the first insulating layer 608 is removed, exposing a portion of the redistribution layer 606. The exposed portion of the redistribution layer includes a second pad 611 and a third pad 612. The second pad 612 is used for performing a second type of test, and the third pad is used to perform functional interactions corresponding to the content of the second type of test. The second type of test can be understood as some tests performed on the semiconductor functional structure at high operating speeds. The positions of the second pad 611 and the third pad 612 can be selected and set according to actual needs.

[0132] It should be noted that, in this embodiment, reference is used. Figure 6dIn addition to exposing a portion of the redistribution layer to form the second and third pads, the first insulating layer also exposes the redistribution layer above the first pad to fill the subsequent second insulating layer 610 within the groove 609 formed by the redistribution layer. In this case, the density of the second insulating layer may be less than or equal to that of the first insulating layer. In other embodiments, the first insulating layer also covers the bottom surface and sidewalls of the groove 609 formed by the redistribution layer, and the subsequent second insulating layer 610 is formed within the groove 609 formed by the first insulating layer.

[0133] In other embodiments, the packaging structure further includes conductive pillars, and correspondingly, the method further includes: forming conductive pillars on the first pad after completing the first type of test; the step of forming a redistribution layer on the first pad and the isolation layer includes: forming a redistribution layer on the conductive pillars and the isolation layer, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillars.

[0134] In this embodiment of the disclosure, the relative positional relationship between the second pad and the third pad can be set according to actual needs. For example, in the encapsulation structure, the second pad is located between the conductive post and the third pad, and / or, in the encapsulation structure, the conductive post is located between the second pad 611 and the third pad 612. Based on this, the relative position between the second pad 611 and the third pad 612 in a portion of the redistribution layer 606 can be the same as or different from the relative position between the second pad 611 and the third pad 612 in another portion of the redistribution layer 606, as previously mentioned, and will not be repeated here.

[0135] The offset direction and offset distance of the center point of each second pad relative to the center point of the corresponding first pad are equal. In this way, after performing the first type of test, the same set of probe cards can be aligned with the center points of all the second pads after moving a certain distance in a certain direction from the center point of the first pad. That is, the probe card can directly perform the second type of test on all the second pads without replacing the probe card.

[0136] Additionally, it should be noted that in the above embodiments of this disclosure, a packaging structure compatible with two types of testing is adopted to meet the requirement that the semiconductor functional structure can be tested in different types of processes at different stages. However, it should be noted that when designing the layout of the packaging structure, via positions for the redistribution layer need to be reserved on the top metal layer to ensure that when a redistribution layer needs to be added, the top metal layer or any other photomask and process should not be modified.

[0137] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0138] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0139] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0140] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure, characterized in that, include: An isolation layer having multiple vias covers the surface of an interconnect layer, the vias exposing portions of the interconnect layer, the interconnect layer being disposed on the surface of a semiconductor functional structure; N first pads, each first pad consisting of an interconnect layer exposed by one of the vias; where N is a positive integer greater than 1; N redistribution layers, each redistribution layer covering the isolation layer and electrically connected to a corresponding first pad among the N first pads; a portion of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, wherein the first edge and the second edge are two opposite edges of the semiconductor functional structure. A first insulating layer covers and exposes a portion of each of the redistribution layers; Each exposed portion of the redistribution layer includes a second pad and a third pad; wherein the center point of each second pad is offset from the center point of the corresponding first pad in both direction and distance; the relative positions between the second pad and the third pad in some redistribution layers are different from those in other redistribution layers; the first pad and the second pad are used for testing the semiconductor functional structure at different operating speeds, and the third pad is used to perform functional interactions corresponding to the content tested by the second pad; wherein the redistribution layer and the second pad are formed after the first operating speed test is performed using the first pad.

2. The packaging structure according to claim 1, characterized in that, In each of the N rewiring layers, the second pad and the third pad are arranged side by side along a second direction, which is perpendicular to the first direction.

3. The packaging structure according to claim 2, characterized in that, The orthographic projection of the center point of each of the second pads onto the plane of the interconnect layer is offset by a first distance in the second direction relative to the center point of the corresponding first pad.

4. The packaging structure according to claim 3, characterized in that, The shape of the orthographic projection of each of the redistribution layers onto the plane where the interconnect layer is located includes an elongated strip shape.

5. The packaging structure according to claim 4, characterized in that, The first end of a portion of the first pad near the first edge and the second end of a portion of the redistribution layer near the first edge are substantially flush along a third direction, and the third direction is perpendicular to both the first direction and the second direction. The third end of another portion of the first pad near the second edge is substantially flush with the fourth end of another portion of the redistribution layer near the second edge along the third direction.

6. The packaging structure according to claim 5, characterized in that, In part of the redistribution layer, the second pad is located near the second end, and the third pad is located away from the second end; In another portion of the redistribution layer, the second pad is located near the fourth end, and the third pad is located away from the fourth end.

7. The packaging structure according to claim 6, characterized in that, Each of the redistribution layers further includes a first region for making a conductive connection with the first pad; In some redistribution layers, the second pad and the third pad are both located on one side of the first region; in other redistribution layers, the second pad and the third pad are both located on both sides of the first region.

8. The packaging structure according to claim 1, characterized in that, The redistribution layer is in direct contact with the corresponding first pad; or, The packaging structure further includes a conductive pillar located between the redistribution layer and the corresponding first pad, wherein the redistribution layer is electrically connected to the interconnect layer through the conductive pillar.

9. The packaging structure according to claim 8, characterized in that, The encapsulation structure includes the conductive pillars, and the number of conductive pillars is multiple, with the multiple conductive pillars arranged side by side along a first direction.

10. The packaging structure according to claim 8, characterized in that, The redistribution layer is in direct contact with the corresponding first pad, and the packaging structure further includes: A second insulating layer is located within the groove formed by each of the redistribution layers, and the hardness of the material of the second insulating layer is less than that of the material of the redistribution layer.

11. A semiconductor device, characterized in that, include: Semiconductor functional structure and packaging structure as described in any one of claims 1 to 10.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: substrate; Multiple stacked dies; each die includes a semiconductor functional structure and a packaging structure located on the semiconductor functional structure; Each die is electrically connected to the substrate via a lead on the third pad in the package structure.

13. A method for manufacturing an encapsulation structure, characterized in that, include: A semiconductor functional structure is provided, wherein an interconnect layer is disposed on the surface of the semiconductor functional structure; An isolation layer with multiple vias is formed, the isolation layer covering the surface of the interconnect layer, the vias exposing a portion of the interconnect layer, each of the exposed portions of the interconnect layer serving as a first pad, forming N first pads; the first pads are used for performing a first type of test; N is a positive integer greater than 1; After completing the first type of test, N redistribution layers are formed on the N first pads and the isolation layer. Each redistribution layer covers the isolation layer and is electrically connected to a corresponding first pad among the N first pads. A portion of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and another portion of the first pads are arranged side by side along a first direction near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure. A first insulating layer is formed to cover and expose a portion of the redistribution layer, with the exposed portion of the redistribution layer serving as a second pad and a third pad; wherein the center point of each second pad is offset in both direction and distance relative to the center point of the corresponding first pad; the relative positions between the second pad and the third pad in a portion of the redistribution layer are different from the relative positions between the second pad and the third pad in another portion of the redistribution layer; the second pad is used for performing a second type of test, and the third pad is used for performing a functional interaction corresponding to the content of the second type of test; the semiconductor functional structure operates at a lower speed when performing the first type of test than when performing the second type of test.

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