Packaging structures and their fabrication methods, semiconductor devices

Abstract

This disclosure provides a packaging structure and its fabrication method, as well as a semiconductor device. The packaging structure includes: a redistribution layer electrically connected to an interconnect layer of a semiconductor functional structure; an insulating layer covering and exposing a portion of the redistribution layer; the exposed portion of the redistribution layer includes at least one first pad; wherein the first pad includes a first region and a second region continuously disposed thereon; the first region is used for testing; and the second region is used for performing functional interactions corresponding to the content of the test.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to packaging structures and their fabrication methods, and semiconductor devices. Background Technology

[0002] With the rapid increase in the penetration rate of electronic devices and the booming development of the electronic device market, there is an increasing demand for electronic products to evolve towards miniaturization and thinning while possessing high performance, multifunctionality, high reliability, and convenience. This demand places higher requirements on semiconductor device packaging, demanding better, lighter, thinner packaging, higher packaging density, better electrical and thermal performance, higher reliability, and higher cost-effectiveness.

[0003] To ensure that the performance of semiconductor devices meets the corresponding requirements, ports for testing and performing functional interactions need to be fabricated on the package structure. Summary of the Invention

[0004] In view of this, in order to solve one or more of the related technical problems, embodiments of this disclosure provide a packaging structure and a method for manufacturing the same, as well as a semiconductor device.

[0005] According to an embodiment of this disclosure, a packaging structure is provided, including:

[0006] A redistribution layer, which is electrically connected to the interconnect layer of the semiconductor functional structure;

[0007] An insulating layer that covers and exposes a portion of the redistribution layer;

[0008] The exposed portion of the redistribution layer includes at least one first pad; wherein the first pad includes a first region and a second region that are consecutively disposed; the first region is used for testing; and the second region is used for performing functional interactions corresponding to the content of the test.

[0009] In the above scheme, the packaging structure further includes: a plurality of second pads, which are formed by the portion of the redistribution layer exposed by the insulating layer, for testing or for performing functional interactions corresponding to the content of the test;

[0010] In this configuration, at least a portion of the second pads are arranged side-by-side with the at least one first pad along a first direction, the first direction being perpendicular to the direction from the first region to the second region; and the area of ​​each first pad is greater than the area of ​​each second pad.

[0011] In the above scheme, both the first pad and the second pad are elongated strips; the width of the first pad along the first direction is the same as the width of the second pad along the first direction; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush.

[0012] In the above scheme, the number of the first pads includes a plurality of first pads, at least a portion of the first pads are arranged side by side along the first direction at a position close to the first edge of the semiconductor functional structure; at least a portion of the second pads are arranged side by side along the first direction on both sides of the plurality of first pads.

[0013] In the above scheme, at least two second pads are included on each side of the plurality of first pads.

[0014] In the above scheme, a first number of second pads are provided on the first side of the plurality of first pads, and a second number of second pads are provided on the second side of the plurality of first pads, wherein the first number and the second number are different.

[0015] In the above scheme, a portion of the second pads are arranged side by side along the first direction on both sides of the plurality of first pads, and another portion of the second pads are arranged side by side along the second direction at a position close to the second edge of the semiconductor functional structure; the second direction is perpendicular to the first direction; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0016] In the above scheme, the number of first pads includes multiple first pads, a portion of which are arranged side by side along the first direction near the first edge of the semiconductor functional structure, and another portion of which are arranged side by side along the first direction near the second edge of the semiconductor functional structure; a portion of second pads are arranged side by side along the first direction on both sides of a portion of the first pads, and another portion of second pads are arranged side by side along the first direction on both sides of another portion of the first pads; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0017] In the above scheme, the arrangement of the first pad and the second pad located near the first edge of the semiconductor functional structure is symmetrical with the arrangement of the first pad and the second pad located near the second edge of the semiconductor functional structure.

[0018] In the above scheme, all the pads arranged side by side along the first direction are flush with one end near the edge of the semiconductor functional structure;

[0019] The first region is located at one end of the first pad near the edge of the semiconductor functional structure, and the second region is located at one end of the first pad away from the edge of the semiconductor functional structure.

[0020] According to an embodiment of this disclosure, a semiconductor device is further provided, including: a semiconductor functional structure and a packaging structure as described in any one of the above embodiments of this disclosure.

[0021] According to embodiments of this disclosure, a method for manufacturing an encapsulation structure is also provided, the method comprising:

[0022] A redistribution layer is formed on a semiconductor functional structure, and the redistribution layer is electrically connected to an interconnect layer on the semiconductor functional structure.

[0023] An insulating layer is formed on the surface of the redistribution layer;

[0024] A portion of the insulating layer is removed to expose a portion of the redistribution layer, forming at least one first pad; each of the first pads is formed by the portion of the redistribution layer exposed from the insulating layer.

[0025] The first pad includes a first area and a second area that are continuously arranged; the first area is used for testing, and the second area is used for performing functional interactions corresponding to the content of the test.

[0026] In various embodiments of this disclosure, at least one first pad is provided on the semiconductor functional structure. Each first pad includes a first region for performing tests and a second region for performing functional interactions corresponding to the test content. The first region and the second region are continuously arranged; in other words, no partition is provided between the first region and the second region. Thus, while ensuring that the region for testing and the region for performing functional interactions corresponding to the test content are physically distinct, damage to the probe card caused by the partition can be avoided during testing if the probe is misaligned, thereby extending the lifespan of the probe card. Simultaneously, the generation of impurities is reduced, thereby improving testing efficiency. Furthermore, the reduction of probe card damage to the partition improves the overall reliability of the packaging structure. Attached Figure Description

[0027] Figure 1 This is a cross-sectional view of a packaging structure provided in an embodiment of the present disclosure;

[0028] Figure 2a This is a cross-sectional view of another packaging structure provided in an embodiment of this disclosure;

[0029] Figure 2b This is a cross-sectional schematic diagram of another packaging structure provided in the embodiments of this disclosure;

[0030] Figures 3a-3e A schematic diagram illustrating the relative positional relationship between several first and second gaskets provided in embodiments of this disclosure;

[0031] Figure 4 This is a schematic flowchart of the manufacturing method of the packaging structure provided in the embodiments of this disclosure;

[0032] Figures 5a-5c This is a cross-sectional schematic diagram of the manufacturing process of a packaging structure provided in an embodiment of this disclosure.

[0033] Explanation of reference numerals in the attached figures

[0034] 101-Semiconductor functional structure; 102-Isolation layer; 103-Redistribution layer; 104-Insulating layer; 105-First type pad; 106-Second type pad; 107-Partition; 200-Semiconductor functional structure; 201-Semiconductor functional layer; 202-Interconnect layer; 203-Isolation layer; 204-Via; 205-Redistribution layer; 206-Groove; 207-Insulating layer; 208-First pad; 2081-Second type pad 2082 - First region of the first pad; 209 - Second pad; 500 - Semiconductor functional structure; 501 - Semiconductor functional layer; 502 - Interconnect layer; 503 - Isolation layer; 504 - Via; 505 - Redistribution layer; 506 - Groove; 507 - Insulating layer; 508 - First pad; 5081 - First region of the first pad; 5082 - Second region of the first pad; 509 - Second pad.

[0035] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0037] The embodiments of this disclosure are described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of this disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this disclosure.

[0038] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0039] In this embodiment of the disclosure, the term "A and B connected" includes the case where A and B are in direct contact, or the case where A and B are in indirect contact through an intermediate conductive structure.

[0040] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0041] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend onto a lower or upper surface of a structure, and its area may be less than or equal to the area of ​​the extending surface.

[0042] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0043] The semiconductor functional structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include memory.

[0044] In the design of packaging structures for semiconductor devices such as Dynamic Random Access Memory (DRAM), one design method for pads (also known as solder pads) is to create windows in the redistribution layer (RDL).

[0045] The redistribution layer windowing refers to forming a redistribution layer on the top metal layer of a semiconductor functional structure, forming a passivation layer or an insulating layer on the redistribution layer, and then forming a window area on the passivation layer or insulating layer to expose part of the redistribution layer, forming two types of pads arranged side by side. Here, the redistribution layer in the semiconductor device can serve to adjust the position of the pads and also to enhance the power supply network of the power supply and ground.

[0046] In the windowing method of the redistribution layer, two types of pads are typically used: a first-type pad and a second-type pad. The first-type pad is used for probe pin insertion testing, and the second-type pad is used for bringing out the bonding wire. Due to physical isolation requirements, and considering the limited recognition area of ​​the equipment for the first and second-type pads, a partition is usually placed between the side-by-side first-type and second-type pads, such as... Figure 1 As shown.

[0047] For example, refer to Figure 1 An isolation layer 102, a redistribution layer 103 covering the isolation layer 102, and an insulating layer 104 covering the redistribution layer 103 are stacked sequentially on the semiconductor functional structure 101. When a portion of the insulating layer 104 is removed, a portion of the redistribution layer 103 is exposed. The exposed portion of the redistribution layer 103 includes a first type of pad 105 and a second type of pad 106. A partition wall 107 is provided between the first type of pad 105 and the second type of pad 106.

[0048] However, during the alignment of the probe card and the first type of pad, if the center point of the probe card and the first type of pad is misaligned, the probe card pin may directly hit the sidewall. A high sidewall increases the probability of probe card damage; simultaneously, the sidewall also makes it easier for impurities (such as dielectric material) to adhere to the pin, thus affecting the test results; furthermore, after the probe card damages the partition wall, the performance of the second type of pad 106 may also be affected, thereby impacting the operation of the semiconductor functional structure.

[0049] In view of this, to solve one or more of the above problems, embodiments of this disclosure provide a packaging structure and a method for manufacturing the same, and a semiconductor device, wherein the packaging structure includes: a redistribution layer electrically connected to an interconnect layer of a semiconductor functional structure; an insulating layer covering and exposing a portion of the redistribution layer; the exposed portion of the redistribution layer includes at least one first pad; wherein the first pad includes a first region and a second region continuously disposed thereon; the first region is used for testing; and the second region is used for performing a functional interaction corresponding to the content of the test.

[0050] Specifically, refer to Figure 2a The packaging structure includes:

[0051] substrate ( Figure 2a (Not shown in the image), the constituent materials of the substrate may include silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI).

[0052] A semiconductor functional structure 200 is located above a substrate. Specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and an interconnect layer 202 located on the semiconductor functional layer 201. Various functional structures can be disposed in the semiconductor functional layer 201 according to actual needs. Correspondingly, the interconnect layer 202 is used to extract electrical signals from the functional structures in the semiconductor functional layer 201 to operate the functional structures. In some embodiments, the interconnect layer 202 includes a top metal layer, which not only extracts the electrical signals from the functional structures but also supports the semiconductor functional structure 200.

[0053] An isolation layer 203 covers the surface of the interconnect layer 202 and is used to isolate the interconnect layer 202 and the subsequently formed redistribution layer 205 in a partial area. A via 204 is provided in the isolation layer 203, exposing a portion of the interconnect layer 202. The via 204 can be cylindrical, inverted trapezoidal, or any suitable shape. The constituent materials of the isolation layer 203 include, but are not limited to, tetraethyl orthosilicate (TEOS).

[0054] A redistribution layer 205 covers the surface of the isolation layer 203 and the sidewalls and bottom of the via 204. A portion of the redistribution layer 205 is connected to the exposed portion of the interconnect layer 202, serving to extract electrical signals from the interconnect layer 202. The redistribution layer 205 is composed of materials including, but not limited to, metals; preferably, the material of the redistribution layer is aluminum (Al).

[0055] It should be noted that the thickness of the redistribution layer 205 on the exposed portion of the interconnect layer 202 can be the same as the thickness of the redistribution layer 205 on the surface of the isolation layer 203. In some embodiments, the diameter of the via 204 is greater than twice the thickness of the redistribution layer 205. In this case, the redistribution layer 205 covers the sidewalls and bottom of the via 204, and the redistribution layer 205 forms a groove 206. An insulating layer 207 covers the surface of the redistribution layer 205, which serves to isolate the electrical connection between the redistribution layer 205 and other conductive materials, and also protects the redistribution layer 205 from damage. The material of the insulating layer 207 includes, but is not limited to, polyimide (PI).

[0056] Here, the insulating layer 207 also fills the groove 206.

[0057] In some embodiments, the hardness of the material of the insulating layer 207 is less than the hardness of the material of the redistribution layer 205, thereby reducing the stress on the packaging structure and increasing the reliability of the packaging structure.

[0058] Here, a portion of the insulating layer 207 is removed, exposing a portion of the redistribution layer 205, which includes a first pad 208. The first pad 208 includes a continuously disposed first region 2081 and a second region 2082. The first region 2081 is used for testing; the second region 2082 is used to perform functional interactions corresponding to the test content. In some specific embodiments, the first region 2081 is used for probe testing; the second region 2082 is used to bring out bonding wires.

[0059] refer to Figure 2a The first region 2081 and the second region 2082 are continuously arranged, meaning there is no partition between them. Thus, compared to related technologies, the reference... Figure 1 By providing a partition wall 107 between the first type of pad 105 and the second type of pad 106, this embodiment of the present disclosure can, under the premise of ensuring that the area used for testing and the area used for performing functional interactions corresponding to the test content are physically separated, avoid damage to the probe card caused by the partition wall when the probe is misaligned during testing, thereby extending the service life of the probe card; at the same time, it reduces the generation of impurities, which is beneficial to improving test accuracy; in addition, it reduces the damage to the partition wall by the probe card, thereby improving the overall reliability of the packaging structure.

[0060] It should be noted that the first type of pad 105 in the related technology corresponds to the first region 2081 in the embodiment of this disclosure, and their functions and areas can be the same; the second type of pad 106 corresponds to the second region 2082 in the embodiment of this disclosure, and their functions and areas can be the same. Here, the area of ​​the first region 2081 and the area of ​​the second region 2082 can be the same or different. Preferably, the area of ​​the first region 2081 and the area of ​​the second region 2082 are the same.

[0061] It should be noted that in some other embodiments, there may be a possibility of supporting probe card pin piercing testing on the same windowed area before wire bonding encapsulation at the packaging plant, without affecting the yield of the wire bonding package. In other words, the exposed portion of the redistribution layer may also include only the second pad. The second pad can be used for both probe testing and wire bonding.

[0062] In some specific embodiments, reference is made to Figure 2bThe packaging structure further includes: a plurality of second pads 209, which are formed by the exposed portion of the redistribution layer 205 of the insulating layer, for testing or for performing functional interactions corresponding to the content of the test; wherein, at least a portion of the plurality of second pads 209 are arranged side by side with the at least one first pad 208 along a first direction, the first direction being perpendicular to the direction from the first region to the second region; the area of ​​each first pad is larger than the area of ​​each second pad.

[0063] Here, the first direction can be the X-axis direction or the Y-axis direction; the second direction can be the Y-axis direction or the X-axis direction; it should be noted that when the first direction is the X-axis direction, the second direction is the Y-axis direction; and when the first direction is the Y-axis direction, the second direction is the X-axis direction. For ease of understanding, this embodiment of the disclosure uses the example of the first direction being the X-axis direction and the second direction being the Y-axis direction for explanation.

[0064] In practical applications, multiple second gaskets 209 and at least one first gasket 208 can be formed in the same process.

[0065] In this embodiment, in order to ensure the quality of testing and wire bonding, the partition between the first type of pad and the second type of pad in the related technology is removed, so that the area of ​​the first pad 208 is greater than or equal to the sum of the areas of the first type of pad and the second type of pad. In the related technology, the area of ​​the first type of pad and the second type of pad is the maximum area that the machine can locate by recognizing its edges. This means that the machine may not be able to accurately locate the first pad 208 by recognizing its edges.

[0066] For example, in related technologies, both testing and wire bonding require high-precision positioning. When the probe identifies the pad, the range of the identification pattern is limited. The identification range of the testing machine is: within a range of 50um from the center point, it is necessary to find the four edges of the window, that is, the edge of the pad. However, in the embodiment of this disclosure, the first pad can be long and narrow, and at least one side of the length is more likely to exceed the above identification range because it is superimposed with the lengths of the two pads (the first type of pad and the second type of pad) in the related technologies. This makes it impossible for the testing machine to find the edge of the first pad within the existing identification accuracy range, thus causing the positioning of the first pad to fail.

[0067] In order to accurately locate the specific position of the first pad 208 within the existing recognition accuracy range, in some embodiments of this disclosure, the encapsulation structure includes at least one first pad and a plurality of second pads. By reasonably arranging the positions of the first pad and the plurality of second pads, both areas of the first pad can be successfully located.

[0068] In some embodiments, both the first pad and the second pad are elongated strips; the width of the first pad along the first direction is the same as the width of the second pad along the first direction; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush.

[0069] Here, the elongated shape includes a general rectangle (with different lengths and widths) and a square (with the same length and width). In some embodiments, each of the first pads 208 and each of the second pads 209 is a general rectangle; in other embodiments, each of the second pads 209 is a square, and each of the first pads 208 is a general rectangle.

[0070] Here, the width of each first pad 208 along the first direction is the same as the width of each second pad 209 along the first direction; the length of each first pad 208 along the second direction is greater than the length of each second pad 209 along the second direction.

[0071] In the above embodiments, the equal spacing between two adjacent pads can be understood as: the spacing between two adjacent first pads, the spacing between an adjacent first pad and a second pad, and the spacing between two adjacent second pads are all equal. The fact that one end of all pads arranged side-by-side along the first direction is flush can be understood as: one end of all first pads and all second pads arranged side-by-side along the first direction is flush. For example, the ends of all first pads and all second pads arranged side-by-side along the first direction that are flush near the edge of the semiconductor functional structure are flush.

[0072] In some embodiments, the number of first pads includes a plurality of first pads, at least a portion of which are arranged side by side along a first direction near a first edge of the semiconductor functional structure; at least a portion of which are second pads are arranged side by side along the first direction on both sides of the plurality of first pads.

[0073] Here, for reference Figure 3a The number of first pads 208 may include multiple first substrates, which are disposed at the middle position near the first edge of the semiconductor functional structure; the number of second pads 209 may include multiple second pads, which are respectively disposed on both sides of the multiple first pads 208.

[0074] Here, the identification of the two regions in the first pad 208 can be aided by the second pads 209 located on both sides. Specifically:

[0075] As previously mentioned, the area of ​​the second pad 209 is similar to that of the first or second type of pad in the related technology. The second pad 209 is within the recognition range of the testing machine, which can accurately identify the position (four edges) of each second pad 209. Given that the first pad 208 and the second pad 209 are both elongated strips with the same width, one end flush, and the spacing between adjacent pads is equal, the predicted position of the region (first region or second region) near the alignment end in each first pad 208 can be obtained by using the positions of the second pads 209 on both sides as a reference. Since the width direction (i.e., the first direction) of the first pad 208 is within the recognition range of the testing machine, the region near the alignment end in each first pad 208 can be accurately identified by combining the width direction recognition. After accurately identifying a region of the first pad 208, the center point of the first region can be obtained. Considering that the two regions of the first pad are set continuously, share a long side, and the length of the long side of the first pad is constant, the center point of the first region is moved a fixed distance in a second direction perpendicular to the first direction. This can be considered as the center point of another region of the first pad 208 that is far from the alignment end, thereby further identifying another region of the first pad 208 that is far from the alignment end.

[0076] In some embodiments, the ends of all the pads arranged side-by-side along a first direction are flush with the edge of the semiconductor functional structure; the first region is located at the end of the first pad closest to the edge of the semiconductor functional structure, and the second region is located at the end of the first pad furthest from the edge of the semiconductor functional structure. That is, the first region 2081 of the first pad can be identified first using the second pads 209 located on both sides, and then the second region 2082 can be identified using the first region 2081.

[0077] It should be noted that when using the edges of the semiconductor functional structure to describe the positional relationship of different regions in the first pad or the positional relationship of the first pad and the second pad, the edge refers to the edge of the first pad that is closer to the first pad among the multiple edges of the semiconductor functional structure, and more specifically, the edge of the first pad that is closer to the first pad among two opposite edges in the second direction; correspondingly, when using the edges of the semiconductor functional structure to describe the positional relationship of different regions in the second pad or the positional relationship of the first pad and the second pad, the edge refers to the edge of the second pad that is closer to the second pad among the multiple edges of the semiconductor functional structure.

[0078] It is understandable that the process of leading the bonding wires out of the first pad 208 is relatively flexible in terms of controllability or adjustability, while the process of aligning the first pad 208 with the probe card is relatively difficult. Therefore, setting the first region 2081 on the side closer to the edge of the semiconductor functional structure at both ends of the first pad 208 helps to reduce the difficulty of aligning the first region 2081 with the probe card and provides a higher fault tolerance for the probe card during the testing process.

[0079] In other embodiments, the ends of all the pads arranged side-by-side along a first direction that are furthest from the edge of the semiconductor functional structure are flush, the second region is located at the end of the first pad closest to the edge of the semiconductor functional structure, and the first region is located at the end of the first pad furthest from the edge of the semiconductor functional structure. In this case, the first region 2081 of the first pad can also be identified first by relying on the second pads 209 located on both sides, and then the second region 2082 can be identified using the first region 2081.

[0080] Here, the second region 2082 is located at one end of the first pad 208 that is closer to the edge of the semiconductor functional structure. This helps to shorten the length of the bonding wires soldered on the second region 2082 and increase the bonding process window.

[0081] In some embodiments, at least two second pads are included on each side of the plurality of first pads.

[0082] Here, the plurality of first pads 208 have a first side and a second side; wherein, the first side and the second side of the first pad 208 are opposite sides. The direction from the first side to the second side is parallel to the X-axis direction.

[0083] For example, refer to Figure 3a The number of first pads 208 includes 6, and the number of second pads 209 includes 10; the 6 first pads 208 and the 10 second pads 209 are arranged side by side along the X-axis direction at a position close to the first edge 20a of the semiconductor functional structure 200; and the 10 second pads 209 are respectively arranged on the first side and the second side of the 6 first pads 208.

[0084] It should be noted that the number of second pads 209 located on both sides of the first pad 208 can be one or more. Having one second pad 209 on each side of the first pad 208 is sufficient to assist in identifying the first and second regions within the first pad 208. However, in actual manufacturing processes, the second pads 209 located at the edges on the sides furthest from the first pad 208 are easily damaged, for example, by cutting or abrasion. Therefore, two or more second pads 209 are provided on both sides of the first pad 208; this ensures that even if one second pad 209 at the edge is damaged, the remaining undamaged second pads can still be used to accurately position the first pad.

[0085] Here, a first number of second pads are provided on the first side of the plurality of first pads 208, and a second number of second pads are provided on the second side of the plurality of first pads. The first number and the second number may be the same or different. Figure 3a The diagram shows the case where the first quantity is the same as the second quantity. Figure 3b The diagram illustrates a case where the first quantity and the second quantity are different. Furthermore, it should be noted that when the first quantity and the second quantity are different, the first pad can also be located in the middle region of the first direction, that is, the distance between the leftmost of the plurality of first pads and the left edge of the semiconductor functional structure is equal to the distance between the rightmost of the plurality of first pads and the right edge of the semiconductor functional structure.

[0086] In other embodiments, a portion of the second pads are arranged side-by-side on both sides of the plurality of first pads along a first direction, and another portion of the plurality of second pads are arranged side-by-side along a second direction near the second edge of the semiconductor functional structure; the second direction is perpendicular to the first direction; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0087] For example, refer to Figure 3c The semiconductor functional structure 200 is provided with eight first pads 208 and twelve second pads 209. Eight first pads 208 are located near the first edge 20a of the semiconductor functional structure, and four second pads 209 are located on each side of the eight first pads 208 (a total of eight second pads). Four second pads are located near the second edge 20b of the semiconductor functional structure, and these four second pads are arranged side-by-side along the Y-axis.

[0088] As can be seen, compared to the previous embodiment, Figure 3c exist Figure 3aBased on this, multiple second pads 209 are added, arranged along the second direction (along the Y-axis direction), near the second edge 20b of the semiconductor functional structure.

[0089] It is understandable that the area of ​​the multiple second pads 209 arranged side by side along the Y-axis is within the recognition range of the testing equipment. The testing equipment can accurately identify the position (four edges) of each second pad 209. Based on this, the multiple second pads 209 arranged side by side along the Y-axis can be used to obtain a precise second direction. Thus, when the first area is moved a fixed distance in the second direction to identify the second area, a more precise movement in the second direction can be achieved, thereby achieving a more precise positioning of the second area.

[0090] It should be noted that, Figure 3c The plurality of second pads 209 arranged along the second direction shown in the figure are rotated 90 degrees clockwise compared to the plurality of second pads 209 arranged along the first direction. However, in other embodiments, the plurality of second pads 209 arranged along the second direction may also be arranged in the same orientation as the plurality of second pads 209 arranged along the first direction without rotating 90 degrees. It is understood that rotating 90 degrees is more conducive to saving the area of ​​the pads.

[0091] In some embodiments, the number of the first pads includes a plurality of first pads, a portion of which are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and another portion of which are arranged side by side along a first direction near a second edge of the semiconductor functional structure; a portion of the second pads are arranged side by side along the first direction on both sides of a portion of the first pads, and another portion of the second pads are arranged side by side along the first direction on both sides of another portion of the first pads; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

[0092] For example, refer to Figure 3d The semiconductor functional structure 200 is provided with 20 first pads 208 and 12 second pads 209; wherein, 10 first pads 208 are provided near the first edge 20a of the semiconductor functional structure, and 3 second pads 209 are provided on each side of the 10 first pads 208 (a total of 6 second pads). Similarly, 10 first pads 208 are provided near the second edge 20b of the semiconductor functional structure, and 3 second pads 209 are provided on each side of the 10 first pads 208 (a total of 6 second pads).

[0093] In some embodiments, the arrangement of the first and second pads located near the first edge of the semiconductor functional structure is symmetrical to the arrangement of the first and second pads located near the second edge of the semiconductor functional structure. Here, symmetry can be understood as the pads located at the first edge being mirror images of the pads located at the second edge along a first direction.

[0094] For example, refer to Figure 3d Ten first pads 208 and six second pads 209 are arranged side-by-side along the X-axis near the first edge 20a of the semiconductor functional structure; ten first pads 208 and six second pads 209 are arranged side-by-side along the X-axis near the second edge 20b of the semiconductor functional structure. Here, setting all the pads at the first edge 20a and all the pads at the second edge 20b as a symmetrical structure can save process steps and improve production efficiency.

[0095] When the pads at the first edge position and the pads at the second edge position are symmetrically arranged, the first region and the second region of the corresponding first pad 208 can be identified from the first edge and the second edge respectively. If the line connecting the two first regions identified by the two first pads corresponding to the first edge and the second edge is parallel to the second direction, it further shows that the identification on both sides is accurate.

[0096] In other embodiments, the arrangement of the first and second pads located near the first edge of the semiconductor functional structure is asymmetrical with respect to the arrangement of the first and second pads located near the second edge of the semiconductor functional structure. Here, asymmetry can be understood as the pads located at the first edge not being mirror images of the pads located at the second edge along a first direction.

[0097] For example, refer to Figure 3e All pads at the first edge 20a and all pads at the second edge 20b are configured as an asymmetrical structure. Specifically, 10 first pads are provided near the first edge 20a of the semiconductor functional structure, and 3 second pads 209 are provided on each of the first and second sides of the 10 first pads; 10 first pads are provided near the second edge 20b of the semiconductor functional structure, and 4 second pads 209 are provided on the first side of the 10 first pads, and 2 second pads 209 are provided on the second side. Thus, all pads located at the first edge 20a and all pads located at the second edge 20b are configured as an asymmetrical structure.

[0098] When the pads at the first edge position and the pads at the second edge position are asymmetrically arranged, the identification of the first region 2081 and the second region 2082 of the corresponding first pad 208 from the first edge and the second edge respectively can be used to determine whether errors may occur in the identification results. For example, the identification of the first region 2081 and the second region 2082 of the corresponding first pad 208 from the first edge and the second edge should be different. If the detected conditions of the first pads on both sides are the same, it can be determined that at least one of the identification conditions of the two edges is incorrect.

[0099] It should be noted that, Figure 3a , Figure 3b , Figure 3c , Figure 3d , Figure 3e The descriptions of the quantity of the first and second pads (e.g., 4, 6, 8, 10, 20, etc.) are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0100] According to another aspect of this disclosure, a semiconductor device is also provided, comprising: a semiconductor functional structure and a packaging structure as described in the above embodiments of this disclosure.

[0101] According to another aspect of this disclosure, embodiments of this disclosure provide a method for manufacturing an encapsulation structure for forming the encapsulation structure in the above embodiments; Figure 4 This is a schematic flowchart illustrating a method for manufacturing a packaging structure according to an embodiment of this disclosure. Figure 4 As shown, the manufacturing method of the packaging structure provided in this embodiment includes the following steps:

[0102] Step S401: A redistribution layer is formed on the semiconductor functional structure, and the redistribution layer is electrically connected to the interconnect layer on the semiconductor functional structure;

[0103] Step S402: Form an insulating layer on the surface of the redistribution layer;

[0104] Step S403: Remove a portion of the insulating layer to expose a portion of the redistribution layer, forming at least one first pad; each first pad is formed by the portion of the redistribution layer exposed from the insulating layer;

[0105] The first pad includes a first area and a second area that are continuously arranged; the first area is used for testing, and the second area is used for performing functional interactions corresponding to the content of the test.

[0106] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs. Figures 5a to 5c This is a cross-sectional schematic diagram illustrating the fabrication process of a packaging structure provided in an embodiment of this disclosure. The following is in conjunction with... Figure 4 , Figures 5a to 5c The method for manufacturing the packaging structure provided in the embodiments of this disclosure will be described in detail.

[0107] In step S401, a redistribution layer is formed.

[0108] refer to Figure 5a Forming a redistribution layer includes: providing a substrate ( Figure 5a (Not shown in the figure); a semiconductor functional structure 500 is formed on the substrate; a redistribution layer 505 is formed on the semiconductor functional structure 500. The formation of the semiconductor functional structure on the substrate includes: forming a semiconductor functional layer 501 on the substrate; and forming an interconnect layer 502 on the semiconductor functional layer 501.

[0109] Here, the interconnect layer 502 can be formed on the semiconductor functional layer 501 by means of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0110] Next, an isolation layer 503 is formed on the interconnect layer; the isolation layer 503 is used to protect the interconnect layer 502 from damage. The constituent materials of the isolation layer 503 include, but are not limited to, tetraethyl orthosilicate (TEOS). The methods for forming the isolation layer 503 include, but are not limited to, PVD, CVD, ALD, and other processes.

[0111] Here, a portion of the isolation layer 503 is removed, resulting in a plurality of vias 504 in the isolation layer 503. These vias 504 expose portions of the interconnect layer 502; the exposed portions of the interconnect layer 502 serve as the area where the redistribution layer 505 is electrically connected to the interconnect layer 502. The vias 504 can be cylindrical, inverted trapezoidal, or any suitable shape.

[0112] Next, a redistribution layer 505 is formed on the surface of the isolation layer 503 and in the via 504, wherein the redistribution layer 505 is electrically connected to the interconnect layer 502.

[0113] In some specific embodiments, the redistribution layer 505 is formed on the isolation layer 503 by: forming a new conductor pattern on the isolation layer 503 by exposure and development; and then forming the redistribution layer 505 according to the new conductor pattern using electroplating technology. The redistribution layer 505 includes new conductor paths that are electrically connected to the interconnect layer 502. The constituent materials of the redistribution layer 505 include, but are not limited to, metals; preferably, the material of the redistribution layer is aluminum (Al).

[0114] It should be noted that the thickness of the redistribution layer on the exposed portion of the interconnect layer 502 can be the same as the thickness of the redistribution layer on the surface of the isolation layer 503. In some embodiments, the diameter of the via 504 is greater than twice the thickness of the redistribution layer. In this case, the redistribution layer 505 covers the sidewalls and bottom of the via 504, and the redistribution layer 505 forms a groove 506.

[0115] In step 402, refer to Figure 5b An insulating layer 507 is formed on the surface of the redistribution layer 505.

[0116] The insulating layer 507 covers the surface of the redistribution layer 505, serving two purposes: firstly, to isolate the redistribution layer 505 from electrical connections with other conductive materials, and secondly, to protect the redistribution layer 505 from damage. The material of the insulating layer 507 includes, but is not limited to, polyimide (PI). The methods for forming the first insulating layer 507 include, but are not limited to, PVD, CVD, and ALD processes.

[0117] Here, the groove 506 formed by the redistribution layer 505 is also filled with an insulating layer 507.

[0118] In some embodiments, the hardness of the material of the insulating layer 507 is less than the hardness of the material of the redistribution layer 505, which can reduce the stress on the packaging structure and increase reliability. In step 403, reference Figure 5c This forms at least one first liner 508.

[0119] Specifically, a portion of the insulating layer 507 is removed to expose a portion of the redistribution layer 505; the exposed portion of the redistribution layer 505 includes a first pad 508. Each of the first pads 508 includes a first region 5081 and a second region 5082 that are continuously disposed thereon; the first region 5081 is used for testing, and the second region 5082 is used for performing functional interactions corresponding to the content of the test.

[0120] Based on this, in various embodiments of this disclosure, at least one first pad is provided on the semiconductor functional structure, wherein each first pad includes a first region for performing tests and a second region for performing functional interactions corresponding to the test content; the first region and the second region are continuously arranged, in other words, no partition is provided between the first region and the second region. Thus, while ensuring that the region for testing and the region for performing functional interactions corresponding to the test content are physically distinct, damage to the probe card caused by the partition can be avoided during test execution if the probe is misaligned, thereby extending the lifespan of the probe card; simultaneously, reducing the generation of impurities helps improve test accuracy; furthermore, reducing damage to the partition by the probe card improves the overall reliability of the packaging structure.

[0121] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the various components shown or discussed may be coupled or directly coupled to each other.

[0122] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0123] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0124] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure, characterized in that, include: A redistribution layer, which is electrically connected to the interconnect layer of the semiconductor functional structure; An insulating layer that covers and exposes a portion of the redistribution layer; The exposed portion of the redistribution layer includes at least one first pad; wherein the first pad includes a first region and a second region disposed consecutively; the first region is used for testing; and the second region is used for performing functional interactions corresponding to the content of the test. The packaging structure further includes: a plurality of second pads, formed by a portion of the redistribution layer exposed by the insulating layer, for testing or for performing functional interactions corresponding to the content of the test; In this configuration, at least a portion of the second pads are arranged side-by-side with the at least one first pad along a first direction, the first direction being perpendicular to the direction from the first region to the second region; the area of ​​each first pad is greater than the area of ​​each second pad. Both the first pad and the second pad are elongated strips; the width of the first pad along the first direction is the same as the width of the second pad along the first direction; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush. The number of the first pads includes a plurality of first pads, at least a portion of which are arranged side by side along a first direction near a first edge of the semiconductor functional structure; at least a portion of the second pads are arranged side by side along the first direction on both sides of the plurality of first pads.

2. The packaging structure according to claim 1, characterized in that, At least two second pads are included on each side of at least part of the first pad.

3. The packaging structure according to claim 1, characterized in that, A first number of second pads are provided on a first side of the plurality of first pads, and a second number of second pads are provided on a second side of the plurality of first pads, wherein the first number is different from the second number.

4. The packaging structure according to claim 1, characterized in that, A portion of the second pads are arranged side-by-side on both sides of the plurality of first pads along a first direction, and another portion of the second pads are arranged side-by-side along a second direction near the second edge of the semiconductor functional structure; the second direction is perpendicular to the first direction; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

5. The packaging structure according to claim 1, characterized in that, The number of the first pads includes multiple pads, a portion of which are arranged side by side along a first direction near the first edge of the semiconductor functional structure, and another portion of which are arranged side by side along the first direction near the second edge of the semiconductor functional structure; a portion of the second pads are arranged side by side along the first direction on both sides of a portion of the first pads, and another portion of the second pads are arranged side by side along the first direction on both sides of another portion of the first pads; the first edge and the second edge are two opposite edges of the semiconductor functional structure.

6. The packaging structure according to claim 5, characterized in that, The arrangement of the first pad and the second pad located near the first edge of the semiconductor functional structure is symmetrical with the arrangement of the first pad and the second pad located near the second edge of the semiconductor functional structure.

7. The packaging structure according to any one of claims 1-6, characterized in that, All the pads arranged side by side along the first direction are flush with one end of the edge of the semiconductor functional structure; The first region is located at one end of the first pad near the edge of the semiconductor functional structure, and the second region is located at one end of the first pad away from the edge of the semiconductor functional structure.

8. A semiconductor device, characterized in that, include: Semiconductor functional structure and packaging structure as described in any one of claims 1 to 7.

9. A method for manufacturing an encapsulation structure, characterized in that, The method includes: A redistribution layer is formed on a semiconductor functional structure, and the redistribution layer is electrically connected to an interconnect layer on the semiconductor functional structure. An insulating layer is formed on the surface of the redistribution layer; A portion of the insulating layer is removed to expose a portion of the redistribution layer, forming at least one first pad and a plurality of second pads; each of the first pads and the second pads is formed by the portion of the redistribution layer exposed from the insulating layer. The first pad includes a first area and a second area that are continuously arranged; the first area is used for testing, and the second area is used for performing functional interactions corresponding to the content of the test; the second pad is used for testing or for performing functional interactions corresponding to the content of the test. In this configuration, at least a portion of the second pads are arranged side-by-side with the at least one first pad along a first direction, the first direction being perpendicular to the direction from the first region to the second region; the area of ​​each first pad is greater than the area of ​​each second pad. Both the first pad and the second pad are elongated strips; the width of the first pad along the first direction is the same as the width of the second pad along the first direction; the spacing between two adjacent pads is equal; and one end of all pads arranged side by side along the first direction is flush. The number of the first pads includes a plurality of first pads, at least a portion of which are arranged side by side along a first direction near a first edge of the semiconductor functional structure; at least a portion of the second pads are arranged side by side along the first direction on both sides of the plurality of first pads.

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