Semiconductor device termination structure, device, power module, electronic apparatus, and vehicle

Abstract

The application discloses a semiconductor device terminal structure and a device, a power module, an electronic equipment and a vehicle, and relates to the technical field of semiconductor devices. The semiconductor device terminal structure comprises a first field limiting ring layer and a first field limiting ring, a second field limiting ring layer and a second field limiting ring, a main junction, a cutoff ring, the first field limiting ring is arranged in the first field limiting ring layer, and the second field limiting ring is arranged in the second field limiting ring layer. By arranging the first field limiting ring in the first field limiting ring layer and arranging the second field limiting ring in the second field limiting ring layer, the junction depth of the well region is increased, the depletion layer is widened, and the purpose of improving the withstand voltage of the device is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device terminal structure, device, power module, electronic device, and vehicle. Background Technology

[0002] In semiconductor power devices, the cells in the active region are connected in parallel, making their surface potentials essentially the same. Adjacent P-well regions provide electric field shielding for the JFET (Junction Field Effect Transistor) region, resulting in highly ideal breakdown characteristics for the internal cells. However, the voltage difference between the outermost (terminating) cell and the substrate is significant. The most common termination measure is to use field-limiting loops to reduce the surface electric field and improve the termination breakdown voltage. However, field-limiting loop terminations often exhibit peak electric fields at the injection junction corners, which can easily cause device breakdown. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one objective of the present invention is to provide a semiconductor device termination structure that can effectively improve the withstand voltage of the semiconductor device, thereby reducing the risk of device breakdown.

[0004] The second objective of this invention is to provide a semiconductor device.

[0005] The third objective of this invention is to provide a power module.

[0006] The fourth objective of this invention is to provide an electronic device.

[0007] The fifth objective of this invention is to provide a vehicle.

[0008] To achieve the above objectives, a semiconductor device termination structure according to a first aspect embodiment of the present invention includes: a first field-limiting ring layer having opposing first and second surfaces; a second field-limiting ring layer having opposing third and fourth surfaces, the second field-limiting ring layer being disposed on the second surface of the first field-limiting ring layer, and the fourth surface of the second field-limiting ring layer being away from the first field-limiting ring layer; a field-limiting ring including: a first field-limiting ring and a second field-limiting ring, the first field-limiting ring being disposed within the first field-limiting ring layer; the second field-limiting ring being disposed within the second field-limiting ring layer; a main junction being disposed at one end of the first field-limiting ring layer and extending from the first surface of the first field-limiting ring layer into the interior of the first field-limiting ring layer; and a stop ring being disposed at the other end of the first field-limiting ring layer and extending from the first surface of the first field-limiting ring layer into the interior of the first field-limiting ring layer; the first field-limiting ring being disposed between the main junction and the stop ring.

[0009] According to the semiconductor device termination structure of the present invention, a first field limiting ring is provided in the first field limiting ring layer and a second field limiting ring is provided in the second field limiting ring layer, which increases the well junction depth and widens the depletion layer, thereby improving the device breakdown voltage.

[0010] In some embodiments of the present invention, the first field limiting ring extends from a first surface of the first field limiting ring layer toward the interior of the first field limiting ring layer; and / or, the second field limiting ring extends from a third surface of the second field limiting ring layer toward the interior of the second field limiting ring layer.

[0011] In some embodiments of the present invention, there are multiple first field limiting rings and / or second field limiting rings, which are arranged at intervals along the width direction of the semiconductor device terminal.

[0012] In some embodiments of the present invention, the first field limiting ring and the second field limiting ring are staggered along the width direction of the semiconductor device terminal.

[0013] In some embodiments of the present invention, at least one of the second field limiting loops is disposed directly below the main junction.

[0014] In some embodiments of the present invention, at least one of the second field limiting rings is offset from the main junction in the width direction of the substrate.

[0015] In some embodiments of the present invention, the first field limiting rings closer to the main junction are more densely packed than the first field limiting rings closer to the cutoff ring.

[0016] In some embodiments of the present invention, the spacing between two adjacent first field limiting rings increases sequentially along the direction from the main junction to the cutoff ring.

[0017] In some embodiments of the present invention, the width of the second field limiting ring decreases sequentially along the direction from the main junction to the cutoff ring.

[0018] In some embodiments of the present invention, the depth of the second field limiting ring decreases sequentially along the direction from the main junction to the cutoff ring.

[0019] In some embodiments of the present invention, the depth of the main junction is greater than the depths of the first field limiting loop and the second field limiting loop.

[0020] In some embodiments of the present invention, the depth of the first field limiting ring and / or the second field limiting ring is 3um-6um, and the width is 2um-4um.

[0021] In some embodiments of the present invention, the first field-limiting ring layer is a first epitaxial layer.

[0022] In some embodiments of the present invention, the first epitaxial layer is doped with phosphorus, and the phosphorus concentration is 10. 11 -10 14 atom / cm 3 .

[0023] In some embodiments of the present invention, the second field-limiting ring layer is a substrate.

[0024] In some embodiments of the present invention, the substrate is silicon carbide or silicon substrate.

[0025] In some embodiments of the present invention, a field oxide layer is disposed on the upper surface of the first field limiting ring layer and extends along the width direction of the semiconductor device to directly above the main junction and the cutoff ring.

[0026] In some embodiments of the present invention, metallized cathodes are disposed at both ends of the field oxide layer, with the metallized cathode at one end of the field oxide layer located directly above and in contact with the main junction, and the metallized cathode at the other end of the field oxide layer located directly above and in contact with the cutoff ring.

[0027] In some embodiments of the present invention, a third epitaxial layer and a metallized anode are sequentially disposed on the fourth surface of the substrate.

[0028] In some embodiments of the present invention, a fourth epitaxial layer is further disposed between the third epitaxial layer and the metallized anode, wherein the doping concentration of the fourth epitaxial layer is lower than that of the third epitaxial layer.

[0029] In some embodiments of the present invention, at least one intermediate field limiting ring layer is provided between the first field limiting ring layer and the second field limiting ring layer, wherein an intermediate field limiting ring is provided in the intermediate field limiting ring layer, and the intermediate field limiting ring extends from the upper surface of the intermediate field limiting ring layer into the interior of the intermediate field limiting ring layer.

[0030] To achieve the above objectives, the semiconductor device proposed in the second aspect of the present invention includes at least one semiconductor device termination structure as described in any one of the first aspect embodiments.

[0031] According to the semiconductor device proposed in the embodiments of the present invention, a first field limiting ring is provided in a first field limiting ring layer and a second field limiting ring is provided in a second field limiting ring layer, which increases the well junction depth and widens the depletion layer, thereby achieving the purpose of improving the device breakdown voltage.

[0032] To achieve the above objectives, the power module proposed in the third aspect of the present invention includes at least one semiconductor device termination structure as described in any of the first aspect embodiments.

[0033] According to the power module proposed in the embodiments of the present invention, the device terminal is provided with a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer, which increases the well junction depth, widens the depletion layer, improves the withstand voltage performance of the power module, and thus improves the service life of the power module.

[0034] To achieve the above objectives, a fourth aspect of the present invention provides an electronic device including the power module described in the third aspect of the present invention.

[0035] According to the electronic device of the present invention, the power module described in the third aspect embodiment above is used. In the power module, the device terminal is provided with a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer. This increases the well junction depth, widens the depletion layer, improves the voltage withstand performance of the power module, and thus improves the voltage withstand performance of the electronic device.

[0036] To achieve the above objectives, a fifth aspect of the present invention provides a vehicle including the power module described in the third aspect of the present invention.

[0037] According to the vehicle of the present invention, the power module described in the first aspect example above is used. In the power module, the device terminal is provided with a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer. This increases the well junction depth, widens the depletion layer, improves the withstand voltage performance of the power module, and thus ensures the safety of vehicle operation.

[0038] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0039] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0040] Figure 1 This is a schematic diagram of a semiconductor device terminal structure according to an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a semiconductor device terminal structure according to another embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of a semiconductor device terminal structure according to yet another embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0044] Figure 5This is a schematic diagram of a power module according to an embodiment of the present invention;

[0045] Figure 6 This is a schematic diagram of an electronic device according to an embodiment of the present invention;

[0046] Figure 7 This is a schematic diagram of a vehicle according to an embodiment of the present invention.

[0047] Figure label:

[0048] 5. Cut-off ring; 6. Main junction; 7. Metallized cathode; 8. Field oxide layer;

[0049] First round limit ring 9; First round limit ring 91; Second round limit ring 92;

[0050] First ring-limited layer 10; Second ring-limited layer 20;

[0051] Third epitaxial layer 30; Fourth epitaxial layer 40; Metallized anode 50;

[0052] Semiconductor device terminal structure 100; semiconductor device 200; power module 300;

[0053] Electronic equipment 400; vehicles 1000. Detailed Implementation

[0054] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary, and other modifications are also within the scope of protection of this application.

[0055] To improve the withstand voltage of devices, this invention proposes a semiconductor device termination structure. In this embodiment, the semiconductor device may include IGBTs, MOSFETs, etc.

[0056] The following is for reference. Figure 1 A semiconductor device termination structure according to an embodiment of the present invention is described.

[0057] Figure 1 This is a schematic diagram of a semiconductor device termination structure according to an embodiment of the present invention. Figure 1As shown, the semiconductor device termination structure of this embodiment includes a first field-limiting ring layer 10 and a second field-limiting ring layer 20. The first field-limiting ring layer 10 has opposing first and second surfaces, and the second field-limiting ring layer 20 has opposing third and fourth surfaces. The second field-limiting ring layer 20 is disposed on the second surface of the first field-limiting ring layer 10, and the fourth surface of the second field-limiting ring layer 20 is away from the first field-limiting ring layer 10. A field-limiting ring 9 includes a first field-limiting ring 91 and a second field-limiting ring 92. The first field-limiting ring 91 is disposed within the first field-limiting ring layer 10, and the second field-limiting ring 92 is disposed within the second field-limiting ring layer 20. A main junction 6 is disposed at one end of the first field-limiting ring layer 10 and extends from the first surface of the first field-limiting ring layer 10 into the interior of the first field-limiting ring layer 10. A stop ring 5 is disposed at the other end of the first field-limiting ring layer 10 and extends from the first surface of the first field-limiting ring layer 10 into the interior of the first field-limiting ring layer 10. The first field-limiting ring 91 is disposed between the main junction 6 and the stop ring 5.

[0058] In the semiconductor device terminal structure of this embodiment, a first field limiting ring 91 is provided in the first field limiting ring layer 10, and a second field limiting ring 92 is provided in the second field limiting ring layer 20, which increases the well junction depth and widens the depletion layer, thereby improving the device withstand voltage.

[0059] In some embodiments, the first field limiting ring 91 extends from a first surface of the first field limiting ring layer 10 toward the interior of the first field limiting ring layer 10; and / or, the second field limiting ring 92 extends from a third surface of the second field limiting ring layer 20 toward the interior of the second field limiting ring layer.

[0060] In some embodiments, there are multiple first field limiting rings 91 and / or second field limiting rings 92, which are spaced apart along the width direction of the semiconductor device terminal. The spaced arrangement of the first field limiting rings and / or second field limiting rings is equivalent to widening the depletion layer along the width direction of the semiconductor device terminal, thereby increasing the radius of curvature of the depletion layer and thus improving the breakdown voltage of the semiconductor device.

[0061] In some embodiments, the first field limiting ring 91 and the second field limiting ring 92 are staggered along the width direction of the semiconductor device termination. For example, in the substrate width direction, the first field limiting ring 91 and the adjacent second field limiting ring 92 are partially or completely staggered. This staggered arrangement increases the junction depth, widens the depletion layer, reduces the risk of main junction voltage concentration, and concentrates the internal electric field distribution within the substrate, enabling breakdown and ultimately improving the device's breakdown voltage.

[0062] In some embodiments, at least one of the second field limiting rings 92 is disposed directly below the main junction 6. In the semiconductor device termination structure, the main junction 6 has the largest voltage drop and is easily broken down. The second field limiting ring 92 disposed directly below the main junction 6 can reduce the risk of the main junction being broken down, thereby improving the device's withstand voltage.

[0063] In some embodiments, at least one of the second field limiting rings 92 is offset from the main junction 6 in the width direction of the semiconductor device terminal. This offset arrangement can increase the radius of curvature of the depletion layer, allowing the electric field lines of the depletion layer to connect seamlessly, achieving bulk breakdown and improving the device's withstand voltage performance.

[0064] In some embodiments, the first field limiting ring 91 closer to the main junction 6 is more densely packed than the first field limiting ring 91 closer to the stop ring 5. In the semiconductor device termination structure, the main junction 6 has the largest voltage division and is easily broken down. Therefore, placing the second field limiting rings more densely near the main junction 6 can reduce the risk of the main junction 6 being broken down and improve the device's withstand voltage performance.

[0065] More specifically, the spacing of the first field limiting ring 91 near the main junction 6 is smaller than the spacing of the billionth field limiting ring 91 near the cutoff ring 5.

[0066] In some embodiments, along the direction from the main junction 6 to the stop ring 5, the spacing between two adjacent first field limiting rings 91 increases sequentially.

[0067] In some embodiments, the width of the first field limiting ring 91 decreases sequentially along the direction from the main junction 6 to the stop ring 5.

[0068] In some embodiments, the depth of the first field limiting ring 91 decreases sequentially along the direction from the main junction 6 to the stop ring 5.

[0069] In some embodiments, the depth of the main junction 6 is greater than the depths of the first field limiting ring 91 and the second field limiting ring.

[0070] In some embodiments, the depth of the first field limiting ring 91 and / or the second field limiting ring 92 is 3um-6um, and the width is 2um-4um.

[0071] Depth refers to the distance extending inward from the first surface of the first field-limiting ring layer or the third surface of the second field-limiting ring layer. In the termination structure of semiconductor devices, by adjusting the spacing, width, and / or depth of the first field-limiting ring, the voltage of the main junction can be more effectively dispersed, the risk of voltage concentration in the main junction can be more effectively mitigated, and ultimately the device's withstand voltage can be improved.

[0072] In some embodiments, the first field-confining ring layer 10 is a first epitaxial layer, and the first epitaxial layer is doped with phosphorus element at a concentration of 10. 11 -10 14 atom / cm 3 .

[0073] In some embodiments, the second field-limiting layer 20 is a substrate, which is a silicon carbide or silicon substrate. The substrate has opposing third and fourth surfaces. The first epitaxial layer is disposed on the third surface of the substrate. Phosphorus doping of the third surface of the substrate can be performed using molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or liquid phase epitaxy (LPE) techniques, with a phosphorus concentration of 10. 11 -10 14 atom / cm 3 The phosphorus concentration can be adjusted according to actual production needs.

[0074] Specifically, in some embodiments, the main junction 6 is disposed at one end of the first epitaxial layer and extends from the first surface of the first epitaxial layer into the interior of the epitaxial layer; the first epitaxial layer can be boron-doped using an ion implantation process with a boron concentration of 10. 13 -10 15 atom / cm 3 The stop ring 5 is disposed at the other end of the first epitaxial layer and extends from the first surface of the first epitaxial layer into the interior of the first epitaxial layer; the first epitaxial layer can be phosphorus-doped using an ion implantation process, with a phosphorus concentration of 10. 14 -10 16 atom / cm 3 .

[0075] A first field-limiting ring 91 extends from the first surface of the first epitaxial layer into the interior of the first epitaxial layer. The first field-limiting ring 91 is disposed between the main junction and the stop ring. The first epitaxial layer can be doped with boron using an ion implantation process, with a boron concentration of 10. 11 -10 14 atom / cm 3 .

[0076] A main junction 6, a stop ring 5, and a first field limiting ring 91 located between the main junction 6 and the stop ring 5 are formed on the first surface of the first epitaxial layer 10. Taking a silicon carbide substrate as an example, specifically, a SiO2 protective layer is deposited on the upper surface of the first epitaxial layer 10, photoresist is spin-coated or otherwise coated on the SiO2 protective layer, and a second photolithography is performed to form an etching mask window. Through exposure and development, the first epitaxial layer 10 is doped by ion implantation, and the boron concentration at the main junction 6 is 10.13 -10 15 atom / cm 3 For example, a concentration of 10 13 atom / cm 3 The phosphorus concentration at point 5 of the ring was 10. 14 -10 16 atom / cm 3 For example, a concentration of 10 15 atom / cm 3 The first limited-ring boron concentration was 10. 11 -10 14 atom / cm 3 For example, it forms at a concentration of 10. 13 atom / cm 3， The depth of the main junction 6 is greater than the depth of the first field-limiting ring 91. The order in which the main junction 6, the cutoff ring 5, and the first field-limiting ring 91 are formed can be: first the main junction 6, then the cutoff ring 5, and then the first field-limiting ring 91; or first the main junction 6, then the first field-limiting ring 91, and then the cutoff ring 5; or other sequences. After the ion implantation process is completed, high-temperature diffusion bonding and impurity activation can be performed.

[0077] The second field-limiting ring 92 extends from the third surface of the substrate 4 into the interior of the substrate; the substrate can be doped with boron using an ion implantation process, with a boron concentration of 10. 11 -10 14 atom / cm 3 .

[0078] Taking silicon carbide substrate as an example, the specific process can be as follows: depositing a SiO2 protective layer on the selected SiC substrate surface, spin-coating or otherwise coating photoresist onto the SiO2 protective layer, performing a first photolithography to form an etching mask window, exposing and developing the substrate, and then performing boron doping treatment on the substrate through an ion implantation process, with a boron concentration of 10. 11 -10 14 atom / cm 3 After cleaning, the impurities are activated by high-temperature diffusion in a diffusion furnace.

[0079] In this embodiment, a first field limiting ring is provided in the first epitaxial layer and a second field limiting ring is provided in the substrate, which increases the well junction depth and widens the depletion layer, making the internal electric field distribution more concentrated in the substrate, thereby improving the breakdown voltage of the semiconductor device.

[0080] In some embodiments, the field oxide layer 8 is disposed on the first surface of the first field oxide layer 10, more specifically, on the first surface of the first epitaxial layer, and extends along the width direction of the semiconductor device termination to directly above the main junction 6 and the stop ring 5. The field oxide layer 8 can be prepared by a wet oxide (or dry oxide) process, and the material is not limited to silicon dioxide; other materials with good insulation properties and good lattice matching can also be used. Specifically, referring to the accompanying drawings, the first surface of the first field oxide layer 10 refers to the upper surface of the first field oxide layer 10; in some embodiments, it is the upper surface of the first epitaxial layer.

[0081] In some embodiments, the metallized cathode 7 is disposed at both ends of the field oxide layer 8, with the metallized cathode 7 at one end of the field oxide layer 8 located directly above and in contact with the main junction 6, and the metallized cathode 7 at the other end of the field oxide layer 8 located directly above and in contact with the cutoff ring 5.

[0082] Specifically, on the upper surface of the first epitaxial layer, metallized cathodes 7 can be formed at both ends of the field oxide layer 8 by metal evaporation or sputtering processes. The material can be aluminum, or other highly conductive materials such as gold, copper, or silver.

[0083] Specifically, such as Figure 1 As shown, the left boundary of the field oxide layer 8 exceeds the right boundary of the main junction 6, and the right boundary of the field oxide layer 8 exceeds the left boundary of the cutoff ring 5. The metallized cathode 7 is disposed directly above the main junction 6, which can improve the curvature of the depletion layer. The electric field is concentrated at the right end of the metallized cathode 7 and will not easily concentrate near the main junction 6. The electric field lines are stretched laterally (in the direction of the semiconductor device terminal width) to the right end, which can improve the breakdown voltage of the device.

[0084] In some embodiments, such as Figure 2 As shown, a third epitaxial layer 30 and a metallized anode 50 are sequentially disposed on the fourth surface (or back side) of the substrate.

[0085] Taking a silicon carbide substrate as an example, the preparation method of the third epitaxial layer 30 can specifically involve phosphorus doping the substrate through ion implantation or processes such as molecular beam epitaxy (MBE), chemical vapor deposition (CVD), or liquid phase epitaxy (LPE). The phosphorus concentration can be up to 10. 16 -10 18 atom / cm 3 For example, a concentration of 10 18 atom / cm 3 The metallized anode 50 can be formed by vapor deposition of highly conductive materials such as aluminum, gold, copper, or silver.

[0086] In some embodiments, such as Figure 3As shown, a fourth epitaxial layer 40 is further disposed between the third epitaxial layer 30 and the metallized anode 50. The doping concentration of the fourth epitaxial layer 40 is lower than that of the third epitaxial layer 30. The lower doping concentration of the fourth epitaxial layer 40 allows for a thicker overall epitaxial layer and a higher device withstand voltage. The fourth epitaxial layer 40 can be formed by ion implantation to dope boron onto its surface; the boron concentration can be up to 10%. 13 -10 15 atom / cm 3 For example, a concentration of 10 14 atom / cm 3 .

[0087] In some embodiments, at least one intermediate field limiting ring layer (not shown in the figures) is provided between the first field limiting ring layer 10 and the second field limiting ring layer 20. The intermediate field limiting ring layer contains an intermediate field limiting ring that extends from its upper surface into its interior. By providing an intermediate field limiting ring, the well junction depth is increased, the depletion layer is widened, and the device breakdown voltage is improved.

[0088] In some embodiments, the first intermediate ring-limiting layer is a second epitaxial layer (not shown in the figure), and the second epitaxial layer is doped with phosphorus at a concentration of 10. 11 -10 14 atom / cm 3 The intermediate field confinement ring can be achieved by doping the second epitaxial layer with boron using an ion implantation process, with a boron concentration of 10. 11 -10 14 atom / cm 3 .

[0089] The terminal structure of the semiconductor device according to the embodiments of the present invention has been described above. In summary, a first field limiting ring is provided in the first field limiting ring layer and a second field limiting ring is provided in the second field limiting ring layer, which increases the well junction depth and widens the depletion layer, thereby improving the breakdown voltage of the semiconductor device.

[0090] The devices in this invention are not only applicable to planar gate MOSFET structures, but also to other devices with MOS structures, such as IGBTs, as well as different device structures, such as trench gate MOSFET structures, and semiconductor devices with different substrates, such as Si-based or GaN-based semiconductor devices.

[0091] Based on the semiconductor device terminal structure of the above embodiments, the second aspect of the present invention also provides a semiconductor device, including at least one semiconductor device terminal structure as described in the first aspect embodiment.

[0092] In some embodiments of the present invention, such as Figure 4 The diagram shown is a block diagram of a semiconductor device according to an embodiment of the present invention. The semiconductor device 200 includes at least one semiconductor device termination structure 100 as described in the first aspect embodiment above. The semiconductor device termination structure 100 has a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer. The specific structure of the semiconductor device termination structure 100 can be found in the detailed description of the above embodiments, and will not be repeated here.

[0093] According to the semiconductor device proposed in the embodiments of the present invention, a first field limiting ring is provided in the first field limiting ring layer and a second field limiting ring is provided in the second field limiting ring layer, which increases the well junction depth and widens the depletion layer, thereby achieving the purpose of improving the device breakdown voltage.

[0094] Based on the semiconductor device terminal structure of the above embodiments, a third aspect of the present invention also provides a power module.

[0095] In some embodiments of the present invention, such as Figure 5 The diagram shown is a block diagram of a power module according to an embodiment of the present invention. The power module 300 includes at least one semiconductor device termination structure 100 as described in the first aspect embodiment above. The semiconductor device termination structure 100 has a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer. The specific structure of the semiconductor device termination structure 100 can be found in the detailed description of the above embodiments, and will not be repeated here.

[0096] The power module 300 proposed in the embodiments of the present invention employs at least one semiconductor device termination structure 100 as described in the above embodiments. By setting a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer of the semiconductor device termination structure 100, the well junction depth can be increased, the withstand voltage performance of the power module can be improved, and the service life of the power module can be improved.

[0097] In some embodiments of the present invention, such as Figure 6 The diagram shown is a block diagram of an electronic device according to an embodiment of the present invention. The electronic device 400 includes at least one power module 300 as described in the second aspect embodiment above. The power module 300 includes at least one semiconductor device termination structure 100 as described in the first aspect embodiment above. The semiconductor device termination structure 100 has a first field limiting ring in the first field limiting ring layer and a second field limiting ring in the second field limiting ring layer. The specific structure of the semiconductor device termination structure 100 can be found in the detailed description of the above embodiments, and will not be repeated here.

[0098] The electronic device can be a motor controller, or other suitable electronic devices, without limitation. Those skilled in the art can choose according to actual needs.

[0099] The electronic device 400 proposed according to the embodiments of the present invention includes a power module 300 as in the second aspect embodiment. The power module 300 adopts at least one semiconductor device termination structure 100 as in the above embodiment, and a first field limiting ring is provided in the first field limiting ring layer and a second field limiting ring is provided in the second field limiting ring layer. This can increase the well junction depth, widen the depletion layer, improve the voltage withstand performance of the power module, and thus improve the voltage withstand performance of the electronic device.

[0100] In some embodiments of the present invention, such as Figure 7 The diagram shown is a block diagram of a vehicle according to an embodiment of the present invention, wherein the vehicle 1000 includes a power module 300.

[0101] The vehicle 1000 according to an embodiment of the present invention includes a power module 300 as in the second aspect embodiment. The power module 300 employs at least one semiconductor device termination structure 100 as described in the above embodiment. A first field limiting ring is provided in the first field limiting ring layer, and a second field limiting ring is provided in the second field limiting ring layer. This can increase the well junction depth, widen the depletion layer, improve the withstand voltage performance of the power module, and thus ensure the safety of vehicle operation.

[0102] Other configurations and operations of the semiconductor device 200, power module 300, electronic device 400, and vehicle 1000 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0103] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0104] In the description of this invention, the terms "head end", "tail end", "inner", "outer", "upper", "left", "right", "top", "bottom", "back", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0105] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device termination structure, characterized in that, include: The first field-limiting ring layer has a first surface and a second surface that are opposite to each other. The second field-limiting layer has opposing third and fourth surfaces. A ring-limiting layer is disposed on the second surface of the first field ring-limiting layer, and the fourth surface of the second field ring-limiting layer is far from the first field ring-limiting layer; Field limiting loop, the field limiting loop including: a first field limiting loop and a second field limiting loop, wherein the first field limiting loop is set in the field limiting loop. The first field limiting ring layer is described above; the second field limiting ring is set within the second field limiting ring layer; The main junction is disposed at one end of the first field-limiting ring layer and extends from the first surface of the first field-limiting ring layer into the interior of the first field-limiting ring layer. A cutoff ring is disposed at the other end of the first field limiting ring layer and extends from the first surface of the first field limiting ring layer into the interior of the first field limiting ring layer; The first field limiting loop is disposed between the main junction and the cutoff loop; The depth of the main junction is greater than the depths of the first field limiting loop and the second field limiting loop; The second field-limiting ring layer is a substrate, and a third epitaxial layer and a metallized anode are sequentially disposed on the fourth surface of the substrate; A fourth epitaxial layer is disposed between the third epitaxial layer and the metallized anode, wherein the doping concentration of the fourth epitaxial layer is lower than that of the third epitaxial layer.

2. The semiconductor device termination structure according to claim 1, characterized in that, The first field limiting ring extends from the first surface of the first field limiting ring layer into the interior of the first field limiting ring layer; and / or, the second field limiting ring extends from the third surface of the second field limiting ring layer into the interior of the second field limiting ring layer.

3. The semiconductor device termination structure according to claim 1, characterized in that, The first field limiting ring and / or the second field limiting ring are multiple and are arranged at intervals along the width direction of the semiconductor device terminal.

4. The semiconductor device termination structure according to claim 3, characterized in that, The first field limiting ring and the second field limiting ring are staggered along the width direction of the semiconductor device terminal.

5. The semiconductor device termination structure according to claim 3, characterized in that, At least one of the second field limiting loops is positioned directly below the main junction.

6. The semiconductor device termination structure according to claim 3, characterized in that, At least one of the second field limiting loops is offset from the main junction in the width direction of the semiconductor device terminal.

7. The semiconductor device termination structure according to claim 3, characterized in that, The first field limiting ring closer to the main junction is denser than the first field limiting ring closer to the cutoff ring.

8. The semiconductor device termination structure according to claim 7, characterized in that, Along the direction from the main junction to the cutoff ring, the spacing between two adjacent first field limiting rings increases sequentially.

9. The semiconductor device termination structure according to claim 3, characterized in that, Along the direction from the main junction to the cutoff ring, the width of the first field limiting ring decreases sequentially.

10. The semiconductor device termination structure according to claim 3, characterized in that, Along the direction from the main junction to the cutoff ring, the depth of the first field limiting ring decreases sequentially.

11. The semiconductor device termination structure according to claim 1, characterized in that, The depth of the first field limiting loop and / or the second field limiting loop is 3 μm-6 μm, and the width is 2 μm-4 μm.

12. The semiconductor device termination structure according to claim 1, characterized in that, The first field-limited ring layer is the first epitaxial layer.

13. The semiconductor device termination structure according to claim 12, characterized in that, The first epitaxial layer is doped with phosphorus, and the phosphorus concentration is [missing information]. .

14. The semiconductor device termination structure according to claim 1, characterized in that, The substrate is a silicon carbide or silicon substrate.

15. The semiconductor device termination structure according to claim 1, characterized in that, The field oxide layer is disposed on the first surface of the first field limiting ring layer and extends along the width direction of the semiconductor device to directly above the main junction and the cutoff ring.

16. The semiconductor device termination structure according to claim 15, characterized in that, Metallized cathodes are disposed at both ends of the field oxide layer. The metallized cathode at one end of the field oxide layer is located directly above the main junction and in contact with the main junction, while the metallized cathode at the other end of the field oxide layer is located directly above the cutoff ring and in contact with the cutoff ring.

17. The semiconductor device termination structure according to claim 1, characterized in that, At least one intermediate field limiting ring layer is provided between the first field limiting ring layer and the second field limiting ring layer. The intermediate field limiting ring layer has an intermediate field limiting ring, which extends from the upper surface of the intermediate field limiting ring layer into the interior of the intermediate field limiting ring layer.

18. A semiconductor device, characterized in that, It includes at least one semiconductor device termination structure as described in any one of claims 1-17.

19. A power module, characterized in that, It includes at least one semiconductor device termination structure as described in any one of claims 1-17.

20. An electronic device, characterized in that, Includes the power module as described in claim 19.

21. A vehicle, characterized in that, Includes the power module as described in claim 20.

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