Shielded gate trench MOSFET and method of making the same

Abstract

The application provides a shielded gate trench MOSFET and a preparation method thereof. The shielded gate trench MOSFET comprises a substrate, an epitaxial layer, a shielding dielectric layer, an interlayer dielectric layer, a source lead contact hole and a source conductive layer. The epitaxial layer is located on the upper surface of the substrate and comprises a cell trench structure, a terminal lead structure, a source lead structure, a body region and a source region. The source lead structure comprises a source lead conductive layer. The shielding dielectric layer and the interlayer dielectric layer are sequentially stacked above the epitaxial layer. The source lead contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the source lead conductive layer. The source conductive layer is filled into the source lead contact hole. A shielding dielectric layer with a high selective etching ratio between the third dielectric layer and the interlayer dielectric layer is formed between the interlayer dielectric layer and the epitaxial layer. The third dielectric layer is shielded by the shielding dielectric layer to avoid damage to the third dielectric layer. The interlayer dielectric layer is planarized to avoid the deviation during exposure of the contact hole.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a shielded gate trench MOSFET and its fabrication method. Background Technology

[0002] In the field of low- and medium-voltage power MOSFETs, shielded gate trench MOSFETs have advantages such as lower on-resistance and faster switching speed compared to traditional trench MOSFETs. In system applications, they have lower conduction losses and lower switching losses, enabling the system to have higher conversion and transmission efficiency.

[0003] Currently, low-voltage shielded gate trench MOSFETs (typically 60V and below) require small linewidths (CD) and small cell pitches. However, domestic lithography machines used for power device production can only expose a minimum size of approximately 0.2–0.25 μm, with a positioning accuracy of 70 nm. Furthermore, wafer warpage during manufacturing makes it particularly easy for contact holes to shift at the wafer edge during etching. Figure 1 The diagram shown is a cross-sectional view of the structure after the source lead-out contact hole position is offset. It includes a substrate 01, an epitaxial layer 02, a cell trench structure 021, a first trench 0211, a first shielding gate layer 0212, a first dielectric layer 0213, a first isolation dielectric layer 0214, a gate dielectric layer 0215, a first gate conductive layer 0216, a terminal lead-out structure 0222, a second trench 0221, a second shielding gate layer 0222, a second dielectric layer 0223, and a second isolation dielectric layer 024. 24. Second gate conductive layer 0225, source lead-out structure 023, third trench 0231, third dielectric layer 0232, source lead-out conductive layer 0233, interlayer dielectric layer 03, source contact hole 031, terminal lead-out contact hole 032, source lead-out contact hole 033 and photoresist layer 04. If the source lead-out contact hole is offset, it will damage the oxide layer on the sidewall of the trench. Tungsten deposition in the contact hole forms a sharp wedge, which forms a current concentration point when energized, bringing a risk to use.

[0004] Therefore, there is an urgent need to find a method for fabricating shielded gate trench MOSFETs that avoids the offset of the source lead-out contact hole at the wafer edge and the formation of sharp wedges by the conductive pillars filling the contact hole during the fabrication process. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shielded gate trench MOSFET and its fabrication method, which solves the problems of source contact hole offset at the wafer edge and the formation of sharp wedges by conductive pillars filling the contact holes during the fabrication of shielded gate trench MOSFETs in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a shielded gate trench MOSFET, comprising the following steps:

[0007] A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate;

[0008] A cell trench structure, a terminal lead-out structure, a source lead-out structure, a second conductivity type body region, and a first conductivity type source region are formed in the epitaxial layer. The source lead-out structure includes a source lead-out conductive layer. The body region is located on the upper surface of the epitaxial layer between two adjacent cell trench structures and between the cell trench structure and the terminal lead-out structure. The source region is located on the upper surface of the body region.

[0009] A shielding medium layer and an interlayer medium layer covering the upper surface of the shielding medium layer are sequentially formed above the epitaxial layer, and the upper surface of the interlayer medium layer is planarized.

[0010] A source lead-out contact hole is formed that penetrates the interlayer dielectric layer and the shielding dielectric layer, and the bottom of the source lead-out contact hole extends into the source lead-out conductive layer;

[0011] A source conductive layer is formed on the upper surface of the interlayer dielectric layer, and the source conductive layer is also filled into the source lead-out contact hole.

[0012] Optionally, the cell trench structure includes a first trench, a first shielding gate layer filling the lower part of the first trench, a first dielectric layer wrapping the bottom surface and sidewalls of the first shielding gate layer and located on the inner wall of the first trench, a first isolation dielectric layer covering the upper surface of the first shielding gate layer and the first dielectric layer, a gate dielectric layer located on the inner wall of the first trench and covering the upper surface of the first isolation dielectric layer, and a first gate conductive layer filling the upper part of the first trench. The terminal lead-out structure includes a second trench, a second shielding gate layer filling the lower part of the second trench, a second dielectric layer wrapping the bottom surface and sidewalls of the second shielding gate layer and located on the inner wall of the second trench, a second isolation dielectric layer covering the upper surface of the second shielding gate layer and the second dielectric layer, the gate dielectric layer located on the inner wall of the second trench and covering the upper surface of the second isolation dielectric layer, and a second gate conductive layer filling the upper part of the second trench. The source lead-out structure includes a third trench and a third dielectric layer located on the inner wall of the third trench, and the source lead-out conductive layer fills the third trench. The gate dielectric layer also covers the upper surface of the epitaxial layer.

[0013] Optionally, forming the first isolation dielectric layer and the second isolation dielectric layer includes the following steps: forming an isolation dielectric material layer on the upper surface of the epitaxial layer, the isolation dielectric material layer filling the first trench and the second trench, and planarizing the upper surface of the isolation dielectric material layer; patterning the isolation dielectric material layer to obtain an opening of a first preset depth, wherein the bottom surface of the opening is lower than the upper surface of the epitaxial layer; removing the isolation dielectric material layer from the upper surface of the epitaxial layer, and deepening the bottom of the opening to a second preset depth to obtain the first isolation dielectric layer and the second isolation dielectric layer, wherein the opening size of the opening is the same as the opening size of the first trench.

[0014] Optionally, while forming the source lead-out contact hole, a source contact hole and a terminal lead-out contact hole are also formed, and the source contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the body region, and the terminal lead-out contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the second gate conductive layer.

[0015] Optionally, the material of the shielding dielectric layer is different from the material of the third dielectric layer.

[0016] Optionally, the material of the shielding medium layer includes silicon nitride.

[0017] Optionally, the method for planarizing the interlayer dielectric layer includes chemical mechanical polishing.

[0018] Optionally, the method for forming the source lead-out contact hole includes dry etching.

[0019] Optionally, the process of forming the source lead-out contact hole further includes a first etching stage, a second etching stage, and a third etching stage. The first etching stage includes etching the interlayer dielectric layer using a first etching condition until the shielding dielectric layer is exposed. The second etching stage includes etching the shielding dielectric layer using a second etching condition until the source lead-out conductive layer is exposed. The third etching stage includes etching the source lead-out conductive layer using a third etching condition.

[0020] The present invention also provides a shielded gate trench MOSFET, comprising:

[0021] First conductivity type substrate;

[0022] A first conductivity type epitaxial layer is located on the upper surface of the substrate and includes a cell trench structure, a terminal lead-out structure, a source lead-out structure, a second conductivity type body region, and a first conductivity type source region. The source lead-out structure includes a source lead-out conductive layer. The body region is located on the upper surface of the epitaxial layer between two adjacent cell trench structures and between the cell trench structure and the terminal lead-out structure. The source region is located on the upper surface of the body region.

[0023] A shielding dielectric layer is located above the epitaxial layer;

[0024] A planarized interlayer dielectric layer is located on the upper surface of the shielding dielectric layer;

[0025] The source lead-out contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the source lead-out conductive layer;

[0026] A source conductive layer is located on the upper surface of the interlayer dielectric layer and fills the source lead-out contact hole.

[0027] As described above, the shielded gate trench MOSFET and its fabrication method of the present invention form a shielding dielectric layer on the upper surface of the epitaxial layer after forming the cell trench structure, the termination lead structure, and the source lead structure, and before forming the interlayer dielectric layer. During the etching of the source lead contact hole, the shielding dielectric layer and the third dielectric layer have a high selectivity. During the etching of the source lead conductive layer, the opening size of the shielding dielectric layer remains unchanged. The shielding dielectric layer masks the third dielectric layer to prevent the bottom of the contact hole from expanding and damaging the third dielectric layer. The etching of the layer affects the stability of the device. After the interlayer dielectric layer is formed on the upper surface of the shielding dielectric layer, the upper surface of the interlayer dielectric layer is planarized to reduce the damage to the third dielectric layer caused by the positional displacement during exposure during the formation of the source lead-out contact hole. This results in an excessively small contact area between the source conductive layer filling the source lead-out contact hole and the source lead-out conductive layer, which in turn forms a wedge, causing current concentration and affecting the stability of the device. Moreover, without the need to add high-precision equipment and more complex process steps, the yield of the contact hole is guaranteed, which has high industrial application value. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the cross-sectional structure after the source lead-out contact hole position is offset, as shown in the fabrication method of a shielded gate trench MOSFET.

[0029] Figure 2 The diagram shows the process flow of the method for fabricating the shielded gate trench MOSFET of the present invention.

[0030] Figure 3 The diagram shows a cross-sectional structure of the shielded gate trench MOSFET fabrication method of the present invention after forming the first trench, the second trench, and the third trench.

[0031] Figure 4 The diagram shown is a cross-sectional view of the shielded gate trench MOSFET fabrication method of the present invention after the formation of the first conductive material layer.

[0032] Figure 5 The diagram shows a cross-sectional structure after forming the first and second shielding gate layers, which is a method for fabricating a shielded gate trench MOSFET according to the present invention.

[0033] Figure 6 The diagram shown is a cross-sectional view of the shielded gate trench MOSFET fabrication method of the present invention after the formation of the isolation dielectric material layer.

[0034] Figure 7 The diagram shows a cross-sectional structure after the formation of the second conductive material layer in the fabrication method of the shielded gate trench MOSFET of the present invention.

[0035] Figure 8 The diagram shows a cross-sectional structure after the source region is formed in the fabrication method of the shielded gate trench MOSFET of the present invention.

[0036] Figure 9 The diagram shown is a cross-sectional view of the shielded gate trench MOSFET fabrication method of the present invention after the formation of the interlayer dielectric layer.

[0037] Figure 10 The diagram shows a cross-sectional view of the shielded gate trench MOSFET fabrication method of the present invention after forming the source contact hole, the terminal lead-out contact hole, and the source lead-out contact hole.

[0038] Figure 11 The diagram shown is a cross-sectional view of the shielded gate trench MOSFET of the present invention.

[0039] Component designation explanation

[0040] 01 Substrate

[0041] 02 Epitaxial Layer

[0042] 021 Cellular groove structure

[0043] 0211 First Trench

[0044] 0212 First Shielding Grid Layer

[0045] 0213 First dielectric layer

[0046] 0214 First isolation medium layer

[0047] 0215 Gate dielectric layer

[0048] 0216 First gate conductive layer

[0049] 022 Terminal Outlet Structure

[0050] 0221 Second trench

[0051] 0222 Second Shielding Layer

[0052] 0223 Second dielectric layer

[0053] 0224 Second isolation medium layer

[0054] 0225 Second gate conductive layer

[0055] 023 Source pinout structure

[0056] 0231 Third trench

[0057] 0232 Third dielectric layer

[0058] 0233 Source electrode conductive layer

[0059] 03 Interlayer Dielectric Layer

[0060] 031 Source contact hole

[0061] 032 Terminal lead-out contact hole

[0062] 033 Source lead-out contact hole

[0063] 04 Photoresist layer

[0064] 1 Substrate

[0065] 2 Epitaxial layer

[0066] 21-cell groove structure

[0067] 211 First trench

[0068] 212 First Shielding Grid Layer

[0069] 213 First dielectric layer

[0070] 214 First isolation medium layer

[0071] 215 Gate dielectric layer

[0072] 216 First gate conductive layer

[0073] 217 Dielectric Material Layer

[0074] 218 First conductive material layer

[0075] 219 Second photoresist layer

[0076] 22 Terminal lead-out structure

[0077] 221 Second trench

[0078] 222 Second Shielding Layer

[0079] 223 Second dielectric layer

[0080] 224 Second isolation medium layer

[0081] 225 Second gate conductive layer

[0082] 226 Isolation Dielectric Material Layer

[0083] 227 Second conductive material layer

[0084] 228 Second Shielding Layer

[0085] 23 Source pinout structure

[0086] 231 Third trench

[0087] 232 Third dielectric layer

[0088] 233 Source electrode conductive layer

[0089] 3. Shielding medium layer

[0090] 4 Interlayer dielectric layer

[0091] 41 Source contact hole

[0092] 42 Terminal lead-out contact hole

[0093] 43 Source lead-out contact hole

[0094] 44 Third photoresist layer

[0095] 5. Source conductive layer

[0096] 6 Drain conductive layer Detailed Implementation

[0097] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0098] Please see Figures 2 to 11It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0099] Example 1

[0100] This embodiment provides a method for fabricating a shielded gate trench MOSFET, such as... Figure 2 The diagram shown is a process flow chart of the fabrication method of the shielded gate trench MOSFET, including the following steps:

[0101] S1: A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate;

[0102] S2: A cell trench structure, a terminal lead-out structure, a source lead-out structure, a second conductivity type body region, and a first conductivity type source region are formed in the epitaxial layer. The source lead-out structure includes a source lead-out conductive layer. The body region is located on the upper surface of the epitaxial layer between two adjacent cell trench structures and between the cell trench structure and the terminal lead-out structure. The source region is located on the upper surface of the body region.

[0103] S3: A shielding medium layer and an interlayer medium layer covering the upper surface of the shielding medium layer are sequentially formed above the epitaxial layer, and the upper surface of the interlayer medium layer is planarized.

[0104] S4: Form a source lead-out contact hole that penetrates the interlayer dielectric layer and the shielding dielectric layer, and the bottom of the source lead-out contact hole extends into the source lead-out conductive layer;

[0105] S5: A source conductive layer is formed on the upper surface of the interlayer dielectric, and the source conductive layer is also filled into the source lead-out contact hole.

[0106] Please see Figures 3 to 8 The steps S1 and S2 are performed as follows: a first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is formed on the upper surface of the substrate 1; a cell trench structure 21, a terminal lead-out structure 22, a source lead-out structure 23, a second conductivity type body region 24, and a first conductivity type source region 25 are formed in the epitaxial layer. The source lead-out structure 23 includes a source lead-out conductive layer 233. The body region 24 is located on the upper surface of the epitaxial layer 2 between two adjacent cell trench structures 21 and between the cell trench structure 21 and the terminal lead-out structure 22. The source region 25 is located on the upper surface of the body region 24.

[0107] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0108] Specifically, the substrate 1 is made of silicon or other suitable materials. In this embodiment, the substrate 1 is a silicon substrate.

[0109] Specifically, the method for forming the epitaxial layer 2 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0110] Specifically, the doping concentration of the substrate 1 can be selected according to actual conditions and is not limited here; the doping concentration of the epitaxial layer can be selected according to actual conditions and is not limited here. In this embodiment, the doping concentration of the substrate 1 is higher than the doping concentration of the epitaxial layer 2.

[0111] As an example, the cell trench structure 21 includes a first trench 211, a first shielding gate layer 212 filling the lower part of the first trench 211, a first dielectric layer 213 surrounding the bottom surface and sidewalls of the first shielding gate layer 212 and located on the inner wall of the first trench 211, a first isolation dielectric layer 214 covering the upper surfaces of the first shielding gate layer 212 and the first dielectric layer 213, a gate dielectric layer 215 located on the inner wall of the first trench 211 and covering the upper surface of the first isolation dielectric layer 214, and a first gate conductive layer 216 filling the upper part of the first trench 211. The terminal lead-out structure 22 includes a second trench 221 and a second shielding gate layer 222 filling the lower part of the second trench 221. The second dielectric layer 223, which encloses the bottom and sidewalls of the second shielding gate layer 222 and is located on the inner wall of the second trench 221, includes an isolation dielectric layer 224 covering the upper surfaces of the second shielding gate layer 222 and the second dielectric layer 223, a gate dielectric layer 215 located on the inner wall of the second trench 224 and covering the upper surface of the second isolation dielectric layer 224, and a second gate conductive layer 225 filling the upper part of the second trench 221. The source lead-out structure 23 includes a third trench 231 and a third dielectric layer 232 located on the inner wall of the third trench 231, and the source lead-out conductive layer 233 fills the third trench 231. The gate dielectric layer 215 also covers the upper surface of the epitaxial layer 2.

[0112] Specifically, such as Figure 3The diagram shows a cross-sectional view of the first trench 211, the second trench 221, and the third trench 231. The formation of the first trench 211, the second trench 221, and the third trench 231 further includes the following steps: forming a first photoresist layer (not shown) on the upper surface of the epitaxial layer 2 and patterning the first photoresist layer; forming the first trench 211, the second trench 221, and the third trench 231 based on the patterned first photoresist layer.

[0113] Specifically, the method for forming the first trench 211 includes dry etching, wet etching, or other suitable methods; the method for forming the second trench 221 includes dry etching, wet etching, or other suitable methods; and the method for forming the third trench 231 includes dry etching, wet etching, or other suitable methods. In this embodiment, the first trench 211, the second trench 221, and the third trench 231 are formed simultaneously using dry etching.

[0114] Specifically, the size of the first groove 211 can be selected according to actual conditions, and is not limited here; the size of the second groove 221 can be selected according to actual conditions, and is not limited here; the size of the third groove 231 can be selected according to actual conditions, and is not limited here. In this embodiment, the opening size of the first groove 211 is smaller than the opening size of the second groove 221.

[0115] Specifically, such as Figure 4 The diagram shows a cross-sectional view of the structure after the formation of the first conductive material layer 217, the first shielding gate layer 212, and the second shielding gate layer 222. The formation of the first shielding gate layer 212 and the second shielding gate layer 222 further includes the following steps: forming a dielectric material layer 217 on the inner walls of the first trench 211, the second trench 221, and the third trench 231, and on the upper surface of the epitaxial layer 2; forming a first conductive material layer 217 covering the upper surface of the dielectric material layer 217 and filling the first trench 211, the second trench 221, and the third trench 231. 8; Remove the dielectric material layer 217 and the first conductive material layer 218 on the upper surface of the epitaxial layer 2 to obtain the source lead-out conductive layer 233 and the third dielectric layer 232, and form a second photoresist layer 219 on the upper surface of the epitaxial layer 2; pattern the second photoresist layer 219 so that the second photoresist layer 219 blocks the opening surface of the third trench 231, and etch the first conductive material layer 218 in the first trench 211 and the second trench 221 to a preset depth to obtain the first shielding gate layer 212 and the second shielding gate layer 222.

[0116] Specifically, the method for forming the dielectric layer material layer 217 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.

[0117] Specifically, while ensuring the withstand voltage of the device, the thickness of the dielectric material layer 217 can be selected according to the actual situation, and is not limited here.

[0118] Specifically, the dielectric layer 217 is made of silicon oxide, silicon nitride, or other suitable dielectric materials.

[0119] Specifically, the method for forming the first conductive material layer 218 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0120] Specifically, the first conductive material layer 218 is made of polycrystalline silicon or other suitable conductive materials. In this embodiment, polycrystalline silicon is used as the first conductive material layer 218.

[0121] Specifically, such as Figure 5 The diagram shows a cross-sectional view of the structure after the formation of the first shielding gate layer 212 and the second shielding gate layer 222. The method for removing the first conductive material layer 218 from the upper surface of the dielectric layer 217 includes chemical mechanical polishing or other suitable methods; the method for removing the dielectric layer 217 from the upper surface of the epitaxial layer 2 includes chemical mechanical polishing or other suitable methods. In this embodiment, chemical mechanical polishing is used to simultaneously remove the dielectric layer 217 and the first conductive material layer 218 located above the epitaxial layer 2.

[0122] Specifically, the methods for forming the first shielding gate layer 212 and the second shielding gate layer 222 include dry etching, wet etching, or other suitable methods.

[0123] Specifically, while removing the first conductive material layer 218 in the first trench 211 and the second trench 221, the dielectric material layer 217 located on the inner wall of the first trench 211 and the second trench 221 can also be removed simultaneously to obtain the first dielectric layer 213 and the second dielectric layer 223, making the upper surface of the first shielding gate layer 212 flush with the upper surface of the first dielectric layer 213, and the upper surface of the second shielding gate layer 222 flush with the upper surface of the second dielectric layer 223. Alternatively, only the first conductive material layer 218 in the first trench 211 and the second trench 221 can be removed. In this embodiment, the dielectric material layer 217 and the first conductive material layer 218 in the first trench 211 and the second trench 221 are removed simultaneously.

[0124] Specifically, the thickness of the first shielding layer 212 formed in the first trench 211 can be selected based on actual conditions, and is not limited here; the thickness of the second shielding layer 222 formed in the second trench 221 can be selected based on actual conditions, and is not limited here. In this embodiment, the thickness of the first shielding layer 212 in the first trench 211 is the same as the thickness of the second shielding layer 222 in the second trench 221.

[0125] Specifically, after forming the first shielding gate layer 212 and the second shielding gate layer 222, the method further includes the step of removing the second photoresist layer 219.

[0126] Specifically, after removing the second photoresist layer 219, the process also includes the steps of forming the first isolation dielectric layer 214 and the second isolation dielectric layer 224.

[0127] Specifically, the first isolation medium layer 214 and the second isolation medium layer 224 are formed simultaneously.

[0128] As an example, such as Figure 6 The diagram shows a cross-sectional view of the structure after the formation of the isolation dielectric material layer 226. The formation of the first isolation dielectric layer 214 and the second isolation dielectric layer 224 includes the following steps: forming the isolation dielectric material layer 226 on the upper surface of the epitaxial layer 2, the isolation dielectric material layer 226 filling the first trench 211 and the second trench 221, and planarizing the upper surface of the isolation dielectric material layer 226; patterning the isolation dielectric material layer 226 to obtain an opening (not shown) of a first preset depth, and the bottom surface of the opening is lower than the upper surface of the epitaxial layer 2; removing the isolation dielectric material layer 226 from the upper surface of the epitaxial layer 2, and deepening the bottom of the opening to a second preset depth to obtain the first isolation dielectric layer 214 and the second isolation dielectric layer 224, and the opening size of the opening is the same as the opening size of the first trench 211.

[0129] Specifically, the method for forming the insulating medium material layer 226 includes high-density plasma chemical vapor deposition or other suitable methods.

[0130] Specifically, after planarizing the insulating medium material layer 226 and before forming the opening of the first preset depth, a window is formed on the upper surface of the insulating medium material layer 226, and the opening is formed based on the window.

[0131] Specifically, the method for planarizing the isolation medium material layer 226 includes chemical mechanical polishing or other suitable methods; the method for forming the window includes dry etching or other suitable methods; and the method for forming the opening at a first preset depth includes dry etching or other suitable methods.

[0132] Specifically, after removing the isolation medium material layer 226 on the upper surface of the epitaxial layer 2 and before forming the first isolation medium layer 214 and the second isolation medium layer 224, the step of forming a first shielding layer covering the opening of the third trench 231 is also included.

[0133] Specifically, the method for removing the isolation dielectric material layer 226 on the upper surface of the epitaxial layer 2 includes chemical mechanical polishing or other suitable methods; the method for deepening the bottom of the opening includes wet etching or other suitable methods.

[0134] Specifically, the opening size of the opening is the same as the size of the first trench 211, so that the isolation medium material layer 226 on the sidewall of the first trench 211 is etched clean.

[0135] Specifically, the second isolation layer formed in the second trench 221 includes the isolation dielectric material layer 226 of the remaining preset thickness located on the sidewall of the second trench 221 and the isolation dielectric material layer 226 covering the second dielectric layer 223 and the second shielding gate layer 221.

[0136] Specifically, after forming the first isolation dielectric layer 214 and the second isolation dielectric layer 224, the method further includes removing the first shielding layer and forming a gate dielectric layer 215 covering the upper surface of the epitaxial layer 2. The gate dielectric layer 215 also covers the inner wall of the first trench 211, the exposed surface of the first isolation dielectric layer 214, the exposed surface of the second isolation dielectric layer 224, the upper surface of the epitaxial layer 2, and the upper surface of the source lead-out structure 23. The method for forming the gate dielectric layer 215 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.

[0137] Specifically, while ensuring device safety, the thickness of the first isolation dielectric layer 214 formed in the first trench 211 can be selected according to the actual situation, and is not limited here; the thickness of the second isolation dielectric layer 224 formed in the second trench 221 can be selected according to the actual situation, and is not limited here.

[0138] Specifically, after forming the gate dielectric layer 215 and before forming the shielding dielectric layer 3, the process further includes the steps of forming the first gate conductive layer 216 and the second gate conductive layer 225.

[0139] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the structure after the formation of the second conductive material layer 227. The formation of the first gate conductive layer 216 and the second gate conductive layer 225 includes the following steps: forming a second conductive material layer 227 covering the upper surface of the gate dielectric layer 215, wherein the second conductive material layer 227 fills the first trench 211 and the second trench 221, and removing the second conductive material layer 227 from the upper surface of the gate dielectric layer 215; forming a patterned second masking layer 228 on the upper surface of the gate dielectric layer 215, and etching the second conductive material layer 227 based on the patterned second masking layer 228 to obtain the first gate conductive layer 216 and the second gate conductive layer 225, wherein the upper surfaces of the first gate conductive layer 216 and the second gate conductive layer 225 are both lower than the upper surface of the epitaxial layer 2.

[0140] Specifically, the second shielding layer 258 covers the upper surface of the epitaxial layer 2 and the source lead-out structure 23, and the second shielding layer 228 exposes the upper surface of the terminal lead-out structure 22, the upper surface of the epitaxial layer 2 located between the terminal lead-out structure 22 and the cell trench structure 21, the upper surface of the epitaxial layer 2 located between two adjacent cell trench structures 21, and the upper surface of the cell trench structure 21.

[0141] Specifically, the method for forming the second conductive material layer 227 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for removing the second conductive material layer 227 from the upper surface of the gate dielectric layer 215 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods; the method for removing the second conductive material layer 227 from the first trench 211 and the second trench 221 includes dry etching, wet etching, or other suitable methods.

[0142] Specifically, after forming the first gate conductive layer 216 and the second gate conductive layer 225, and before forming the shielding dielectric layer, the process further includes the step of sequentially forming the body region 24 and the source region 25. The body region 24 is located on the upper surface of the epitaxial layer 2 between the two adjacent cell trench structures 21 and between the cell trench structure 21 and the terminal lead-out structure 22. The source region 25 is located on the upper surface of the body region 24.

[0143] Specifically, such as Figure 8The diagram shows a cross-sectional view of the source region 25 after its formation. The method for forming the body region 24 includes ion implantation or other suitable methods; the method for forming the source region 25 includes ion implantation or other suitable methods. In this embodiment, when forming the body region 24 and the source region 25, the cell trench structure 21, the terminal lead-out structure 22, and the second shielding layer 228 are used as masking layers. The epitaxial layer 2 is then subjected to second conductivity type ion implantation and first conductivity type ion implantation sequentially to obtain the body region 24 and the source region 25 located on the upper surface of the body region 24.

[0144] Specifically, after forming the source region 25, the process also includes the step of removing the second shielding layer 228.

[0145] Please see Figures 9 to 10 Then, perform steps S3 and S4: sequentially form a shielding dielectric layer 3 covering the epitaxial layer 2 and an interlayer dielectric layer 4 covering the upper surface of the shielding dielectric layer 3 above the epitaxial layer 2, and planarize the upper surface of the interlayer dielectric layer 4; form a source lead-out contact hole 43 penetrating the interlayer dielectric layer 4 and the shielding dielectric layer 3, and the bottom of the source lead-out contact hole 43 extends into the source lead-out conductive layer 233.

[0146] Specifically, the interlayer dielectric layer 4 and the shielding dielectric layer 3 are made of different materials.

[0147] As an example, the material of the shielding dielectric layer 3 may include silicon nitride or other suitable high-dielectric materials.

[0148] Specifically, the material of the interlayer dielectric layer 4 includes silicon oxide or other suitable high-dielectric materials.

[0149] Specifically, such as Figure 9 The diagram shown is a cross-sectional view of the structure after the interlayer dielectric layer 4 is formed. The method for forming the shielding dielectric layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The method for forming the interlayer dielectric layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0150] As an example, methods for planarizing the interlayer dielectric layer 4 include chemical mechanical polishing or other suitable methods.

[0151] As an example, while forming the source lead-out contact hole 43, a source contact hole 41 and a terminal lead-out contact hole 42 are also formed. The source contact hole 41 penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends into the body region 24. The terminal lead-out contact hole 42 penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends into the second gate conductive layer 225.

[0152] Specifically, before forming the source lead-out contact hole 43, the upper surface of the interlayer dielectric layer 4 is planarized to reduce the offset during photolithography caused by the unevenness of the upper surface of the interlayer dielectric layer 4. This reduces the damage to the third dielectric layer 232 caused by the offset of the contact hole position when forming the source lead-out contact hole 43. Otherwise, the contact area between the source lead-out contact hole 43 and the source conductive layer 5 will be too small, resulting in the formation of a wedge. This will cause a current concentration point when the device conducts electricity, affecting the reliability of the device.

[0153] Specifically, after planarizing the interlayer dielectric layer 4 and before forming the source contact hole 41, the terminal lead-out contact hole 42 and the source lead-out contact hole 43, the process further includes forming a third photoresist layer 44 covering the upper surface of the interlayer dielectric layer 4 and patterning the third photoresist layer 44.

[0154] Specifically, such as Figure 10 The diagram shows a cross-sectional view of the source contact hole 41, the terminal lead-out contact hole 42, and the source lead-out contact hole 43. Based on the patterned third photoresist layer 44, the interlayer dielectric layer 4 and the shielding dielectric layer 3 are etched sequentially. After etching the shielding dielectric layer 3, the source region 25, the second gate conductive layer 225, and the source lead-out conductive layer 233 are etched to obtain the source contact hole 41, the terminal lead-out contact hole 42, and the source lead-out contact hole 43.

[0155] As an example, the method for forming the source lead-out contact hole 43 includes dry etching or other suitable methods.

[0156] Specifically, the method for forming the source contact hole 41 includes dry etching or other suitable methods; the method for forming the terminal lead-out contact hole 42 includes dry etching or other suitable methods.

[0157] As an example, the process of forming the source lead-out contact hole 43 further includes a first etching stage, a second etching stage, and a third etching stage. The first etching stage includes etching the interlayer dielectric layer 4 under a first etching condition until the shielding dielectric layer 3 is exposed. The second etching stage includes etching the shielding dielectric layer 3 under a second etching condition until the source lead-out conductive layer 233 is exposed. The third etching stage includes etching the source lead-out conductive layer 233 under a third etching condition.

[0158] Specifically, the second etching condition is different from the third etching condition, while the first etching condition can be the same as the third etching condition.

[0159] As an example, the material of the third dielectric layer 232 is different from that of the shielding dielectric layer 3, so that there is a high etching selectivity between the third dielectric layer 232 and the shielding dielectric layer 3.

[0160] Specifically, when forming the source lead-out contact hole 43, a dry etching method is used to achieve a high selectivity for the shielding dielectric layer 3 and the third dielectric layer 232. After the shielding dielectric layer 3 is etched, it is used as a mask layer to prevent the opening in the shielding dielectric layer 3 from continuing to expand and causing the third dielectric layer 232 to be etched, thereby damaging the third dielectric layer 232 and affecting the performance of the device.

[0161] Specifically, after forming the source contact hole 41 and before forming the source conductive layer 5, the process further includes forming a second conductive source contact region (not shown) in the body region 24.

[0162] Specifically, the doping concentration of the source contact region is higher than that of the body region 24, so that the source conductive layer 5 filling the source contact hole 41 forms an ohmic contact with the body region 24, thereby reducing the contact resistance of the electrode.

[0163] Specifically, after forming the source contact region and before forming the source conductive layer 5, the process also includes the step of removing the third photoresist layer 44.

[0164] Please see again Figure 11 Step S5 is performed: a source conductive layer 5 is formed on the upper surface of the interlayer dielectric layer 4, and the source conductive layer is filled into the source lead-out contact hole 43.

[0165] Specifically, the source conductive layer 5 also fills the source contact hole 41 and the terminal lead-out contact hole 42.

[0166] Specifically, the method for forming the source conductive layer 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods.

[0167] Specifically, the thickness of the formed source conductive layer 5 can be selected according to the actual situation, and is not limited here.

[0168] Specifically, it also includes the steps of forming a gate contact hole (not shown) in the interlayer dielectric layer 4, forming a gate layer (not shown) that fills the gate contact hole, and forming a drain conductive layer 6 on the lower surface of the substrate 1.

[0169] Specifically, since the formation of the gate contact hole and gate layer is a conventional process, it will not be described in detail here.

[0170] Specifically, the method for forming the drain conductive layer 6 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods.

[0171] The method for fabricating a shielded trench MOSFET in this embodiment involves forming a shielding dielectric layer 3 on the upper surface of the epitaxial layer 2, covering the upper surface of the epitaxial layer 4, after forming the source lead-out structure 23 and before forming the interlayer dielectric layer 4. The shielding dielectric layer 3 and the third dielectric layer 232 have a high etching selectivity ratio, ensuring that the source lead-out conductive layer 233 is not etched during the etching of the shielding dielectric layer 3. Simultaneously, the opening size in the shielding dielectric layer 3 remains unchanged during the etching of the source lead-out conductive layer 233, thus shielding the third dielectric layer 232 and preventing etching during the process. When the source lead-out conductive layer 233 is formed, the bottom of the source lead-out contact hole 43 expands, causing the third dielectric layer 232 to be etched. After the interlayer dielectric layer 4 is formed, the interlayer dielectric layer 4 is planarized to ensure the flatness of the upper surface of the interlayer dielectric layer 4 during photolithography, reduce the offset during exposure when forming the source lead-out contact hole 43, avoid damage to the third dielectric layer 232 caused by the offset of the source lead-out contact hole 43, and avoid the contact area between the source conductive layer 5 filling the source lead-out contact hole 43 and the source lead-out conductive layer 233 being too small, which would form a wedge, causing current concentration and affecting the stability of the device.

[0172] Example 2

[0173] This embodiment provides a shielded gate trench MOSFET, such as Figure 10 The diagram shown is a cross-sectional view of the shielded gate trench MOSFET, including a first conductivity type substrate 1, a first conductivity type epitaxial layer 2, a shielding dielectric layer 3, an interlayer dielectric layer 4, a source lead-out contact hole 43, and a source conductive layer 5. The epitaxial layer 2 is located on the upper surface of the substrate 1 and includes a cell trench structure 21, a terminal lead-out structure 22, a source lead-out structure 23, a second conductivity type body region 24, and a first conductivity type source region 25. The source lead-out structure 23 includes a source lead-out conductive layer, and the body region 24 is located between two adjacent cell trench junctions. The source region 25 is located on the upper surface of the epitaxial layer 2 between the cell trench structure 21 and the terminal lead-out structure 22; the shielding dielectric layer 3 is located above the epitaxial layer 2; the planarized interlayer dielectric layer 4 is located on the upper surface of the shielding layer 3; the source lead-out contact hole 43 penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends into the lead-out conductive layer 233; the source conductive layer 5 is located on the upper surface of the interlayer dielectric layer and fills the source lead-out contact hole 43.

[0174] Specifically, the shielded gate trench MOSFET is prepared using the preparation method described in Example 1.

[0175] Specifically, the thickness of the substrate 1 can be set according to the actual situation, and is not limited here.

[0176] Specifically, the thickness of the epitaxial layer 2 can be set according to the actual situation, and is not limited here.

[0177] Specifically, while ensuring device safety, the thickness of the shielding dielectric layer 3 can be selected according to the actual situation, and is not limited here; the thickness of the interlayer dielectric layer 4 can be selected according to the actual situation, and is not limited here.

[0178] Specifically, the shielding dielectric layer 3 and the third dielectric layer 232 have a high etching selectivity.

[0179] Specifically, the doping concentration of the body region 24 can be set according to the actual situation, and is not limited here; the doping concentration of the source region 25 can be set according to the actual situation, and is not limited here.

[0180] Specifically, the interlayer dielectric layer 4 is further provided with a source contact hole 41 and a terminal lead-out contact hole 42. The source contact hole 41 penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends into the body region 24. The terminal lead-out contact hole 43 penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends into the second gate conductive layer 225.

[0181] Specifically, the opening size of the source contact hole 41 can be set according to the actual situation, and is not limited here; the size of the terminal lead-out contact hole 42 can be set according to the actual situation, and is not limited here; the size of the source lead-out contact hole 43 can be set according to the actual situation, and is not limited here.

[0182] Specifically, the source conductive layer 5 is made of at least one of copper, aluminum, nickel, gold, tungsten, silver, and titanium, or other suitable conductive materials. In this embodiment, AlCu is used as the source conductive layer.

[0183] Specifically, the shielding dielectric layer 3 is used to prevent the bottom of the source lead-out contact hole 43 from expanding, thereby damaging the third dielectric layer 232 in the source lead-out structure 23.

[0184] Specifically, the shielded gate trench MOSFET also includes a gate layer and a drain conductive layer 6. The gate layer penetrates the interlayer dielectric layer 4 and the shielding dielectric layer 3 and extends to the first gate conductive layer 216. The drain conductive layer 6 is located on the lower surface of the substrate 1.

[0185] In this embodiment, the shielded gate trench MOSFET is provided with a shielding dielectric layer 3 between the epitaxial layer 2 and the interlayer dielectric layer 4, which has a high etching selectivity ratio with the third dielectric layer 232 and the interlayer dielectric layer 4. This prevents the bottom of the formed source lead-out contact hole 43 from being too large and damaging the third dielectric layer 232.

[0186] In summary, the shielded gate trench MOSFET and its fabrication method of the present invention reduce the offset during exposure for forming source lead-out contact holes by planarizing the upper surface of the interlayer dielectric layer, ensuring the accuracy of the source lead-out contact hole position during etching, preventing damage to the third dielectric layer caused by source lead-out contact hole offset, and avoiding the formation of wedges and current concentration due to excessively small contact area between the source conductive layer filling the source lead-out contact hole and the source lead-out conductive layer. A shielding dielectric layer with a high selectivity between the interlayer dielectric layer and the epitaxial layer and the third dielectric layer is formed, ensuring that the opening size at the shielding dielectric layer remains unchanged during etching of the source lead-out conductive layer, and using the shielding dielectric layer to shield the third dielectric layer, preventing damage to the third dielectric layer and affecting device stability. Furthermore, the yield of the contact holes is guaranteed without the need for additional high-precision equipment and complex process steps. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0187] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating a shielded gate trench MOSFET, comprising: Includes the following steps: A substrate of a first conductivity type is provided, and an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate; A cell trench structure, a terminal lead-out structure, a source lead-out structure, a second conductivity type body region, and a first conductivity type source region are formed in the epitaxial layer. The source lead-out structure includes a source lead-out conductive layer. The body region is located on the upper surface of the epitaxial layer between two adjacent cell trench structures and between the cell trench structure and the terminal lead-out structure. The source region is located on the upper surface of the body region. A shielding medium layer and an interlayer medium layer covering the upper surface of the shielding medium layer are sequentially formed above the epitaxial layer, and the upper surface of the interlayer medium layer is planarized. A source lead-out contact hole is formed that penetrates the interlayer dielectric layer and the shielding dielectric layer, and the bottom of the source lead-out contact hole extends into the source lead-out conductive layer; A source conductive layer is formed on the upper surface of the interlayer dielectric layer, and the source conductive layer is also filled into the source lead-out contact hole. The cell trench structure includes a first trench, a first shielding gate layer filling the lower part of the first trench, a first dielectric layer wrapping the bottom surface and sidewalls of the first shielding gate layer and located on the inner wall of the first trench, a first isolation dielectric layer covering the upper surface of the first shielding gate layer and the first dielectric layer, a gate dielectric layer located on the inner wall of the first trench and covering the upper surface of the first isolation dielectric layer, and a first gate conductive layer filling the upper part of the first trench. The terminal lead-out structure includes a second trench, a first [missing information - likely a type of conductive layer] filling the lower part of the second trench, and a [missing information - likely a type of conductive layer]. The second shielding gate layer comprises a second dielectric layer that encloses the bottom and sidewalls of the second shielding gate layer and is located on the inner wall of the second trench, a second isolation dielectric layer that covers the upper surface of the second shielding gate layer and the second dielectric layer, the gate dielectric layer located on the inner wall of the second trench and covering the upper surface of the second isolation dielectric layer, and a second gate conductive layer that fills the upper part of the second trench. The source lead-out structure includes a third trench and a third dielectric layer located on the inner wall of the third trench, and the source lead-out conductive layer fills the third trench. The gate dielectric layer also covers the upper surface of the epitaxial layer. The shielding dielectric layer and the third dielectric layer have a high etching selectivity.

2. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that, The formation of the first isolation dielectric layer and the second isolation dielectric layer includes the following steps: forming an isolation dielectric material layer on the upper surface of the epitaxial layer, the isolation dielectric material layer filling the first trench and the second trench, and planarizing the upper surface of the isolation dielectric material layer; forming an opening of a first preset depth in the isolation dielectric material layer, and the bottom surface of the opening is lower than the upper surface of the epitaxial layer; removing the isolation dielectric material layer on the upper surface of the epitaxial layer, and deepening the bottom of the opening to a second preset depth to obtain the first isolation dielectric layer and the second isolation dielectric layer, and the opening size of the opening is the same as the opening size of the first trench.

3. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: While forming the source lead-out contact hole, a source contact hole and a terminal lead-out contact hole are also formed. The source contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the body region. The terminal lead-out contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the second gate conductive layer.

4. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: The material of the shielding medium layer includes silicon nitride.

5. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: The material of the third dielectric layer is different from that of the shielding dielectric layer.

6. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: Methods for planarizing the interlayer dielectric layer include chemical mechanical polishing.

7. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: The method for forming the source lead-out contact hole includes dry etching.

8. The method for fabricating a shielded gate trench MOSFET according to claim 1, characterized in that: The process of forming the source lead-out contact hole further includes a first etching stage, a second etching stage, and a third etching stage. The first etching stage includes etching the interlayer dielectric layer using a first etching condition until the shielding dielectric layer is exposed. The second etching stage includes etching the shielding dielectric layer using a second etching condition until the source lead-out conductive layer is exposed. The third etching stage includes etching the source lead-out conductive layer using a third etching condition.

9. A shielded gate trench MOSFET, characterized in that, include: First conductivity type substrate; A first conductivity type epitaxial layer is located on the upper surface of the substrate and includes a cell trench structure, a terminal lead-out structure, a source lead-out structure, a second conductivity type body region, and a first conductivity type source region. The source lead-out structure includes a source lead-out conductive layer. The body region is located on the upper surface of the epitaxial layer between two adjacent cell trench structures and between the cell trench structure and the terminal lead-out structure. The source region is located on the upper surface of the body region. A shielding dielectric layer is located above the epitaxial layer; A planarized interlayer dielectric layer is located on the upper surface of the shielding dielectric layer; The source lead-out contact hole penetrates the interlayer dielectric layer and the shielding dielectric layer and extends into the source lead-out conductive layer; A source conductive layer is located on the upper surface of the interlayer dielectric layer and fills the source lead-out contact hole. The cell trench structure includes a first trench, a first shielding gate layer filling the lower part of the first trench, a first dielectric layer enclosing the bottom and sidewalls of the first shielding gate layer and located on the inner wall of the first trench, a first isolation dielectric layer covering the upper surface of the first shielding gate layer and the first dielectric layer, a gate dielectric layer located on the inner wall of the first trench and covering the upper surface of the first isolation dielectric layer, and a first gate conductive layer filling the upper part of the first trench. The terminal lead-out structure includes a second trench and a second shielding gate filling the lower part of the second trench. The epitaxial layer comprises a second dielectric layer that encloses the bottom and sidewalls of the second shielding gate layer and is located on the inner wall of the second trench, a second isolation dielectric layer that covers the upper surface of the second shielding gate layer and the second dielectric layer, the gate dielectric layer located on the inner wall of the second trench and covering the upper surface of the second isolation dielectric layer, and a second gate conductive layer that fills the upper part of the second trench. The source lead-out structure includes a third trench and a third dielectric layer located on the inner wall of the third trench, and the source lead-out conductive layer fills the third trench. The gate dielectric layer also covers the upper surface of the epitaxial layer. The shielding dielectric layer and the third dielectric layer have a high etching selectivity.

Images