Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the semiconductor structure comprises: a substrate; a trench in the substrate; a doped region on the sidewall and the bottom of the trench; a shield structure in the trench, the top of the shield structure is lower than the top of the trench; a gate structure on the shield structure. The semiconductor structure and the method of forming the same improve the compatibility of the transistor fabrication process and improve the process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the development of semiconductor technology, the size of semiconductor devices continues to shrink, and semiconductor devices have higher integration, faster operating speed, and lower efficiency.

[0003] As device dimensions shrink, the lithography dimensions required for semiconductor fabrication processes become increasingly smaller, while the performance requirements for these devices become increasingly demanding. Based on this, researchers have adopted various methods to fabricate small-sized transistor structures. For example, the widely studied all-around gate transistor (AGBMT) reduces transistor leakage current, shrinks size, and lowers device power consumption by surrounding the gate around a stacked channel.

[0004] In addition, some researchers have designed gates in unique shapes, thereby significantly reducing the actual size of the gate. For example, by designing the gate as a V-shape with a pointed tip, the tip width becomes the effective gate size, greatly improving the efficiency of transistor switching and reducing device power consumption.

[0005] However, in the existing technology, the compatibility of transistor fabrication processes is low and the process window needs to be improved. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which improves the compatibility of transistor fabrication processes and enhances the process window.

[0007] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, including: a substrate; a trench located in the substrate; doped regions located on the sidewalls and bottom of the trench; a shielding structure located in the trench, the top of the shielding structure being lower than the top of the trench; and a gate structure located on the shielding structure.

[0008] Optionally, the semiconductor structure further includes: a well region located on the sidewall of the trench; the top surface of the well region is higher than the top surface of the shielding structure, and the bottom surface of the well region is lower than the top surface of the shielding structure.

[0009] Optionally, the ratio of the gate structure thickness to the trench depth is in the range of 1:20 to 1:5; the gate structure thickness is in the range of 15 angstroms to 200 angstroms.

[0010] Optionally, the substrate may be made of silicon.

[0011] Optionally, the ratio of the dimension of the shielding structure to the trench depth in the direction perpendicular to the substrate surface ranges from 1:4 to 3:4; the dimension of the shielding structure in the direction perpendicular to the substrate surface ranges from 15 nanometers to 50 nanometers.

[0012] Optionally, the material of the shielding structure includes aluminum.

[0013] Optionally, the bottom dimension of the trench is smaller than the top dimension.

[0014] Optionally, the angle between the trench sidewall and the substrate surface ranges from 40 degrees to 65 degrees.

[0015] Optionally, the semiconductor structure further includes a gate oxide layer located on the surface of the doped region on the trench sidewalls and bottom.

[0016] Optionally, the semiconductor structure further includes a contact barrier layer located between the shielding structure and the gate structure.

[0017] Optionally, the material of the contact barrier layer includes aluminum oxide.

[0018] Optionally, the doped region contains a first doped ion; the first doped ion includes an N-type conductive ion.

[0019] Optionally, the well region contains a second doped ion; the second doped ion includes a P-type conductive ion.

[0020] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; etching the substrate to form a trench within the substrate; implanting first doped ions into the sidewalls and bottom of the trench to form a doped region; forming a shielding structure located within the trench, wherein the top of the shielding structure is lower than the top of the trench; and forming a gate structure on the shielding structure.

[0021] Optionally, after forming the shielding structure and before forming the gate structure, the method further includes: implanting second doped ions into the trench sidewalls to form a well region, wherein the top surface of the well region is higher than the top surface of the shielding structure and the bottom surface of the well region is lower than the top surface of the shielding structure.

[0022] Optionally, the process parameters for implanting a second doped ion into the trench sidewall include: the second doped ion includes a P-type conductive ion; and the implantation direction is perpendicular to the trench sidewall surface.

[0023] Optionally, before forming the gate structure, the method further includes: forming a barrier structure located on the sidewall of the trench, the barrier structure having a first opening, the projection pattern of the first opening on the substrate surface being located within the range of the projection pattern of the trench on the substrate surface.

[0024] Optionally, the method for forming the well region includes: using the shielding structure and the blocking structure as masks, implanting second doped ions into the trench sidewalls to form the well region.

[0025] Optionally, the method for forming the trench includes: forming a mask layer located on the surface of a substrate, the mask layer exposing a portion of the substrate surface; and etching the substrate using the mask layer as a mask to form the trench.

[0026] Optionally, the method for forming the gate structure includes: after forming the well region, depositing an initial gate structure on the shielding structure; and thinning the initial gate structure to form the gate structure.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] In the semiconductor structure provided by the technical solution of this invention, the trench has a shielding structure, which blocks the electric field influence of the gate structure on the doped region at the bottom of the trench, increasing the stability of transistor switching. Simultaneously, it reduces leakage current in the substrate at the bottom of the trench during transistor operation. Due to the presence of the shielding structure, no additional isolation structure is needed at the bottom of the trench, allowing the transistor to have reliable switching performance without affecting other devices within the substrate. This reduces substrate requirements, decreases process complexity, and improves process compatibility. Furthermore, the thickness of the gate structure determines the range of its electric field influence on the doped region on the trench sidewalls, thereby controlling the conduction and cutoff of the channel. The thickness of the gate structure is the actual size of the gate structure in operation. The presence of the shielding structure allows for better control of the gate structure thickness, thus overcoming the size limitations of photolithography and resulting in a smaller gate structure size.

[0029] Furthermore, since the trench sidewalls have well regions, the transistor is in a normally off state. The well regions serve as the channel of the transistor. Subsequently, by applying voltage to the gate structure, the conductive ions in the well regions are inverted, thereby turning on the channel. Therefore, compared to normally on depletion-mode transistors, the semiconductor structure of the present invention provides an enhancement-mode transistor structure and reduces the power consumption of the transistor.

[0030] In the semiconductor structure formation method provided by the present invention, a shielding structure is formed within the trench before the gate structure is formed. This shielding structure blocks the electric field influence of the gate structure on the doped region at the bottom of the trench, increasing the stability of transistor switching and reducing leakage current in the substrate at the bottom of the trench. Therefore, no additional isolation structure is needed at the bottom of the trench, reducing process difficulty and improving process compatibility. Furthermore, the thickness of the gate structure is the actual size of the gate structure in operation. Due to the presence of the shielding structure, the thickness of the gate structure can be better controlled by forming the gate structure on the shielding structure, thereby overcoming the size limitations of photolithography and forming a smaller gate structure.

[0031] Furthermore, since a well region is formed on the sidewall of the trench, the transistor is in a normally off state. Therefore, compared with a normally on depletion-type transistor, the semiconductor structure formation method of the present invention provides a method for forming an enhancement-type transistor, reducing the power consumption of the transistor.

[0032] Furthermore, during the formation of the well region, a shielding structure and a blocking structure are first formed within the trench. Then, using the shielding structure and the blocking structure as masks, second doped ions are injected into the trench sidewalls, forming the well region in a self-aligned manner. This defines the relative position of the well region and the subsequently formed gate structure, ensuring that the gate structure has an effective electric field influence on the well region. At the same time, the shielding structure controls the injection range of the second doped ions, making the size of the well region smaller, thereby further ensuring the small size characteristics of the transistor as a whole. Attached Figure Description

[0033] Figure 1 This is a schematic cross-sectional view of a semiconductor structure.

[0034] Figures 2 to 11 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, in the prior art, transistor fabrication processes have low compatibility and the process window needs improvement. The following analysis and explanation will focus on specific embodiments.

[0036] Figure 1 This is a schematic diagram of a cross-sectional structure of a semiconductor.

[0037] Please refer to Figure 1The semiconductor structure includes: a substrate (not shown), the substrate including an insulating layer 104 and a silicon substrate 100 located on the insulating layer 104; a trench (not shown) located in the substrate, the bottom dimension of the trench being smaller than the top dimension; doped regions 101 located on the sidewalls and bottom of the trench; a gate oxide layer 102 located on the doped regions 101; and a gate structure 103 located in the trench.

[0038] When no voltage is applied, the doped region 101, which serves as the transistor channel, is in a conducting state. When a voltage is applied to the gate structure 103, the conductive ions in the doped region 101 are inverted, thereby completing the channel cutoff of the transistor.

[0039] Specifically, when a voltage is applied to the gate structure 103, because the bottom dimension of the trench is smaller than the top dimension, a strong electric field exists at the bottom tip of the gate structure 103. That is, the actual effective portion of the gate structure 103 is at the bottom tip of the gate structure 103 (e.g., Figure 1 (As shown at point A in the middle), thereby causing the conductive ions in the doped region 101 at the bottom of the gate structure 103 to invert, thus completing the channel cutoff of the transistor.

[0040] Because there is a strong electric field at the bottom tip of the gate structure 103, in order to ensure the effectiveness of the transistor switching and reduce leakage, an insulating layer 104 needs to be set near the bottom of the gate structure 103 to ensure the reliable operation of the transistor. Therefore, the structure of the substrate is limited to silicon-on-insulator, resulting in higher costs for substrate preparation and acquisition, poor process compatibility of the transistor, and a smaller process window.

[0041] To address the aforementioned technical problems, the present invention provides a method for forming a semiconductor structure. Before forming the gate structure, a shielding structure is formed within a trench. Therefore, the shielding structure blocks the electric field influence of the gate structure on the doped region at the bottom of the trench. Consequently, an additional isolation structure is no longer needed at the bottom of the trench structure, reducing process complexity and improving process compatibility. Furthermore, the thickness of the gate structure is the actual size of the gate structure in operation. Due to the presence of the shielding structure, the thickness of the gate structure can be better controlled by forming the gate structure on the shielding structure, thereby overcoming the size limitations of photolithography and forming a smaller gate structure.

[0042] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Figures 2 to 11 This is a cross-sectional structural schematic diagram of the formation process of the semiconductor structure according to an embodiment of the present invention.

[0044] Please refer to Figure 2Provide a substrate 200; form an initial mask layer 205 on the surface of the substrate 200.

[0045] The substrate 200 is made of materials including silicon, silicon germanium, and silicon carbide. Specifically, in this embodiment, the substrate 200 is made of an elemental material, namely silicon.

[0046] In this embodiment, the material of the initial mask layer 205 includes silicon oxide.

[0047] Please refer to Figure 3 A mask opening 202 is formed in the initial mask layer 205 to form a mask layer 201, and the mask opening 202 exposes a portion of the substrate 200 surface.

[0048] In subsequent processes, the substrate 200 is etched using the mask layer 201 as a mask to form trenches 203, thereby defining the positions of the transistors composed of the doped regions, well regions, and gate structures that are subsequently formed. The width L1 of the mask opening 202 in the direction parallel to the surface of the substrate 200 defines the overall size of the transistor.

[0049] Specifically, in this embodiment, the width dimension L1 ranges from 40 nanometers to 60 nanometers.

[0050] Please refer to Figure 4 Using the mask layer 201 as a mask, the substrate 200 is etched to form a trench 203 within the substrate 200.

[0051] Trench 203 provides space for the subsequent formation of doped regions, well regions, shielding structures, and gate structures.

[0052] In this embodiment, the etching process for the substrate 200 includes a wet etching process. The etching solution used in the wet etching process includes an alkaline solution.

[0053] By using a wet etching process with an alkaline solution, the substrate 200 can be selectively etched, so that the surface of the trench 203 formed after etching is a (111) crystal plane, and the bottom dimension of the trench 203 is smaller than the top dimension, and the cross-sectional shape of the trench 203 along the direction perpendicular to the surface of the substrate 200 is an inverted triangle.

[0054] Specifically, the top of trench 203 has a size range of 15 nanometers to 60 nanometers; the bottom of trench 203 has a size range of 3 nanometers to 10 nanometers.

[0055] The sidewall of trench 203 is inclined relative to the surface of substrate 200, and the angle between the sidewall of trench 203 and the surface of substrate 200 ranges from 40 degrees to 65 degrees.

[0056] In this embodiment, the alkaline solution includes tetramethylammonium hydroxide.

[0057] In other embodiments, the bottom dimension of the trench is the same as the top dimension.

[0058] Please refer to Figure 5 A gate oxide layer 211 is formed on the sidewalls and bottom of the trench 203; first doped ions are implanted on the sidewalls and bottom of the trench 203 to form a doped region 210.

[0059] In this embodiment, the material of the gate oxide layer 211 includes silicon oxide.

[0060] In this embodiment, the thickness of the gate oxide layer 211 ranges from 10 angstroms to 30 angstroms.

[0061] In this embodiment, the doped region 210 works in conjunction with the subsequently formed well region to jointly affect the conduction and cutoff of the transistor channel.

[0062] In this embodiment, the doped region 210 contains a first doped ion; the first doped ion includes an N-type conductive ion.

[0063] In another embodiment, prior to forming the gate oxide layer, the method further includes depositing a doped material layer on the bottom and sidewall surfaces of the trench; the material of the doped material layer includes MoS2. First doped ions are implanted into the doped material layer.

[0064] In another embodiment, the material of the gate oxide layer includes hafnium dioxide.

[0065] Please refer to Figure 6 A barrier structure 212 is formed on the sidewall of the trench 203. The barrier structure 212 has a first opening 206. The projection pattern of the first opening 206 on the surface of the substrate 200 is located in the trench 203 (e.g., Figure 5 (As shown) within the range of the projected pattern on the surface of substrate 200.

[0066] The barrier structure 212 is used to control the position of the shielding structure and gate structure subsequently formed in the trench 203. At the same time, in subsequent processes, it enables the well region to be formed on the sidewall of the trench 203 in a self-aligned manner.

[0067] In this embodiment, the method for forming the barrier structure 212 includes: forming an initial barrier material layer (not shown) on the surface of the gate oxide layer 211 in the trench 203 and on the surface of the mask layer 201; etching the initial barrier material layer to form a first opening 206, the first opening exposing the gate oxide layer 211 at the bottom of the trench 203 and part of the sidewall surface, thereby making the initial barrier material layer the barrier structure 212.

[0068] In this embodiment, the projection pattern of the first opening 206 on the surface of the substrate 200 is located within the range of the projection pattern of the trench 203 on the surface of the substrate 200. The first opening 206 defines the relative positions of the subsequent shielding structure, well region, and gate structure, ensuring the effectiveness of the transistor.

[0069] In this embodiment, the size L2 of the first opening 206 ranges from 10 nanometers to 50 nanometers. Size L2 refers to the width of the first opening 206 in the direction parallel to the surface of the substrate 200.

[0070] In this embodiment, the material of the blocking structure 212 includes silicon nitride.

[0071] Please refer to Figure 7 This forms a shielding structure 220 located within the trench 203, with the top of the shielding structure 220 being lower than the top of the trench 203.

[0072] In this embodiment, the material of the shielding structure 220 includes aluminum.

[0073] The shielding structure 220 serves to block the electric field influence of the gate structure subsequently formed on its surface on the doped region 210 at the bottom of the trench 203, thereby increasing the stability of transistor switching. Furthermore, it reduces leakage current within the substrate 200 at the bottom of the trench 203 during transistor operation. Due to the presence of the shielding structure 220, an additional isolation structure 250 is no longer needed at the bottom of the trench 203. The transistor can reliably switch without affecting other devices within the substrate 200 using only the elemental silicon substrate 200, thus reducing process complexity and improving process compatibility.

[0074] In this embodiment, the ratio of the dimension of the shielding structure 220 in the direction perpendicular to the surface of the substrate 200 to the depth of the trench 203 ranges from 1:4 to 3:4; the dimension T1 of the shielding structure 220 in the direction perpendicular to the surface of the substrate 200 ranges from 15 nanometers to 50 nanometers.

[0075] In this embodiment, the method for forming the shielding structure 220 includes: forming an initial shielding material layer (not shown) located within the trench 203; and etching back the initial shielding material layer to form the shielding structure 220.

[0076] Specifically, the top of the shielding structure 220 is flush with the bottom of the blocking structure 212.

[0077] Next, a contact barrier layer 221 is formed on the shielding structure 220.

[0078] In this embodiment, the material of the contact barrier layer 221 includes aluminum oxide.

[0079] The contact barrier layer 221 serves to isolate the shielding structure 220 from the gate structure subsequently formed thereon, thereby ensuring the reliability of the transistor switch.

[0080] Please refer to Figure 8 A second doped ion is injected into the sidewall of trench 203 to form a well region 230. The top surface of the well region 230 is higher than the top surface of the shielding structure 220, and the bottom surface of the well region 230 is lower than the top surface of the shielding structure 220.

[0081] The well region 230 serves as the channel of the transistor. Due to the presence of the well region 230, the transistor is normally off. When the transistor is operating, the conductive ions in the well region 230 are inverted, thereby turning on the channel. Therefore, compared to a normally on depletion-mode transistor, this embodiment provides a method for forming an enhancement-mode transistor, reducing the power consumption of the transistor.

[0082] In this embodiment, the method for forming the well region 230 includes: using the shielding structure 220 and the blocking structure 212 as masks, implanting second doped ions into the sidewall of the trench 203 to form the well region 230.

[0083] The process parameters for implanting a second doped ion into the sidewall of trench 203 include: the second doped ion includes a P-type conductive ion; the implantation direction is perpendicular to the sidewall surface of trench 203.

[0084] During the formation of the well region 230, a shielding structure 220 and a blocking structure 212 are first formed within the trench 203. Then, using the shielding structure 220 and the blocking structure 212 as masks, second doped ions are implanted into the sidewall of the trench 203. Therefore, the well region 230 can be formed in a self-aligned manner on the sidewall of the trench 203, thereby defining the relative position of the well region 230 and the subsequently formed gate structure, ensuring that the gate structure has an effective electric field influence on the well region 230. At the same time, the second doped ions are implanted from the junction of the blocking structure 212 and the shielding structure 220. The blocking structure 212 and the shielding structure 220 control the implantation range of the second doped ions, thereby making the size of the well region 230 smaller and ensuring the small size of the transistor as a whole.

[0085] Please refer to Figure 9 A gate structure 240 is formed on the shielding structure 220.

[0086] The method for forming the gate structure 240 includes: depositing an initial gate structure (not shown) on a shielding structure 220 after forming a well region 230; and thinning the thickness of the initial gate structure to form the gate structure 240.

[0087] The thickness T2 of the gate structure 240 determines the range of its electric field influence on the doped region 210 of the trench 203 sidewall and the well region 230, thereby controlling the conduction and cutoff of the channel. Therefore, the thickness T2 of the gate structure 240 is the actual size of the gate structure 240 that plays a role.

[0088] Due to the presence of the shielding structure 220, the gate structure 240 can be formed by deposition, and through thinning, the thickness T2 of the gate structure 240 can be better controlled, thereby breaking through the size limit of the photolithography process and forming a smaller gate structure 240.

[0089] The ratio of the thickness T2 of the gate structure 240 to the depth of the trench 203 ranges from 1:20 to 1:5. Specifically, the thickness T2 of the gate structure 240 ranges from 15 angstroms to 200 angstroms.

[0090] In this embodiment, the material of the gate structure 240 includes polysilicon or metal.

[0091] Please refer to Figure 10 After forming the gate structure 240, the blocking structure 212 is removed; and an isolation structure 250 surrounding the gate structure 240 is formed.

[0092] In this embodiment, the material of the isolation structure 250 includes silicon oxide.

[0093] When no voltage is applied to the gate structure 240, the transistor is normally off. When a voltage is applied to the gate structure 240, the conductive ions in the well region 230 are inverted under the influence of the electric field generated by the gate structure 240, thereby turning on the channel, that is, realizing the switching effect of the transistor. Due to the presence of the shielding structure 220, the electric field of the gate structure 240 only affects the well region 230 on the sidewall of the trench 203, and has no effect on the doped region 210 below the shielding structure 220. This increases the stability of the transistor switching, reduces leakage current in the substrate 200 at the bottom of the trench 203, and eliminates the need for an additional isolation structure at the bottom of the trench 203, reducing the requirements for the substrate 200, thereby reducing the process difficulty and improving process compatibility.

[0094] Furthermore, the gate structure 240 is formed by deposition, which allows for better control over the thickness T2 of the gate structure 240, thereby breaking through the size limits of photolithography and forming a smaller gate structure 240. At the same time, the well region 230 is formed on the sidewall of the trench 203 by self-alignment, and the shielding structure 220 and the blocking structure 212 control the implantation range of the second doped ions, making the size of the well region 230, i.e., the transistor channel, smaller, thereby further reducing the overall size of the transistor and improving the integration and performance of the device.

[0095] Please refer to Figure 11 An upper dielectric layer 251 is formed on the isolation structure 250. Within the upper dielectric layer 251, a gate contact structure 260 is formed on the gate structure 240, and source contact structures 261 and drain contact structures 262 are formed on the surfaces of the doped regions 210 on both sides of the gate structure 240. The gate contact structure 260, source contact structure 261, and drain contact structure 262 connect the transistor to the upper electrical interconnect structure (not shown).

[0096] Accordingly, embodiments of the present invention also provide a semiconductor structure formed using the above method.

[0097] Please continue to refer to this. Figure 10 The semiconductor structure includes: a substrate 200; trenches located within the substrate 200 (e.g., ... Figure 5 (as shown); doped regions 210 located on the sidewalls and bottom of trench 203; shielding structure 220 located within trench 203, with the top of shielding structure 220 lower than the top of trench 203; gate structure 240 located on shielding structure 220.

[0098] In this embodiment, the semiconductor structure further includes a well region 230 located on the sidewall of the trench 203; the top surface of the well region 230 is higher than the top surface of the shielding structure 220, and the bottom surface of the well region 230 is lower than the top surface of the shielding structure 220.

[0099] In this embodiment, the ratio of the thickness of the gate structure 240 to the depth of the trench 203 is in the range of 1:20 to 1:5; the thickness of the gate structure 240 is in the range of 15 angstroms to 200 angstroms.

[0100] In this embodiment, the substrate 200 is made of silicon.

[0101] In this embodiment, the ratio of the size of the shielding structure 220 in the direction perpendicular to the surface of the substrate 200 to the depth of the trench 203 is in the range of 1:4 to 3:4; the size of the shielding structure 220 in the direction perpendicular to the surface of the substrate 200 is in the range of 15 nanometers to 50 nanometers.

[0102] In this embodiment, the material of the shielding structure 220 includes aluminum.

[0103] In this embodiment, the bottom dimension of the trench 203 is smaller than the top dimension.

[0104] In this embodiment, the top of the trench 203 has a size range of 15 nanometers to 60 nanometers; the bottom of the trench 203 has a size range of 3 nanometers to 10 nanometers.

[0105] In this embodiment, the angle between the sidewall of the trench 203 and the surface of the substrate 200 ranges from 40 degrees to 65 degrees.

[0106] In this embodiment, the semiconductor structure further includes a gate oxide layer 211 on the surface of the doped region 210 located on the sidewalls and bottom of the trench 203.

[0107] In this embodiment, the thickness of the gate oxide layer 211 ranges from 10 angstroms to 30 angstroms.

[0108] In this embodiment, the semiconductor structure further includes a contact barrier layer 221 located between the shielding structure 220 and the gate structure 240.

[0109] In this embodiment, the material of the contact barrier layer 221 includes aluminum oxide.

[0110] In this embodiment, the doped region 210 contains a first doped ion; the first doped ion includes an N-type conductive ion.

[0111] In this embodiment, the well region 230 contains a second doped ion; the second doped ion includes a P-type conductive ion.

[0112] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A trench located within the substrate, wherein the bottom width of the trench is smaller than the top width; The doped regions located on the sidewalls and bottom of the trench; A shielding structure located within the trench and covering the doped region, wherein the top of the shielding structure is lower than the top of the trench; The well region located on the sidewall of the trench; The top surface of the well region is higher than the top surface of the shielding structure, the bottom surface of the well region is lower than the top surface of the shielding structure, and the well region is connected to the doped region on both sides along the direction parallel to the trench sidewall. The gate structure located on the shielding structure; The doped region contains a first doped ion; the first doped ion includes an N-type conductive ion; the well region contains a second doped ion; the second doped ion includes a P-type conductive ion; the well region serves as a transistor channel.

2. The semiconductor structure as described in claim 1, characterized in that, The ratio of the gate structure thickness to the trench depth is in the range of 1:20 to 1:5; the gate structure thickness is in the range of 15 angstroms to 200 angstroms.

3. The semiconductor structure as described in claim 1, characterized in that, The substrate is made of silicon.

4. The semiconductor structure as described in claim 1, characterized in that, The ratio of the dimension of the shielding structure to the trench depth in the direction perpendicular to the substrate surface ranges from 1:4 to 3:4; the dimension of the shielding structure in the direction perpendicular to the substrate surface ranges from 15 nanometers to 50 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The material of the shielding structure includes aluminum.

6. The semiconductor structure as described in claim 1, characterized in that, The angle between the trench sidewall and the substrate surface ranges from 40 degrees to 65 degrees.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: Gate oxide layer located on the surface of the doped region on the trench sidewalls and bottom.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A contact barrier layer located between the shielding structure and the gate structure.

9. The semiconductor structure as described in claim 8, characterized in that, The material of the contact barrier layer includes aluminum oxide.

10. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; The substrate is etched to form trenches within the substrate, wherein the bottom width of the trenches is smaller than the top width; First doped ions are injected into the sidewalls and bottom of the trench to form a doped region; A shielding structure is formed within the trench, covering the doped region, with the top of the shielding structure lower than the top of the trench. After the shielding structure is formed, a second dopant ion is implanted into the trench sidewall to form a well region. The top surface of the well region is higher than the top surface of the shielding structure, and the bottom surface of the well region is lower than the top surface of the shielding structure. The well region is connected to the doped region on both sides along the direction parallel to the trench sidewall. A gate structure is formed on the shielding structure; The doped region contains a first doped ion, which includes N-type conductive ions; the well region contains a second doped ion, which includes P-type conductive ions; and the well region serves as a transistor channel.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process parameters for implanting a second doped ion into the trench sidewall include: the second doped ion includes a P-type conductive ion; the implantation direction is perpendicular to the trench sidewall surface.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, Before forming the gate structure, the method further includes: forming a barrier structure located on the sidewall of the trench, the barrier structure having a first opening, the projection pattern of the first opening on the substrate surface being located within the range of the projection pattern of the trench on the substrate surface.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the well region includes: using the shielding structure and the blocking structure as masks, implanting second doped ions into the trench sidewalls to form the well region.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the trench includes: forming a mask layer on the surface of a substrate, the mask layer exposing a portion of the substrate surface; and etching the substrate using the mask layer as a mask to form a trench.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the gate structure includes: after forming the well region, depositing an initial gate structure on the shielding structure; and thinning the initial gate structure to form the gate structure.

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