Method and apparatus for edge passivation of copper grid silicon heterojunction solar cells

Abstract

This disclosure discloses a method and apparatus for edge passivation of copper-grid silicon heterojunction solar cells, relating to the field of battery technology. The method includes: slicing the copper-grid silicon heterojunction solar cell to obtain multiple cell wafers; transferring a stack of cell wafers to a chemical vapor deposition (CVD) apparatus; introducing hydrogen gas into the CVD apparatus for a preset time period, wherein the first hydrogen gas flow rate is 5000-25000 sccm; and depositing an intrinsic amorphous silicon thin film at the slice cross-section of each cell wafer in the stack to obtain edge-passivated cell wafers, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. Therefore, passivation treatment of the slice cross-section of the copper-grid silicon heterojunction solar cell wafers can be performed at low temperatures, ensuring that the copper-grid silicon heterojunction solar cell wafers and copper electrodes are not affected, reducing the carrier recombination rate at the slice cross-section of the copper-grid silicon heterojunction solar cell wafers, improving the passivation effect, and increasing the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

Description

Technical Field

[0001] This disclosure relates to the field of battery technology, and in particular to a method and apparatus for edge passivation of copper grid silicon heterojunction cells. Background Technology

[0002] With the widespread application of module technologies such as half-cell modules, shingled modules, and tiled modules, laser scribing has become an important process in module manufacturing. This involves using lasers to cut full-size cells into 1 / 2, 1 / 3, 1 / 6, ..., 1 / n cell segments.

[0003] After laser cutting of a whole cell, the fracture surface defects are severe, significantly impacting the electrical performance of the cell segments. Studies show that after a silicon heterojunction cell is laser-cut into two halves, the efficiency of each half cell decreases by 0.3% abs. If cut into even smaller segments, the impact of edge defects becomes more pronounced due to the increased perimeter / area ratio, ultimately leading to a greater reduction in the efficiency of the segmented cells and consequently, a decrease in module output power.

[0004] In related technologies, the edges of solar cells can be passivated to reduce efficiency loss. However, no effective method for passivating the edges of copper-grid silicon heterojunction solar cell slices has been proposed. Therefore, how to passivate the edges of copper-grid silicon heterojunction solar cell slices has become a key research direction. Summary of the Invention

[0005] This disclosure aims to at least partially address one of the technical problems in the related art.

[0006] The first aspect of this disclosure provides a method for edge passivation of a copper grid silicon heterojunction solar cell, comprising:

[0007] The copper grid silicon heterojunction solar cell is sliced ​​to obtain multiple cell slices;

[0008] The battery stack, formed by stacking multiple battery cells, is transferred to a chemical vapor deposition apparatus;

[0009] Hydrogen gas is introduced into the chemical vapor deposition equipment within a preset time period, wherein the first hydrogen gas flow rate is 5000-25000 sccm;

[0010] An intrinsic amorphous silicon thin film is deposited at the cross-section of each battery segment in the battery stack to obtain edge-passivated battery segments, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C.

[0011] Optionally, after obtaining the edge-passivated battery slabs, the method further includes:

[0012] The cross-section of the battery slice with blunted edges is subjected to light irradiation treatment, wherein the heating temperature of the light irradiation treatment does not exceed 120°C.

[0013] Optionally, the thickness of the intrinsic amorphous silicon thin film is 5-30 nm.

[0014] Optionally, the chemical vapor deposition equipment is any one of the following: a plasma-enhanced chemical vapor deposition equipment, or a hot-wire chemical vapor deposition equipment.

[0015] Optionally, when the chemical vapor deposition equipment is a plasma-enhanced chemical vapor deposition equipment, during the deposition of an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the battery stack, the deposition power of the intrinsic amorphous silicon thin film is 15-60 mW / cm², and the ratio between the second hydrogen flow rate and the silane flow rate is 0.3-10.

[0016] Optionally, when the chemical vapor deposition equipment is a hot-wire chemical vapor deposition equipment, the hot-wire temperature is 1600-2100°C during the deposition of an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the battery stack.

[0017] A second aspect of this disclosure provides an edge passivation device for a copper grid silicon heterojunction solar cell, comprising:

[0018] The slicing module is used to slice copper grid silicon heterojunction solar cells to obtain multiple cell slices;

[0019] A transfer module is used to transfer a battery stack formed by stacking multiple battery wafers to a chemical vapor deposition apparatus;

[0020] The hydrogen injection module is used to introduce hydrogen into the chemical vapor deposition equipment within a preset time period, wherein the first hydrogen flow rate is 5000-25000 sccm.

[0021] A thin film deposition module is used to deposit an intrinsic amorphous silicon thin film at the cross-section of each battery segment in the battery stack to obtain edge-passivated battery segments, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C.

[0022] Optional, also includes:

[0023] The post-processing module is used to perform light irradiation on the cross-section of the edge-passivated battery slice, wherein the heating temperature of the light irradiation process does not exceed 120°C.

[0024] A third aspect of this disclosure provides a copper grid silicon heterojunction solar cell, comprising: a copper grid silicon heterojunction solar cell manufactured according to the edge passivation method of the copper grid silicon heterojunction solar cell proposed in the first aspect embodiment, wherein the cross-section of the copper grid silicon heterojunction solar cell is subjected to hydrogen implantation treatment and has an intrinsic amorphous silicon thin film deposited thereon.

[0025] The copper grid silicon heterojunction solar cell edge passivation method and apparatus disclosed herein have the following beneficial effects:

[0026] In this embodiment, the copper-grid silicon heterojunction solar cell is first sliced ​​to obtain multiple cell wafers. Then, a stack of these wafers is transferred to a chemical vapor deposition (CVD) apparatus. Hydrogen gas is introduced into the CVD apparatus within a preset time period, with a flow rate of 5000-25000 sccm. Finally, an intrinsic amorphous silicon thin film is deposited at the slice cross-section of each cell wafer in the stack to obtain edge-passivated cell wafers. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. This allows for passivation treatment of the slice cross-sections of the copper-grid silicon heterojunction solar cell wafers at low temperatures. This ensures that the copper-grid silicon heterojunction solar cell wafers and copper electrodes are not affected, while reducing the carrier recombination rate at the slice cross-sections, improving the passivation effect, effectively compensating for recombination losses caused by slicing, and improving the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

[0027] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0028] The above and / or additional aspects and advantages of this disclosure will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a schematic flowchart of an edge passivation method for a copper grid silicon heterojunction solar cell provided in an embodiment of the present disclosure.

[0030] Figure 2 This is a schematic flowchart of an edge passivation method for a copper grid silicon heterojunction solar cell provided in another embodiment of this disclosure;

[0031] Figure 3 This is a schematic diagram of the edge passivation device for a copper grid silicon heterojunction solar cell provided in an embodiment of the present disclosure.

[0032] Figure 4 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Detailed Implementation

[0033] Embodiments of this disclosure are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting this disclosure.

[0034] The following description, with reference to the accompanying drawings, outlines an edge passivation method, apparatus, electronic device, and storage medium for copper grid-wire silicon heterojunction solar cells according to embodiments of the present disclosure.

[0035] Figure 1 This is a schematic flowchart illustrating the edge passivation method for copper grid silicon heterojunction solar cells provided in this embodiment of the disclosure.

[0036] like Figure 1 As shown, the method for passivating the cross-sectional edge of the copper grid silicon heterojunction solar cell may include the following steps:

[0037] Step 101: Slice the copper grid silicon heterojunction cell to obtain multiple cell slices.

[0038] Optionally, the copper grid silicon heterojunction solar cell can be sliced ​​using a combination of laser scribing and mechanical dicing or laser thermal stress dicing to obtain multiple independent copper grid silicon heterojunction solar cell slices, wherein each copper grid silicon heterojunction solar cell slice has at least one cut surface.

[0039] Step 102 involves transferring the battery stack, formed by stacking multiple battery cells, into a chemical vapor deposition apparatus.

[0040] In this embodiment of the disclosure, when stacking multiple battery wafers to form a battery stack, each battery wafer in the stack is placed in the same orientation, that is, the front and back sides of each battery wafer in the stack are the same. Furthermore, a waste silicon wafer or waste battery of the same size as the battery wafer is placed on both the exposed front and back sides of the battery in the stack as a supporting wafer. This reduces the gaps between the battery wafers and prevents intrinsic amorphous silicon from being deposited onto the front and back sides of the battery wafers through gaps during subsequent deposition of intrinsic amorphous silicon thin films on the cut edges of the battery wafers, thus avoiding any impact on the subsequent component soldering.

[0041] Optionally, the chemical vapor deposition apparatus may be any of the following: a plasma-enhanced chemical vapor deposition (PECVD) apparatus, or a hot-wire chemical vapor deposition (HWCVD) apparatus. This disclosure does not limit it in this regard.

[0042] Step 103: Within a preset time period, hydrogen gas is introduced into the chemical vapor deposition equipment, wherein the initial hydrogen gas flow rate is 5000-25000 sccm. This process can effectively pre-clean the edges of the battery slices, improving the passivation effect of subsequent intrinsic amorphous silicon thin films.

[0043] The preset time period can be the time for injecting hydrogen into the chemical vapor deposition equipment. Optionally, the preset time period can be 5-20 seconds, such as 5 seconds, 10 seconds, 20 seconds, etc. This disclosure does not limit it.

[0044] The first hydrogen flow rate can be the flow rate of hydrogen injected into the chemical vapor deposition apparatus before depositing an intrinsic amorphous silicon thin film at the edge of the slice of each cell segment in the battery stack. For example, the first hydrogen flow rate can be 5000 sccm, 10000 sccm, 15000 sccm, 25000 sccm, etc. This disclosure does not limit it in this respect.

[0045] Optionally, if the chemical vapor deposition equipment is a plasma-enhanced chemical vapor deposition equipment, the power of the hydrogen injection process can be 15-160 mW / cm². Specifically, it can be 20 mW / cm², 50 mW / cm², 100 mW / cm², 160 mW / cm², etc. This disclosure does not limit it in this way.

[0046] In this embodiment of the present disclosure, after the battery stack is transferred to the chemical vapor deposition equipment, hydrogen gas can be introduced into the chemical vapor deposition equipment. This not only increases the concentration of hydrogen gas in the chemical vapor deposition equipment, but also provides a good pre-cleaning effect on the edge of the slice of the battery, which provides conditions for better deposition of intrinsic amorphous silicon thin film on the slice, thereby improving the passivation effect of the intrinsic amorphous silicon thin film.

[0047] Step 104: Deposit an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the cell stack to obtain edge-passivated cell segments, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C.

[0048] It should be noted that since copper-grid silicon heterojunction solar cells contain copper electrodes, excessively high process temperatures may damage the structure and performance of the copper electrodes, thus affecting the performance of the solar cell. In this embodiment, the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C, thereby avoiding damage to the copper electrodes due to excessive temperature. Furthermore, it achieves the deposition of intrinsic amorphous silicon thin films at the edges of the slices in each copper-grid silicon heterojunction solar cell slab, thereby improving the conversion efficiency of the copper-grid silicon heterojunction solar cell.

[0049] Among them, the edge-passivated battery slab can be a battery slab with an intrinsic amorphous silicon thin film at the cross-section of the slice.

[0050] The deposition temperature is 80-120℃, more preferably 100-120℃, and can specifically be 105℃, 110℃, 115℃, etc. This disclosure does not limit it.

[0051] Optionally, the thickness of the intrinsic amorphous silicon thin film can be 5-30 nm. It is understood that a good passivation effect can be achieved when the thickness of the intrinsic amorphous silicon thin film deposited at the edge of the cell wafer slice reaches a preset thickness. Therefore, the deposition of intrinsic amorphous silicon at the edge of the cell wafer slice can be stopped once the preset thickness is reached, thereby improving the efficiency of depositing intrinsic amorphous silicon thin films at the edge of each cell wafer slice while ensuring passivation.

[0052] Optionally, if the chemical vapor deposition equipment is a plasma-enhanced chemical vapor deposition equipment, the deposition power of intrinsic amorphous silicon thin films is 15-60 milliwatts per square centimeter (mW / cm²). 2 The ratio between the second hydrogen flow rate and the silane flow rate is 0.3-10.

[0053] The second hydrogen flow rate can be the flow rate of hydrogen injected during the deposition of an intrinsic amorphous silicon thin film at the edge of the slice cross-section of each battery segment. Optionally, the first hydrogen flow rate can be the same as or different from the second hydrogen flow rate. This disclosure does not limit this.

[0054] Optionally, if the chemical vapor deposition equipment is a hot-wire chemical vapor deposition equipment, the hot-wire temperature can be 1600-2100℃ during the formation of an intrinsic amorphous silicon thin film at the edge of the slice cross-section of each cell segment in the battery stack. For example, 1700℃, 1800℃, 1900℃, 2000℃, etc., and this disclosure does not limit it.

[0055] It should be noted that during the deposition of intrinsic amorphous silicon thin films at the cut surfaces of the battery cells in a battery stack, it is necessary to ensure that the battery stack is in the same chemical vapor deposition (PECVD) equipment. For example, after transferring a battery stack formed by stacking multiple battery cells to a PECVD equipment, hydrogen gas is introduced into the PECVD equipment, and the battery stack is kept in the same PECVD equipment, and intrinsic amorphous silicon thin films are deposited at the cut surfaces of the battery cells.

[0056] In this embodiment, the copper-grid silicon heterojunction solar cell is first sliced ​​to obtain multiple cell wafers. Then, a stack of these wafers is transferred to a chemical vapor deposition (CVD) apparatus. Hydrogen gas is introduced into the CVD apparatus within a preset time period, with a flow rate of 5000-25000 sccm. Finally, an intrinsic amorphous silicon thin film is deposited at the slice cross-section of each cell wafer in the stack to obtain edge-passivated cell wafers. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. This allows for passivation treatment of the slice cross-sections of the copper-grid silicon heterojunction solar cell wafers at low temperatures. This ensures that the copper-grid silicon heterojunction solar cell wafers and copper electrodes are not affected, while reducing the carrier recombination rate at the slice cross-sections, improving the passivation effect, effectively compensating for recombination losses caused by slicing, and improving the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

[0057] Figure 2 This is a schematic flowchart of an edge passivation method for a copper grid silicon heterojunction solar cell provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the edge passivation method for this copper grid silicon heterojunction cell may include the following steps:

[0058] Step 201: Slice the copper grid silicon heterojunction cell to obtain multiple cell slices.

[0059] Step 202 involves transferring the battery stack, formed by stacking multiple battery cells, into a chemical vapor deposition apparatus.

[0060] Step 203: During a preset time period, hydrogen gas is introduced into the chemical vapor deposition equipment, wherein the first hydrogen gas flow rate is 5000-25000 sccm.

[0061] Step 204: Deposit an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the cell stack to obtain edge-passivated cell segments, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C.

[0062] The specific implementation of steps 201 to 204 can be found in the detailed steps of other embodiments in this disclosure, and will not be described in detail here.

[0063] Step 205: Apply light treatment to the cross-section of the battery slice with passivated edges, wherein the heating temperature of the light treatment does not exceed 120°C.

[0064] In this embodiment of the present disclosure, after depositing an intrinsic amorphous silicon thin film at the cross-section of each battery segment in the battery stack, the intrinsic amorphous silicon thin film formed at the cross-section of the battery segment can be further illuminated to further improve the passivation effect.

[0065] Optionally, to avoid the cell temperature rising under illumination and adversely affecting the slab formation of copper grid silicon heterojunction cells, the illumination temperature can be set to 5-20 seconds. This can enhance the passivation effect while avoiding the adverse effects of excessively high illumination temperature or excessively long illumination time on the slab formation of copper grid silicon heterojunction cells.

[0066] Optionally, each target battery segment can be illuminated separately, or each target battery segment in the entire battery stack can be illuminated as a whole; this disclosure does not limit this.

[0067] In this embodiment, the copper-grid silicon heterojunction solar cell is first sliced ​​to obtain multiple cell wafers. Then, a stack of these wafers is transferred to a chemical vapor deposition (CVD) apparatus. Hydrogen gas is introduced into the CVD apparatus within a preset time period, with a flow rate of 5000-25000 sccm. Next, an intrinsic amorphous silicon thin film is deposited at the sliced ​​edge of each cell wafer in the stack to obtain edge-passivated wafers. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. Finally, the sliced ​​edge of the passivated wafers is photo-treated, with the photo-treatment temperature not exceeding 120°C. Thus, after the intrinsic amorphous silicon thin film is deposited at the edge of the sliced ​​edge of each cell wafer in the stack, the formed intrinsic amorphous silicon thin film is further photo-treated, thereby further improving the passivation effect and consequently improving the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

[0068] To achieve the above embodiments, this disclosure also proposes an edge passivation device for copper grid silicon heterojunction solar cells.

[0069] Figure 3 This is a schematic diagram of the edge passivation device for a copper grid silicon heterojunction cell provided in an embodiment of this disclosure.

[0070] like Figure 3 As shown, the edge passivation device 300 of the copper grid silicon heterojunction solar cell may include: a slicing module 310, a transfer module 320, a hydrogen injection module 330, and a thin film deposition module 340.

[0071] The slicing module 310 is used to slice the copper grid silicon heterojunction cell to obtain multiple cell slices.

[0072] The transfer module 320 is used to transfer a battery stack formed by stacking multiple battery cells to a chemical vapor deposition equipment;

[0073] The hydrogen injection module 330 is used to inject hydrogen into the chemical vapor deposition equipment within a preset time period, wherein the first hydrogen flow rate is 5000-25000 sccm.

[0074] Thin film deposition module 340 is used to deposit an intrinsic amorphous silicon thin film at the cut edge of each cell wafer in the battery stack to obtain the target cell wafer, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C.

[0075] Optional, also includes:

[0076] The post-processing module is used to perform photo-irradiation on the intrinsic amorphous silicon thin film at the edge of the slice section of the target battery, wherein the irradiation temperature does not exceed 120°C.

[0077] The functions and specific implementation principles of the modules described in this embodiment can be found in the above method embodiments, and will not be repeated here.

[0078] The edge passivation apparatus for copper-grid silicon heterojunction solar cells in this embodiment first slices the copper-grid silicon heterojunction solar cell to obtain multiple cell wafers. Then, a stack of cell wafers is transferred to a chemical vapor deposition (CVD) apparatus. Hydrogen gas is introduced into the CVD apparatus within a preset time period, with a first hydrogen flow rate of 5000-25000 sccm. Finally, an intrinsic amorphous silicon thin film is deposited at the slice cross-section of each cell wafer in the stack to obtain edge-passivated cell wafers. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. Therefore, the edge passivation treatment of the slice cross-section of the copper-grid silicon heterojunction solar cell wafers can be performed at low temperatures. This ensures that the copper-grid silicon heterojunction solar cell wafers and copper electrodes are not affected, while reducing the carrier recombination rate at the slice cross-section of the copper-grid silicon heterojunction solar cell wafers, improving the passivation effect, effectively compensating for recombination losses caused by slicing, and improving the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

[0079] To achieve the above embodiments, this disclosure also proposes a copper grid silicon heterojunction cell, comprising: a copper grid silicon heterojunction cell manufactured according to the edge passivation method of the copper grid silicon heterojunction cell proposed in the above embodiments, wherein the cross-section of the copper grid silicon heterojunction cell is subjected to hydrogen implantation treatment and a layer of intrinsic amorphous silicon thin film is deposited.

[0080] Figure 4 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present disclosure is shown. Figure 4 The electronic device 12 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0081] like Figure 4As shown, the electronic device 12 is represented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0082] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0083] Computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0084] Memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 4 Not shown; usually referred to as a "hard drive"). Although Figure 4Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc (e.g., a compact disc read-only memory (CD-ROM), a digital video disc read-only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this disclosure.

[0085] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of this disclosure.

[0086] Computer device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with computer device 12, and / or with any device that enables computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 22. Furthermore, computer device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of computer device 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0087] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the methods mentioned in the foregoing embodiments.

[0088] The technical solution disclosed herein first slices a copper-grid silicon heterojunction solar cell to obtain multiple cell wafers. Then, a stack of these wafers is transferred to a chemical vapor deposition (CVD) apparatus. Hydrogen gas is introduced into the CVD apparatus within a preset time period, with a flow rate of 5000-25000 sccm. Finally, an intrinsic amorphous silicon thin film is deposited at the slice cross-section of each cell wafer in the stack to obtain edge-passivated cell wafers. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C. This allows for passivation treatment of the slice cross-sections of the copper-grid silicon heterojunction solar cell wafers at low temperatures. This ensures that the copper-grid silicon heterojunction solar cell wafers and copper electrodes are not affected, while reducing the carrier recombination rate at the slice cross-sections, improving the passivation effect, effectively compensating for recombination losses caused by slicing, and increasing the efficiency of the sliced ​​copper-grid silicon heterojunction solar cell.

[0089] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0090] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0091] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0092] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0093] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0094] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0095] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0096] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A method for edge passivation of a copper grid silicon heterojunction solar cell, characterized in that, include: The copper grid silicon heterojunction solar cell is sliced ​​to obtain multiple cell slices; The battery stack, formed by stacking multiple battery cells, is transferred to a chemical vapor deposition apparatus; Hydrogen gas is introduced into the chemical vapor deposition equipment within a preset time period, wherein the first hydrogen gas flow rate is 5000-25000 sccm; An intrinsic amorphous silicon thin film is deposited at the cross-section of each battery segment in the battery stack to obtain a battery segment with passivated edges. The deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C to avoid damage to the copper electrode. After obtaining the edge-passivated battery slices, the process further includes: The cross-section of the battery slice with blunted edges is subjected to light irradiation treatment, wherein the heating temperature of the light irradiation treatment does not exceed 120°C.

2. The method according to claim 1, characterized in that, The thickness of the intrinsic amorphous silicon thin film is 5-30 nm.

3. The method according to any one of claims 1-2, characterized in that, The chemical vapor deposition equipment is any one of the following: plasma-enhanced chemical vapor deposition equipment, or hot-wire chemical vapor deposition equipment.

4. The method according to claim 3, characterized in that, When the chemical vapor deposition equipment is a plasma-enhanced chemical vapor deposition equipment, during the deposition of an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the battery stack, the deposition power of the intrinsic amorphous silicon thin film is 15-60 mW / cm², and the ratio between the second hydrogen flow rate and the silane flow rate is 0.3-10.

5. The method according to claim 3, characterized in that, When the chemical vapor deposition equipment is a hot-wire chemical vapor deposition equipment, the hot-wire temperature is 1600-2100°C during the deposition of an intrinsic amorphous silicon thin film at the cross-section of each cell segment in the battery stack.

6. An edge passivation device for a copper grid silicon heterojunction solar cell, characterized in that, include: The slicing module is used to slice copper grid silicon heterojunction solar cells to obtain multiple cell slices; A transfer module is used to transfer a battery stack formed by stacking multiple battery wafers to a chemical vapor deposition apparatus; The hydrogen injection module is used to introduce hydrogen into the chemical vapor deposition equipment within a preset time period, wherein the first hydrogen flow rate is 5000-25000 sccm. A thin film deposition module is used to deposit an intrinsic amorphous silicon thin film at the cross-section of each battery segment in the battery stack to obtain edge passivated battery segments, wherein the deposition temperature of the intrinsic amorphous silicon thin film is 80-120°C to avoid damage to the copper electrode. The post-processing module is used to perform light irradiation on the cross-section of the edge-passivated battery slice, wherein the heating temperature of the light irradiation process does not exceed 120°C.

7. A copper grid silicon heterojunction solar cell manufactured using the edge passivation method for copper grid silicon solar cells according to any one of claims 1-5, characterized in that, The cross-section of the copper grid silicon heterojunction cell is subjected to hydrogen implantation and has an intrinsic amorphous silicon thin film deposited on it.

Images