Semiconductor package and method of manufacturing a semiconductor package

Abstract

A semiconductor package and a method of manufacturing a semiconductor package are disclosed. The semiconductor package includes a printed circuit board, a semiconductor device, a first signal wire and a first ground wire. The printed circuit board includes a first printed circuit board ground pad and a first printed circuit board signal trace. The semiconductor device includes a first device ground pad and a first device signal pad. The first signal wire is coupled between the first device signal pad and the first printed circuit board signal trace. The first ground wire is coupled between the first device ground pad and the first printed circuit board ground pad, wherein the first ground wire crosses the first signal wire.

Description

Technical Field

[0001] This invention relates to crosstalk reduction technology, and more particularly to a semiconductor package and related methods having a ground bonding wire crossing a signal bonding wire to provide crosstalk reduction. Background Technology

[0002] Vertical-emitting optical devices, such as vertical-cavity surface-emitting lasers (VCSELs), are laser beams emitted perpendicular to the surface of a substrate. A VCSEL array can provide multiple emission sources on a single chip to emit a single beam or multiple independent beams. For the packaging of VCSEL arrays, wire bonding is typically used to connect the anode pad and cathode pad of each VCSEL to the signal trace and ground pad on a printed circuit board (PCB), respectively. When a driverless optical module is implemented using a vertical-cavity surface-emitting laser (VCSEL) array, electromagnetic interference (EMI) caused by the signal passing through the signal line of one VCSEL in the array can couple to the signal line of another VCSEL in the same array. This increases the crosstalk interference of the driverless optical module and degrades system performance. Therefore, an innovative semiconductor package (e.g., an optical package) with crosstalk suppression design is needed. Summary of the Invention

[0003] One of the objectives of this invention is to provide a semiconductor package and related methods with a grounding wire crossing a signal wire to provide crosstalk interference suppression.

[0004] In one embodiment of the present invention, a semiconductor package is disclosed. The semiconductor package includes a printed circuit board, a semiconductor device, a first signal bonding wire, and a first ground bonding wire. The printed circuit board includes a first printed circuit board ground pad and a first printed circuit board signal trace. The semiconductor device includes a first device ground pad and a first device signal pad. The first signal bonding wire is coupled between the first device signal pad and the first printed circuit board signal trace. The first ground bonding wire is coupled between the first device ground pad and the first printed circuit board ground pad, wherein the first ground bonding wire crosses the first signal bonding wire.

[0005] In one embodiment of the present invention, a method for manufacturing a semiconductor package is disclosed. The method includes: mounting a semiconductor device onto a printed circuit board, wherein the printed circuit board includes a first printed circuit board ground pad and a first printed circuit board signal trace, and the semiconductor device includes a first device ground pad and a first device signal pad; and performing a wire bonding process, including: coupling a first signal wire bond between the first device signal pad and the first printed circuit board signal trace, and coupling a first ground wire bond between the first device ground pad and the first printed circuit board ground pad, wherein the first ground wire bond crosses the first signal wire bond.

[0006] The crosstalk suppression design proposed in this invention uses an additional grounding wire to cross the signal wire, which not only provides an additional return path but also provides additional electromagnetic interference shielding. In this way, the crosstalk level of the semiconductor package can be effectively reduced. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a semiconductor package with the proposed crosstalk suppression design according to an embodiment of the present invention;

[0008] Figure 2 for Figure 1 The diagram shows a crosstalk suppression design used in the semiconductor package.

[0009] Figure 3 For can be Figure 1 The diagram shows a first design variation of the crosstalk suppression design used in the semiconductor package.

[0010] Figure 4 For can be Figure 1 The diagram shows a second design variation of the crosstalk suppression design used in the semiconductor package.

[0011] Figure 5 For can be Figure 1 The diagram shows a third design variation of the crosstalk suppression design used in the semiconductor package.

[0012] Figure 6 For can be Figure 1 This diagram illustrates the fourth design variation of the crosstalk suppression design used in the semiconductor package.

[0013] Symbol Explanation

[0014] 100: Semiconductor Packaging

[0015] 102: Printed Circuit Board

[0016] 104: Semiconductor Devices

[0017] 105_0, 105_1, 105_2, 105_3: Semiconductor components

[0018] 106: Digital Signal Processor

[0019] 108_0, 108_1, 108_2, 108_3: Printed circuit board signal traces

[0020] 110_0,110_1,110_2,110_3,112_0,112_1,112_2,112_3: Printed circuit board grounding pads

[0021] 114_0, 114_1, 114_2, 114_3: Signal wire bonding

[0022] 116_0, 116_1, 116_2, 116_3: Grounding wire

[0023] 118_0, 118_1, 118_2, 118_3: Additional grounding wires

[0024] 202, 204, 602: Common ground plane

[0025] TX0, TX1, TX2, TX3: Output ports

[0026] SIG_0, SIG_1, SIG_2, SIG_3: Device signal pads

[0027] GND_0, GND_1, GND_2, GND_3: Device grounding pads Detailed Implementation

[0028] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0029] Figure 1 This is a schematic diagram of a semiconductor package with the proposed crosstalk suppression design according to an embodiment of the present invention. The semiconductor package 100 includes a printed circuit board 102, a semiconductor device 104, and a digital signal processor (DSP) 106. The semiconductor device 104 is mounted on the printed circuit board 102 and includes a plurality of semiconductor elements 105_0, 105_1, 105_2, and 105_3. In some embodiments of the present invention, the semiconductor device 104 may be an optical device; for example, the semiconductor device 104 may be a vertical-cavity surface-emitting laser array, wherein each of the semiconductor elements 105_0, 105_1, 105_2, and 105_3 is a vertical-cavity surface-emitting laser. The digital signal processor 106 is mounted on the printed circuit board 102 and is used to drive the semiconductor device 104, such as... Figure 1 As shown, the digital signal processor 106 has multiple output ports TX0, TX1, TX2, and TX3, which are respectively connected to multiple printed circuit board signal traces 108_0, 108_1, 108_2, and 108_3. In this embodiment, the semiconductor device 104 can be a device without a driving circuit, such as an optical device without a driving circuit using a vertical cavity surface-emitting laser. Therefore, the semiconductor device 104 is directly driven by the digital signal processor 106 without any additional driving circuit located between the digital signal processor 106 and the semiconductor device 104. However, this is only for illustrative purposes and is not intended to limit the invention. In practice, any semiconductor package that adopts the crosstalk suppression design proposed in this invention falls within the scope of this invention.

[0030] like Figure 1As shown, each of the semiconductor elements 105_0 to 105_3 has a device signal pad SIG_0 / SIG_1 / SIG_2 / SIG_3 and a device ground pad GND_0 / GND_1 / GND_2 / GND_3. Since semiconductor device 104 is a device without a driving circuit in this embodiment, the device signal pad (e.g., anode pad) SIG_0 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_0 is electrically connected to the printed circuit board signal trace 108_0 via signal bonding wire 114_0; the device signal pad (e.g., anode pad) SIG_1 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_1 is electrically connected to the printed circuit board signal trace 108_1 via signal bonding wire 114_1; the device signal pad (e.g., anode pad) SIG_2 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_2 is electrically connected to the printed circuit board signal trace 108_2 via signal bonding wire 114_2; and the device signal pad (e.g., anode pad) SIG_3 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_3 is electrically connected to the printed circuit board signal trace 108_2 via signal bonding wire 114_3. The device ground pad (e.g., cathode pad) GND_0 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_0 is electrically connected to the printed circuit board ground pad 110_0 via grounding wire 116_0. The device ground pad (e.g., cathode pad) GND_1 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_1 is electrically connected to the printed circuit board ground pad 110_1 via grounding wire 116_1. The device ground pad (e.g., cathode pad) GND_2 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_2 is electrically connected to the printed circuit board ground pad 110_2 via grounding wire 116_2. The device ground pad (e.g., cathode pad) GND_3 of semiconductor element (e.g., vertical cavity surface-emitting laser) 105_3 is electrically connected to the printed circuit board ground pad 110_3 via grounding wire 116_3. In short, the manufacturing process of semiconductor package 100 includes mounting semiconductor device 104 onto printed circuit board 102 and performing wire bonding process to form signal wires and ground wires between semiconductor device 104 and printed circuit board 102.

[0031] Furthermore, since semiconductor device 104 in this embodiment is a device without a driving circuit, the driving signal passing through the signal bonding wire of one semiconductor element is easily affected by electromagnetic interference caused by the driving signal passing through the signal bonding wire of another semiconductor element. To solve this crosstalk interference problem, this invention proposes a crosstalk interference suppression design, which can be adopted by a semiconductor package to effectively reduce the degree of crosstalk interference. According to the crosstalk interference suppression design proposed by this invention, a grounding wire (coupled between a device ground pad (e.g., a cathode pad of a vertical cavity surface-emitting laser) and a printed circuit board ground pad) is formed by a wire bonding process and configured as a crossover. A signal bonding wire (coupled between a device signal pad (e.g., an anode pad of a vertical cavity surface-emitting laser)) and a printed circuit board ground trace) is used. In this embodiment, an additional ground bonding wire 118_0 is coupled between the device ground pad GND_0 of semiconductor element 105_0 and a printed circuit board ground pad 112_0, and crosses signal bonding wire 114_0 (coupled between the device signal pad SIG_0 of semiconductor element 105_0 and printed circuit board trace 108_0); an additional ground bonding wire 118_1 is coupled between the device ground pad GND_1 of semiconductor element 105_1 and a printed circuit board ground pad 112_1, and crosses signal bonding wire 114_1 (coupled between the device signal pad SIG_0 of semiconductor element 105_0 and printed circuit board trace 108_0); an additional ground bonding wire 118_1 is coupled between the device ground pad GND_1 of semiconductor element 105_1 and a printed circuit board ground pad 112_1, and crosses signal bonding wire 114_1 (coupled between the device signal pad SIG_0 of semiconductor element 105_0 and printed circuit board trace 108_0). The additional grounding wire 118_2 is coupled between the device signal pad SIG_1 of semiconductor element 105_2 and a printed circuit board ground pad 112_2, and crosses the signal wire 114_2 (which is coupled between the device signal pad SIG_2 of semiconductor element 105_2 and the printed circuit board trace 108_2); and the additional grounding wire 118_3 is coupled between the device ground pad GND_3 of semiconductor element 105_3 and a printed circuit board ground pad 112_3, and crosses the signal wire 114_3 (which is coupled between the device signal pad SIG_3 of semiconductor element 105_3 and the printed circuit board trace 108_3). Each of the additional grounding wires 118_0 to 118_3 can provide an additional return path and additional electromagnetic interference shielding. With the help of the additional grounding wires 118_0 to 118_3 that cross the signal wires 114_0 to 114_3 respectively, the crosstalk interference of the semiconductor package 100 can be effectively reduced.

[0032] Please refer to this as well. Figure 1 as well as Figure 2 , Figure 2 for Figure 1This diagram illustrates the crosstalk suppression design employed in the semiconductor package 100. An additional ground wire 118_0 crosses signal wire 114_0, and an additional ground wire 118_1 crosses signal wire 114_1, thereby reducing crosstalk interference between the drive signal passing through signal wire 114_0 and the drive signal passing through signal wire 114_1. An additional ground wire 118_1 crosses signal wire 114_1, and an additional ground wire 118_2 crosses signal wire 114_2, thereby reducing crosstalk interference between the drive signal passing through signal wire 114_1 and the drive signal passing through signal wire 114_2. An additional ground wire 118_2 crosses signal wire 114_2, and an additional ground wire 118_3 crosses signal wire 114_3, thereby reducing crosstalk interference between the drive signal passing through signal wire 114_2 and the drive signal passing through signal wire 114_3.

[0033] Furthermore, the device grounding pads GND_0 to GND_3 are all connected to the common ground plane 202 on the semiconductor device (e.g., a vertical-cavity surface-emitting laser array) 104, and the printed circuit board grounding pads 110_1 to 110_3 and 112_0 to 112_3 are all connected to the common ground plane 204 on the printed circuit board 102. In this embodiment, when the semiconductor device 104 is mounted on the printed circuit board 102, the common ground plane 202 of the semiconductor device 104 will have physical contact with the common ground plane 204 on the printed circuit board 102.

[0034] Figure 1 and Figure 2 The crosstalk suppression design shown is for illustrative purposes only and is not intended to limit the invention. Any crosstalk suppression design that uses a grounding wire coupled between the device ground pad and the printed circuit board ground pad and spans the signal wire between the device signal pad and the printed circuit board signal trace falls within the scope of this invention.

[0035] Please refer to this as well. Figure 1 as well as Figure 3 , Figure 3 For can be Figure 1 This is a schematic diagram of the first design variation of the crosstalk suppression design used in the semiconductor package 100 shown. Figure 2 and Figure 3 The main difference between the crosstalk suppression designs shown is that Figure 3 The crosstalk suppression design shown omits Figure 2 The extra grounding wires 118_1 and 118_3 are shown in the crosstalk suppression design.

[0036] Please refer to this as well. Figure 1 as well as Figure 4 , Figure 4 For can be Figure 1 A schematic diagram of a second design variation of the crosstalk suppression design used in the semiconductor package 100 shown. Figure 2 and Figure 4 The main difference between the crosstalk suppression designs shown is that Figure 4 The crosstalk suppression design shown omits Figure 2 The extra grounding wires 118_1 to 118_3 are shown in the crosstalk suppression design.

[0037] Please refer to this as well. Figure 1 as well as Figure 5 , Figure 5 For can be Figure 1 This is a schematic diagram of a third design variation of the crosstalk suppression design used in the semiconductor package 100 shown. Figure 2 and Figure 5 The main difference between the crosstalk suppression designs shown is that Figure 5 The crosstalk suppression design shown omits Figure 2 The grounding wires 116_0 to 116_3 in the crosstalk suppression design shown do not cross a signal wire (which is coupled between a device signal pad (e.g., an anode pad of a vertical-cavity surface-emitting laser) and a printed circuit board signal trace). Compared to Figure 5 The crosstalk suppression design shown is as follows: Figure 2 The crosstalk suppression design shown has better crosstalk suppression performance because it has a larger number of grounding wires to provide return current paths and electromagnetic interference shielding.

[0038] Please refer to this as well. Figure 1 as well as Figure 6 , Figure 6 For can be Figure 1 This is a schematic diagram of the fourth design variation of the crosstalk suppression design used in the semiconductor package 100 shown. Figure 2 and Figure 6 The main difference between the crosstalk suppression designs shown is that Figure 6The crosstalk suppression design shown has two common ground planes that do not physically contact each other. Specifically, device ground pads GND_0 to GND_3 are connected to a common ground plane 602 on the semiconductor device (e.g., a vertical-cavity surface-emitting laser array) 104. Printed circuit board ground pads 110_0 to 110_3 and 112_0 to 112_3 are connected to a common ground plane 104 on the printed circuit board 102. In this embodiment, when the semiconductor device 104 is mounted on the printed circuit board 102, the common ground plane 602 of the semiconductor device 104 does not make physical contact with the common ground plane 204 on the printed circuit board 102.

[0039] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor package comprising: A printed circuit board, comprising a first printed circuit board ground pad and a first printed circuit board signal trace; A semiconductor device, comprising a first device ground pad and a first device signal pad; A first signal wire is bonded between the first device signal pad and the first printed circuit board signal trace; and A first grounding wire is coupled between the grounding pad of the first device and the grounding pad of the first printed circuit board, wherein the first grounding wire crosses the first signal wire.

2. The semiconductor package of claim 1, wherein the printed circuit board further comprises a second printed circuit board ground pad, and the semiconductor package further comprises: The second grounding wire is coupled between the grounding pad of the first device and the grounding pad of the second printed circuit board.

3. The semiconductor package of claim 1, wherein the semiconductor device comprises a plurality of semiconductor elements, and both the first device ground pad and the first device signal pad are semiconductor elements among the plurality of semiconductor elements.

4. The semiconductor package of claim 1, wherein the printed circuit board further includes a second printed circuit board ground pad and a second printed circuit board signal trace; the semiconductor device further includes a second device ground pad and a second device signal pad; and the semiconductor package further includes: A second signal wire is coupled between the second device signal pad and the second printed circuit board signal trace; and The second grounding wire is coupled between the grounding pad of the second device and the grounding pad of the second printed circuit board, wherein the second grounding wire crosses the second signal wire.

5. The semiconductor package of claim 4, wherein the printed circuit board further comprises a third printed circuit board ground pad and a fourth printed circuit board ground pad, and the semiconductor package further comprises: The third grounding wire is coupled between the grounding pad of the first device and the grounding pad of the third printed circuit board; and The fourth grounding wire is coupled between the grounding pad of the second device and the grounding pad of the fourth printed circuit board.

6. The semiconductor package of claim 4, wherein the semiconductor device comprises a plurality of semiconductor elements, the first device ground pad and the first device signal pad are both semiconductor elements among the plurality of semiconductor elements, and the second device ground pad and the second device signal pad are both semiconductor elements among the plurality of semiconductor elements.

7. The semiconductor package of claim 4, wherein the first printed circuit board ground pad and the second printed circuit board ground pad are both connected to the same ground plane on the printed circuit board.

8. The semiconductor package of claim 1, wherein the first printed circuit board ground pad is connected to the ground plane of the printed circuit board, the first device ground pad is connected to the ground plane of the semiconductor device, and the ground plane of the printed circuit board is in physical contact with the ground plane of the semiconductor device.

9. The semiconductor package of claim 1, wherein the first printed circuit board ground pad is connected to the ground plane of the printed circuit board, the first device ground pad is connected to the ground plane of the semiconductor device, and the ground plane of the printed circuit board is not in physical contact with the ground plane of the semiconductor device.

10. The semiconductor package of claim 1, wherein the semiconductor device is an optical device.

11. The semiconductor package of claim 10, wherein the optical device is a vertical cavity surface-emitting laser device, the first device signal pad is an anode pad, and the first device ground pad is a cathode pad.

12. The semiconductor package of claim 10, wherein the optical device is an optical device without a driving circuit.

13. A method for manufacturing a semiconductor package, comprising: A semiconductor device is mounted onto a printed circuit board, wherein the printed circuit board includes a first printed circuit board ground pad and a first printed circuit board signal trace, and the semiconductor device includes a first device ground pad and a first device signal pad; and The wire bonding process includes: The first signal is wire-coupled between the first device signal pad and the first printed circuit board signal trace; and A first grounding wire is coupled between the first device ground pad and the first printed circuit board ground pad, wherein the first grounding wire crosses the first signal wire.

14. The method of claim 13, wherein the printed circuit board further comprises a second printed circuit board ground pad, and the step of performing the wire bonding fabrication process further comprises: The second grounding wire is coupled between the grounding pad of the first device and the grounding pad of the second printed circuit board.

15. The method of claim 13, wherein the semiconductor device comprises a plurality of semiconductor elements, and both the first device ground pad and the first device signal pad are semiconductor elements among the plurality of semiconductor elements.

16. The method of claim 13, wherein the first printed circuit board ground pad is connected to the ground plane of the printed circuit board, the first device ground pad is connected to the ground plane of the semiconductor device, and the ground plane of the printed circuit board is in physical contact with the ground plane of the semiconductor device.

17. The method of claim 13, wherein the first printed circuit board ground pad is connected to the ground plane of the printed circuit board, the first device ground pad is connected to the ground plane of the semiconductor device, and the ground plane of the printed circuit board is not in physical contact with the ground plane of the semiconductor device.

18. The method of claim 13, wherein the semiconductor device is an optical device.

19. The method of claim 18, wherein the optical device is a vertical cavity surface-emitting laser device, the first device signal pad is an anode pad, and the first device grounding pad is a cathode pad.

20. The method of claim 18, wherein the optical device is an optical device without a driving circuit.

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