Switching converter and control circuit therefor

Abstract

The application discloses a switching converter and a control circuit thereof. The control circuit comprises an error amplifier circuit, a comparator for generating a pulse width modulation signal according to an error amplified signal and a second feedback voltage of an output voltage, and a logic circuit for controlling the turn-on and turn-off of high-side and low-side switching tubes of the switching converter according to the pulse width modulation signal. The error amplifier circuit comprises an error amplifier for comparing a first voltage signal with a reference voltage to output the error amplified signal, an inner loop gain analog circuit for obtaining an analog voltage signal in a set proportion to the output of the error amplifier, and a signal selection circuit for selecting one of a first feedback voltage of the output voltage and the analog voltage signal as the first voltage signal according to a flag signal of a DCM mode of the switching converter, thereby improving the transient response speed of the switching converter and reducing the under-voltage value of the output voltage of the switching converter.

Description

Technical Field

[0001] This invention relates to the field of power supply circuit technology, and in particular to a switching converter and its control circuit. Background Technology

[0002] Switching converters are currently the most widely used type of switching power supply on the market. They generally employ control methods such as voltage control, current control, and hysteresis control. Constant-on-time (COT) control is developed based on hysteresis control. In existing COT-controlled Buck converters operating in DCM (Discontinuous Current Mode), the switching frequency fsw is proportional to the load current Io. As the load current Io decreases, the switching frequency fsw falls below the bandwidth of the voltage outer loop. At this point, the voltage outer loop operates in open-loop mode, and the internal node voltage of the error amplifier and the error amplification signal it provides are uncontrolled. Therefore, when the load changes from light to heavy, the error amplifier needs a long time to recover to normal, causing the Buck converter's output voltage to drop significantly before it initiates a new switching action. This results in a poor transient response of the Buck converter, and the output voltage accuracy cannot meet the load requirements.

[0003] Figure 1 A circuit diagram of a prior art COT-controlled switching converter is shown. See also Figure 1 The switching converter employs a Buck topology and has input and output terminals, receiving the input voltage Vin and providing the output voltage Vout, respectively. The control circuit of the switching converter generates control signals HG and LG for the high-side switch M1 and the low-side switch M2. When the high-side switch M1 is on and the low-side switch M2 is off, the input terminal of the switching converter receives the input voltage Vin and charges the inductor L. When the high-side switch M1 is off and the low-side switch M2 is on, the inductor L discharges to the output terminal, thereby generating the output voltage Vout.

[0004] The control circuit of the switching converter has two voltage loops: an inner loop and an outer loop. The outer voltage loop is mainly driven by the error amplifier EA, which primarily stabilizes the output voltage Vout of the switching converter. The error amplifier EA undergoes frequency compensation through the compensation network 11. The inner voltage loop is mainly driven by the comparator 50. When the comparator 50 detects that the output voltage Vout is low, it turns on the high-side switch M1 of the switching converter and turns it off after a set on time. After a set minimum off time, if the comparator 50 detects that the output voltage Vout is low again, it will re-turn on the high-side switch M1. The inner voltage loop controls the set on time and minimum off time of the high-side switch M1 through the timing module 40.

[0005] When the switching converter operates in DCM mode, the slope compensation module 20 no longer functions. Comparator 50 directly compares the feedback voltage Vfb2 of the output voltage Vout with the magnitude of the error amplification signal Veao, and controls the high-side switch M1 to turn on when Vfb2 < Veao. As the load current Io decreases, the switching frequency fsw of the switching converter gradually decreases, eventually causing the feedback voltage Vfb1 to be higher than the reference voltage Vref for a long time within one switching cycle. This causes the error amplification signal Veao to discharge continuously and become very low. Thus, when the load current Io suddenly increases, due to the bandwidth limitation of the error amplifier EA, the error amplification signal Veao cannot recover to its normal value in a short time until the feedback voltage Vfb2 becomes very small, at which point the high-side switch M1 will turn on again. This results in a deterioration in the transient response of the switching converter, and the accuracy of the output voltage Vout cannot meet the load requirements.

[0006] Therefore, a new switching converter and its control circuit are needed to solve the above problems. Summary of the Invention

[0007] In view of the above problems, the purpose of this invention is to provide a switching converter and its control circuit, thereby improving the transient response speed of the switching converter and reducing the undervoltage value of the switching converter output voltage.

[0008] According to one aspect of the present invention, a control circuit for a switching converter is provided, the switching converter including a high-side switch and a low-side switch, the control circuit being used to control the on and off states of the high-side switch and the low-side switch to convert an input voltage of the switching converter into an output voltage, the control circuit including an error amplifier circuit for obtaining an amplified error signal between a first voltage signal related to the output voltage and a reference voltage; a comparator for generating a pulse width modulation signal based on the amplified error signal and a second feedback voltage of the output voltage; and a logic circuit for controlling the on and off states of the high-side switch and the low-side switch based on the pulse width modulation signal, wherein the error amplifier circuit includes an error amplifier, an inner-loop gain analog circuit, and a signal selection circuit; The error amplifier is used to compare the first voltage signal with the reference voltage to output the error amplification signal; the inner loop gain analog circuit is used to obtain an analog voltage signal that is proportional to the output of the error amplifier, and the analog voltage signal is used to characterize the first feedback voltage of the output voltage of the switching converter when it is stably operating in the inductor current continuous mode; the signal selection circuit is used to select one of the first feedback voltage of the output voltage and the analog voltage signal as the first voltage signal according to the DCM mode flag signal of the switching converter; wherein, when the signal selection circuit switches the first voltage signal from the first feedback voltage to the analog voltage signal, the error amplifier and the inner loop gain analog circuit form a voltage regulation loop.

[0009] Optionally, the signal selection circuit is used to select the first feedback voltage of the output voltage as the first voltage signal when the switching converter is operating in the continuous inductor current mode, and to select the analog voltage signal as the first voltage signal after the low-side switch is turned on and the switching converter has maintained the discontinuous inductor current mode for a preset time.

[0010] Optionally, the inner-loop gain analog circuit includes a first switch and a first resistor connected sequentially between the power supply voltage and the ground terminal; a second switch, a third switch, and a second resistor connected sequentially between the power supply voltage and the ground terminal; and a first operational amplifier, whose non-inverting input terminal receives the error amplification signal, whose inverting input terminal is connected to the common node of the third switch and the second resistor, and whose output terminal is connected to the control terminal of the third switch. The control terminals of the first and second switches are connected, the control terminal of the second switch is connected to its drain terminal, and the common node of the first switch and the first resistor provides the analog voltage signal.

[0011] Optionally, the set ratio is the ratio of the resistance values ​​of the first resistor to the second resistor.

[0012] Optionally, the signal selection circuit includes a first transmission gate and a second transmission gate controlled by an inverted first clock signal and a second clock signal, wherein when the first clock signal is high, the first transmission gate is off and the second transmission gate is on, and the second transmission gate outputs the analog voltage signal as the first voltage signal; when the first clock signal is low, the first transmission gate is on and the second transmission gate is off, and the first transmission gate outputs the first feedback voltage as the first voltage signal.

[0013] Optionally, the error amplifier circuit further includes a clock signal generation circuit for generating the first clock signal and the second clock signal according to the DCM mode flag signal, the first control signal, and the second control signal, wherein the DCM mode flag signal is used to characterize the operating state of the switching converter, the first control signal is used to control the on and off of the high-side switching transistor, and the second control signal is used to control the on and off of the low-side switching transistor.

[0014] Optionally, the clock signal generation circuit includes a trigger for generating a trigger signal based on the first control signal and the second control signal; a delay module for receiving the DCM mode flag signal and, after the DCM mode flag signal indicates that the switching converter has switched to the inductor current discontinuous mode, outputting the DCM mode flag signal after a preset delay; an AND gate, with its first input receiving the trigger signal, its second input receiving the trigger signal provided by the delay module, and its output providing the first clock signal; and an inverter, with its input receiving the first clock signal and its output providing the second clock signal.

[0015] Optionally, the trigger is configured to output a high-level trigger signal when the first control signal is low and the second control signal is high, and to output a low-level trigger signal when the first control signal is high and the second control signal is low; the DCM mode flag signal is low when the switching converter operates in continuous inductor current mode and high when the switching converter operates in discontinuous inductor current mode.

[0016] Optionally, the control circuit further includes a voltage clamping module for clamping the voltage value of the error amplification signal within a preset range; and a compensation network for performing frequency compensation on the error amplifier.

[0017] According to another aspect of the present invention, a switching converter is provided, including an input terminal and an output terminal, which respectively receive an input voltage and provide an input voltage; a high-side switch and a low-side switch connected in series between the input terminal and a ground terminal; an inductor connected between the intermediate node of the high-side switch and the low-side switch and the output terminal; and a control circuit as described above, for controlling the on and off of the high-side switch and the low-side switch to convert the input voltage of the switching converter into an output voltage.

[0018] The present invention provides a switching converter and its control circuit, comprising an error amplifier circuit for obtaining an error amplification signal between a first voltage signal and a reference voltage; a comparator for generating a pulse width modulation signal based on the error amplification signal and a second feedback voltage of the output voltage; and a logic circuit for controlling the on and off of a high-side switch and a low-side switch based on the pulse width modulation signal. The error amplifier circuit includes an error amplifier for comparing the first voltage signal with the reference voltage to output an error amplification signal; an inner-loop gain analog circuit for obtaining an analog voltage signal proportional to the output of the error amplifier; and a signal selection circuit for selecting one of the first feedback voltage and the analog voltage signal of the output voltage as the first voltage signal based on a DCM mode flag signal of the switching converter. This ensures that after the switching converter stabilizes in DCM mode, as long as the second feedback voltage of the output voltage drops to the value of the error amplification signal when the switching converter stabilizes in CCM mode, the high-side switch will turn on, causing the inductor current to rise, thereby improving the transient response speed of the switching converter and reducing the undervoltage value of the output voltage. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A circuit diagram of a COT-controlled switching converter in the prior art is shown;

[0021] Figure 2 A schematic diagram of a switching converter according to an embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram of an error amplifier circuit is shown.

[0023] Figure 4 It shows Figure 3 The timing diagram of the switching converter corresponding to the error amplifier circuit shown;

[0024] Figure 5 A schematic diagram of the error amplifier circuit of a switching converter according to an embodiment of the present invention is shown;

[0025] Figure 6 A schematic diagram of a clock signal generation circuit for a switching converter according to an embodiment of the present invention is shown;

[0026] Figure 7 A timing diagram of a switching converter according to an embodiment of the present invention is shown. Detailed Implementation

[0027] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0028] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0029] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.

[0030] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0031] Figure 2 A schematic diagram of a switching converter according to an embodiment of the present invention is shown.

[0032] See Figure 2 The switching converter uses a buck topology and is controlled by COT. The switching converter has input and output terminals, receiving the input voltage Vin and providing the output voltage Vout, respectively.

[0033] The switching converter includes a power circuit 1000 and a control circuit 2000. In the power circuit 1000, the high-side switch M1 and the low-side switch M2 are connected in series between the input terminal and the ground terminal of the switching converter. An inductor L is connected between the intermediate node of the high-side switch M1 and the low-side switch M2 and the output terminal. A resistor Resr and an output capacitor Cout are connected in series between the output terminal and the ground terminal. A resistor R is also connected between the output terminal and the ground terminal. Feedback resistors Rf1 and Rf2 are connected in series between the output terminal and the ground terminal. The feedback voltage Vfb1 for the output voltage Vout is obtained at the intermediate node of the feedback resistors Rf1 and Rf2. When the high-side switch M1 is on and the low-side switch M2 is off, the input terminal of the switching converter receives the input voltage Vin and charges the inductor L. When the high-side switch M1 is off and the low-side switch M2 is on, the inductor L discharges to the output terminal, thereby generating the output voltage Vout.

[0034] The control circuit 2000 includes an error amplifier circuit 2100, a ramp compensation module 2200, an adder 2300, a comparator 2400, a timing module 2500, and a driver 2600. The timing module 2500 and the driver 2600 constitute a logic circuit.

[0035] The error amplifier circuit 2100 is used to obtain the error amplification signal Veao between the first voltage signal and the reference voltage Vref.

[0036] The ramp compensation module 2200 is used to generate a ramp signal to eliminate subharmonic oscillations when the switching converter is operating in CCM (continuous inductor current) mode. When the switching converter is operating in DCM mode, the ramp compensation module 2200 no longer functions.

[0037] The superimposed signal 2300 is used to superimpose the ramp signal and the error amplification signal Veao to generate a superimposed signal when the switching converter is operating in CCM mode.

[0038] The non-inverting input of comparator 2400 receives the superimposed signal, the inverting input receives the feedback voltage Vfb2 of the output voltage Vout, and the output provides a pulse width modulation signal (PWM). When the switching converter operates in DCM mode, since the slope compensation module 2200 is no longer active, the non-inverting input of comparator 2400 directly receives the error amplification signal Veao.

[0039] The logic circuit controls the on / off state of the high-side switch M1 and the low-side switch M2 based on the pulse width modulation (PWM) signal. The timing module 2500 monitors the PWM signal from the comparator 2400 and provides a control signal ctrl based on the PWM signal to control the driver 2600 to output control signals HG and LG. Specifically, after receiving the PWM signal indicating that the high-side switch M1 is on, the timing module 2500 outputs the control signal ctrl to control the high-side switch M1 to be on. After the high-side switch M1 reaches a set on time, it outputs the control signal ctrl to control the high-side switch M1 to be off. After the high-side switch M1 reaches its minimum off time, it monitors the PWM signal again, and when the PWM signal indicates that the high-side switch M1 is on, it outputs the control signal ctrl to control the high-side switch M1 to be on. Specifically, even if the timing module 2500 detects the pulse width modulation signal PWM indicating that the high-side switch M1 is turned on, it will not output the control signal ctrl to control the high-side switch M1 to turn on when the minimum turn-off time of the high-side switch M1 has not been reached. For example, when the comparator 2400 detects that Vfb2 < Veao, it outputs the pulse width modulation signal PWM indicating that the high-side switch M1 is turned on.

[0040] Optionally, the voltage values ​​of feedback voltage Vfb1 and feedback voltage Vfb2 can be the same or different, and this application does not make specific limitations.

[0041] Figure 3 A schematic diagram of an error amplifier circuit is shown. See also Figure 3 The error amplifier circuit 2100 includes a voltage clamping module consisting of a first clamping circuit 2110 and a second clamping circuit 2120, an error amplifier EA, and a compensation network 2130.

[0042] Error amplifier EA is, for example, a transconductance amplifier. Its non-inverting input receives a reference voltage Vref, its inverting input receives a feedback voltage Vfb1, and its output provides an amplified error signal Veao. Compensation network 2130 is used to perform frequency compensation on error amplifier EA. Compensation network 2130 includes a capacitor C1 and a resistor R1 connected between the output of error amplifier EA and ground, and a capacitor C2 connected between the output of error amplifier EA and ground.

[0043] The clamping module is used to clamp the voltage value of the error amplification signal Veao within a preset range.

[0044] The first clamping circuit 2110 clamps the minimum voltage value of the error amplification signal Veao to a first clamping voltage Veao,L. The first clamping circuit 2110 includes an operational amplifier A1, a frequency compensation module 2111, and a switching transistor M3. The switching transistor M3 is connected between the power supply voltage VDD and the output terminal of the error amplifier EA. The inverting input terminal of the operational amplifier A1 receives the first clamping voltage Veao,L, the non-inverting input terminal is connected to the output terminal of the error amplifier EA, and the output terminal is connected to the control terminal of the switching transistor M3. The control terminal of the switching transistor M3 is also connected to the frequency compensation module 2111. The switching transistor M3 is a PMOS transistor. The circuit structure of the frequency compensation module 2111 is, for example, the same as that of the compensation network 2130.

[0045] The second clamping circuit 2120 is used to clamp the maximum voltage value of the error amplified signal Veao to the second clamping voltage Veao,H. The second clamping circuit 2120 includes an operational amplifier A2, a frequency compensation module 2121, and a switching transistor M4. The switching transistor M4 is connected between the output terminal of the error amplifier EA and the ground terminal. The inverting input terminal of the operational amplifier A2 receives the second clamping voltage Veao,H, and the non-inverting input terminal is connected to the output terminal of the error amplifier EA. The output terminal is connected to the control terminal of the switching transistor M4, which is also connected to the frequency compensation module 2121. The switching transistor M4 is an NMOS transistor. The circuit structure of the frequency compensation module 2121 is, for example, the same as that of the compensation network 2130.

[0046] When the switching converter operates in DCM mode, and the feedback voltage Vfb1 of the switching converter output voltage Vout is greater than the reference voltage Vref for a long time, the error amplification signal Veao will be clamped to the first clamping voltage Veao,L when it decreases to Veao,L. Therefore, when the load current Io suddenly increases and causes the output voltage Vout to decrease, the comparator 2400 can only flip to a high level again to turn on the high-side switch M1 of the switching converter and cause the inductor current IL to rise when the feedback voltage Vfb2 decreases to the first clamping voltage Veao,L.

[0047] The error amplifier circuit 2100 of the aforementioned switching converter prevents the high-side switch M1 from turning on again only after the output voltage Vout drops to a very low level by clamping the error amplifier signal Veao. However, compared with the error amplifier signal Veao when the switching converter is operating normally (i.e., when the switching converter is operating stably in CCM mode), the first clamping voltage Veao,L is still a relatively small value, meaning that the output voltage Vout still inevitably drops to a relatively small value. Furthermore, even if the error amplifier signal Veao is clamped, the internal node voltage of the error amplifier EA is still uncontrolled, and the error amplifier EA requires a long time to recover to its normal operating state after the load changes.

[0048] Figure 4 It shows Figure 3 The timing diagram of the switching converter corresponding to the error amplifier circuit shown is available in [reference]. Figure 4 When the load current Io of the switching converter jumps from light load to heavy load, the high-side switch M1 will only turn on when the feedback voltage Vfb2 drops to the first clamping voltage Veao,L, and the inductor current IL will start to rise accordingly.

[0049] Based on this, the inventors of this invention improved the error amplifier circuit to solve the above problems.

[0050] Figure 5 A schematic diagram of the error amplifier circuit of a switching converter according to an embodiment of the present invention is shown.

[0051] See Figure 5 The error amplifier circuit 2100 provided in this embodiment of the invention... Figure 3 The error amplifier circuit shown is based on the circuit with the addition of a signal selection circuit 2140 and an inner loop gain analog circuit 2150. The connection relationship of the error amplifier EA has also been adjusted accordingly. The differences between the two are explained below.

[0052] The non-inverting input of the error amplifier EA receives the reference voltage Vref, the inverting input receives the first voltage signal, and the output of the error amplifier EA provides the error amplification signal Veao.

[0053] The inner-loop gain analog circuit 2150 generates an analog voltage signal Veao,P proportional to the output of the error amplifier EA. The inner-loop gain analog circuit 2150 includes a switch M5 and a resistor R3 connected sequentially between the power supply voltage VDD and ground; switches M6 and M7 and a resistor R2 connected sequentially between the power supply voltage VDD and ground; and an operational amplifier A3. The control terminals of switches M5 and M6 are connected, and the control terminal of switch M6 is connected to its second terminal (drain). The non-inverting input of operational amplifier A3 is connected to the error amplification signal Veao, the inverting input is connected to the common node of switch M7 and resistor R2, and the output is connected to the control terminal of switch M7. The common node of switch M5 and resistor R3 provides the analog voltage signal Veao,P. The analog voltage signal Veao,P characterizes the feedback voltage Vfb1 of the output voltage Vout when the switching converter is stably operating in CCM mode. Switches M5 and M6 are PMOS transistors, and switch M7 is an NMOS transistor.

[0054] Furthermore, the ratio is set to the ratio of the resistance values ​​of resistor R3 to resistor R2. R3 / R2 is used to simulate the gain of the voltage inner loop, that is, the gain of the simulated feedback voltage Vfb2 and the error amplification signal Veao. If the gain of the voltage inner loop Vfb2 / Veao = 1, the inner loop gain simulation circuit 2150 can be omitted, and the error amplification signal Veao can be directly provided to the signal selection circuit 2140.

[0055] The signal selection circuit 2140 is used to select either the feedback voltage Vfb1 or the analog voltage signal Veao,P as the first voltage signal based on the DCM mode flag signal DCM1 of the switching converter. When the signal selection circuit 2140 switches the first voltage signal from the feedback voltage Vfb1 to the analog voltage signal Veao,P, the error amplifier EA and the inner loop gain analog circuit 2150 form a voltage regulation loop.

[0056] The signal selection circuit 2140 includes transmission gates TG1 and TG2. Transmission gates TG1 and TG2 are controlled by inverted clock signals clk1 and clk2 to conduct alternately. When transmission gate TG1 is on, it selects the feedback voltage Vfb1 as the first voltage signal. When transmission gate TG2 is on, it selects the analog voltage signal Veao,P as the first voltage signal.

[0057] Specifically, when the switching converter operates in DCM mode, and clock signal clk1 is high and clock signal clk2 is low, transmission gate TG1 is turned off and transmission gate TG2 is turned on, so that the analog voltage signal Veao,P is output as the first voltage signal, enabling the state-holding loop of error amplifier EA to start functioning and ensuring that error amplifier EA is not in an open-loop state. Since the gain from the error amplifier signal Veao to the analog voltage signal Veao,P is set to the gain of the voltage inner loop, it ensures that when the load current Io changes, as long as the output voltage Vout is lower than the normal value, comparator 2400 can immediately respond and give a new switching action. When clock signal clk1 is low and clock signal clk2 is high, transmission gate TG1 is turned on and transmission gate TG2 is turned off. Transmission gate TG1 outputs the feedback voltage Vfb1 as the first voltage signal. At this time, error amplifier EA is reconnected to the voltage outer loop, and the switching converter switches to normal operating mode.

[0058] Figure 6 A schematic diagram of the clock signal generation circuit of a switching converter according to an embodiment of the present invention is shown.

[0059] See Figure 6 The clock signal generation circuit includes NOR gate 1141, NOR gate 1142, AND gate 1143, inverter 1144, and delay module 1145. Among them, NOR gate 1141 and NOR gate 1142 constitute flip-flops.

[0060] The first input terminal of NOR gate 1141 is connected to the control signal HG, the second input terminal is connected to the output terminal of NOR gate 1142, and the output terminal provides a trigger signal.

[0061] The first input terminal of NOR gate 1142 is connected to the output terminal of NOR gate 1141, and the second input terminal is connected to the control signal LG.

[0062] The delay module 1145 is used to receive the DCM mode flag signal DCM1, and when the DCM mode flag signal DCM1 indicates that the switch converter switches to DCM mode, it delays for a preset time td and outputs the DCM mode flag signal DCM1 to the second input terminal of the AND gate 1143; when the DCM mode flag signal DCM1 indicates that the switch converter exits DCM mode, it directly outputs the DCM mode flag signal DCM1 to the second input terminal of the AND gate 1143.

[0063] The first input of AND gate 1143 receives a trigger signal, the second input receives the DCM mode flag signal DCM1 provided by delay module 1145, and the output provides a clock signal clk1.

[0064] The inverter 1144 receives clock signal clk1 at its input and provides clock signal clk2 at its output.

[0065] When the high-side switch M1 of the switching converter is turned off and the low-side switch M2 is turned on, the control signal HG flips from high level to low level, and when the control signal LG flips from low level to high level, the trigger signal flips from low level to high level. After the inductor current IL drops to 0, the DCM mode flag signal DCM1 will also flip from low level to high level. After the DCM mode flag signal DCM1 is held at a high level for a preset time td, the delay module 1145 outputs the high-level DCM mode flag signal DCM1 to the AND gate 1143, causing the clock signal clk1 to flip from low level to high level and the clock signal clk2 to flip from high level to low level. When the high-level holding time of the DCM mode flag signal DCM1 is less than the preset time td, the delay module 1145 will continuously output the low-level DCM mode flag signal DCM1 to the AND gate 1143, and the clock signals clk1 and clk2 will not flip. The preset time td is relatively small, and its purpose is mainly to avoid the critical state between CCM mode and DCM mode. During this time, the output voltage Vout does not change much. Therefore, the error amplification signal Veao after the preset time td can simulate the feedback voltage Vfb1 when the switching converter is working normally only after passing through the inner loop gain simulation circuit 2150.

[0066] When the load current Io increases, causing the output voltage Vout to decrease and triggering a new switching action, the control signal HG flips from low level to high level, the control signal LG flips from high level to low level, the trigger signal flips from high level to low level, the clock signal clk1 output by AND gate 1143 flips from high level to low level, and the clock signal clk2 output by inverter 1144 flips from low level to high level.

[0067] Figure 7 A timing diagram of a switching converter according to an embodiment of the present invention is shown.

[0068] See Figure 7 When the load current Io of the switching converter jumps from light load to heavy load, as long as the feedback voltage Vfb2 drops to the same level as the error amplification signal Veao when the switching converter is operating normally, the high-side switch M1 will turn on, causing the inductor current IL to rise, thereby improving the transient response speed of the switching converter and reducing the undervoltage value of the output voltage Vout.

[0069] The control circuit 2000 of the switching converter provided in this embodiment of the invention includes an error amplifier circuit 2100 for obtaining an error amplification signal Veao between a first voltage signal and a reference voltage Vref; a comparator 2400 for comparing the error amplification signal Veao with the feedback voltage Vfb2 of the output voltage Vout to obtain a pulse width modulation signal PWM; and a logic circuit for controlling the on and off of the high-side switch M1 and the low-side switch M2 according to the pulse width modulation signal PWM. The error amplifier circuit 2100 includes an error amplifier EA for comparing the first voltage signal with the reference voltage Vref to output the error amplification signal Veao. The circuit includes an inner-loop gain analog circuit 2150 for obtaining an analog voltage signal Veao,P that is proportional to the output of the error amplifier EA; and a signal selection circuit 2140 for selecting either the feedback voltage Vfb1 of the output voltage Vout or the analog voltage signal Veao,P as the first voltage signal according to the operating state of the switching converter. This ensures that after the switching converter is stably operating in DCM mode, as long as the feedback voltage Vfb2 drops to the error amplifier signal Veao when the switching converter is operating normally, the high-side switch M1 will turn on, causing the inductor current IL to rise, thereby improving the transient response speed of the switching converter and reducing the undervoltage value of the output voltage Vout.

[0070] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.

Claims

1. A control circuit for a switching converter, the switching converter including a high-side switch and a low-side switch, the control circuit being used to control the on and off states of the high-side switch and the low-side switch to convert the input voltage of the switching converter into an output voltage, the control circuit comprising: An error amplifier circuit is used to obtain an amplified error signal between the first voltage signal and the reference voltage. A comparator is used to generate a pulse width modulation signal based on the error amplification signal and a second feedback voltage of the output voltage; as well as A logic circuit is used to control the on and off states of the high-side and low-side switches according to the pulse width modulation signal. The error amplifier circuit includes an error amplifier, an inner loop gain analog circuit, and a signal selection circuit. The error amplifier is used to compare the first voltage signal with the reference voltage to output the error amplification signal; The inner loop gain analog circuit is used to obtain an analog voltage signal that is proportional to the output of the error amplifier. The analog voltage signal is used to characterize the first feedback voltage of the output voltage of the switching converter when it is stably operating in the continuous inductor current mode. The signal selection circuit is used to select one of the first feedback voltage of the output voltage and the analog voltage signal as the first voltage signal according to the flag signal of the DCM mode of the switching converter. When the signal selection circuit switches the first voltage signal from the first feedback voltage to the analog voltage signal, the error amplifier and the inner loop gain analog circuit form a voltage regulation loop.

2. The control circuit according to claim 1, wherein, The signal selection circuit is used to select the first feedback voltage of the output voltage as the first voltage signal when the switching converter is operating in the continuous inductor current mode, and to select the analog voltage signal as the first voltage signal after the low-side switch is turned on and the switching converter has maintained the discontinuous inductor current mode for a preset time.

3. The control circuit according to claim 1, wherein, The inner loop gain analog circuit includes: The first switching transistor and the first resistor are connected sequentially between the power supply voltage and the ground terminal; The second switch, the third switch, and the second resistor are connected sequentially between the power supply voltage and the ground terminal; and The first operational amplifier has the error amplification signal received at its non-inverting input, its inverting input connected to the common node of the third switch and the second resistor, and its output connected to the control terminal of the third switch. In this configuration, the control terminals of the first and second switching transistors are connected, and the control terminal of the second switching transistor is connected to its drain terminal. The common node of the first switch and the first resistor provides the analog voltage signal.

4. The control circuit according to claim 3, wherein, The set ratio is the ratio of the resistance values ​​of the first resistor to the resistance values ​​of the second resistor.

5. The control circuit according to claim 1, wherein, The signal selection circuit includes: The first and second transmission gates are controlled by the inverted first and second clock signals. When the first clock signal is high, the first transmission gate is turned off and the second transmission gate is turned on, and the second transmission gate outputs the analog voltage signal as the first voltage signal. When the first clock signal is low, the first transmission gate is turned on and the second transmission gate is turned off. The first transmission gate outputs the first feedback voltage as the first voltage signal.

6. The control circuit according to claim 5, wherein, The error amplifier circuit further includes: A clock signal generation circuit is used to generate the first clock signal and the second clock signal based on the flag signal of the DCM mode, the first control signal, and the second control signal. The DCM mode flag signal is used to characterize the operating state of the switching converter, the first control signal is used to control the on and off of the high-side switch, and the second control signal is used to control the on and off of the low-side switch.

7. The control circuit according to claim 6, wherein, The clock signal generation circuit includes: A trigger, used to generate a trigger signal based on the first control signal and the second control signal; The delay module is used to receive the flag signal of the DCM mode, and after the flag signal of the DCM mode indicates that the switching converter has switched to the inductor current discontinuous mode, it outputs the flag signal of the DCM mode after a preset delay. The AND gate receives the trigger signal at its first input terminal, receives the trigger signal provided by the delay module at its second input terminal, and provides the first clock signal at its output terminal. An inverter receives the first clock signal at its input and provides the second clock signal at its output.

8. The control circuit according to claim 7, wherein, The trigger is configured to output a high-level trigger signal when the first control signal is low and the second control signal is high, and to output a low-level trigger signal when the first control signal is high and the second control signal is low. The DCM mode flag signal is low when the switching converter operates in continuous inductor current mode and high when the switching converter operates in discontinuous inductor current mode.

9. The control circuit according to claim 1, further comprising: A voltage clamping module is used to clamp the voltage value of the error amplification signal within a preset range; A compensation network is used to perform frequency compensation on the error amplifier.

10. A switching converter, comprising: The input terminal and the output terminal respectively receive the input voltage and provide the input voltage. A high-side switch and a low-side switch are connected in series between the input terminal and the ground terminal; An inductor connected between the intermediate node of the high-side switch and the low-side switch and the output terminal. The control circuit as described in any one of claims 1-9 is used to control the on and off states of the high-side switch and the low-side switch to convert the input voltage of the switching converter into the output voltage.

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