A fixed slope start-up circuit for a buck converter

Abstract

The application claims a fixed slope starting circuit for a step-down converter, which is mainly composed of a clock generator, a sampling module, a slope control module, comparators COMP1-2, a data selector and a non-overlapping clock. A and CLK B to control the timing of the sampling module and the slope control module, the sampling module will sample the output voltage V OUT according to the clock signals CLK A and CLK B , and output a detection signal V SEN , the slope control module will compare the output voltage V OUT and the detection signal V SEN according to the change of the clock signal CLK B , and output a soft starting voltage V SS . The rising slope of the output voltage V OUT can be controlled by controlling the rising slope of the soft starting voltage V SS , and the fixed slope starting can be realized.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design technology, and specifically relates to a fixed-slope startup circuit for a buck converter. Background Technology

[0002] In DC-DC power converters, sudden changes in current and voltage during startup can negatively impact the system. Traditional hard-start methods involve directly connecting the input power supply, causing the converter to start operating immediately. This startup method can cause instantaneous peaks in the input current, voltage fluctuations in the power lines, and additional stress and noise on the power supply and load.

[0003] To address these issues, soft-start technology was introduced. Soft-start avoids voltage fluctuations and peak currents in the power supply line, reducing stress on the power supply and load, while also minimizing noise and interference in the system. It provides smooth output voltage and current during startup, preventing system instability and damage.

[0004] Fixed-time soft start refers to a process where the output voltage or current is gradually increased over a fixed period during startup. Specifically, the output voltage or current increases linearly at a fixed rate during startup until a set value is reached. Fixed-time soft start achieves a slow increase in output by controlling the startup time, and is unaffected by input voltage, load changes, or other factors. Therefore, it is not suitable for high-precision, high-power buck converters.

[0005] To achieve high precision and high power in buck converters, this invention proposes a fixed-slope soft-start circuit. Fixed-slope soft-start refers to increasing the output voltage or current at a fixed slope during the startup process. The slope can be understood as the rate of change of the output voltage or current. Fixed-slope soft-start achieves a gradual increase in output by controlling the slope. Unlike fixed-time soft-start, the duration of fixed-slope soft-start is determined based on the rate of change of the output voltage or current. This startup method is more suitable for applications requiring more precise control of the startup process, especially for high-power and high-precision DC-DC converters. Summary of the Invention

[0006] This invention aims to solve the problems of the prior art mentioned above. A fixed-slope startup circuit for a buck converter is proposed. The technical solution of this invention is as follows:

[0007] A fixed-slope startup circuit for a buck converter includes: a clock generator, a sampling module, a slope control module, comparators COMP1-2, a data selector, and a non-overlapping clock, wherein the clock signal CLK of the clock generator is... A and CLK BAll are connected to the sampling module, clock signal CLK B Connect the slope control module; the clock generator is used to generate the clock signal CLK. A and CLK B To control the timing of the sampling module and the slope control module; the sampling module is used to control the timing of the clock signal CLK. A and CLK B Sampling output voltage V OUT And the output signal is the detection signal V. SEN The slope control module is used to control the slope based on the clock signal CLK. B Compare the changes in output voltage V OUT and detection signal V SEN The output signal is the soft-start voltage V. SS By controlling the soft-start voltage V SS The rising slope thus controls the output voltage V. OUT The rising slope is used to achieve a fixed slope start-up; the data selector is used to adjust the control signal V. G The output voltage of the data selector is selected by using '0' or '1', and a soft-start voltage V is used. SS Or use reference voltage V REF Start-up; Comparator COMP2 is used to compare the soft-start voltage V. SS and reference voltage V REF The size of V SS <V REF Control signal V G ='0', when V SS >V REF Control signal V G ='1'; Comparator COMP1 is used to compare the feedback voltage V FB and the output signal V of the data selector C To generate the duty cycle signal V PWM The non-overlapping clock is used to prevent the high-side MOS transistor (H_side) and the low-side MOS transistor (L_side) from conducting simultaneously, so that V... IN A large current is generated when directly connected to GND.

[0008] Furthermore, the input signal of the sampling module is the output voltage V of the buck converter. OUT Clock signal CLK A and CLK B The input signal to the slope control module is the output voltage V. OUT Detection signal V SEN Clock signal CLK B The output signal is the soft-start voltage V. SS The input signal of the data selector is the reference voltage V. REFSoft start voltage V SS The output signal is V C The negative input signal of comparator COMP2 is the reference voltage V. REF Positive input signal soft-start voltage V SS The output signal is the control signal V of the data selector. G The negative input signal of comparator COMP1 is the feedback voltage V. FB The positive input signal is the output signal V of the data selector. C The output signal is the duty cycle signal V. PWM The input signal for the non-overlapping clock is the duty cycle signal V. PWM The output signal is the drive signal V. GH and V GL ;

[0009] Furthermore, the sampling module includes an NMOS transistor M. N1 M N12 Capacitor C1 and current source I1, NMOS transistor M N1 The gate is connected to the clock signal CLK A The source is connected to capacitor C1, the drain is connected to current source I1, and the NMOS transistor M... N2 The gate is connected to the clock signal CLK B The source is connected to capacitor C1, and the drain is connected to the output voltage V. OUT .

[0010] Furthermore, in the sampling module, the current source I1 and the NMOS transistor M... N1 Capacitor C1 and capacitor C2 together form the reference slope generation module, which generates the slope in response to the clock signal CLK. A ='0', CLK B When ='1', NMOS transistor M N2 When turned on, the output voltage V OUT It will be sampled by capacitor C1 in the clock signal CLK A ='1', CLK B When the current is '0', current source I1 linearly charges capacitor C1, and the detection signal V... SEN It rises at a constant slope.

[0011] Furthermore, the slope control module includes a dynamic comparator, a 6-bit up / down counter, a decoder, and a PMOS transistor M. P0 -PMOS transistor M P65 Switches D0-D63 and capacitor C2, including PMOS transistor M. P0 -PMOS transistor M P65 The source is connected to the input voltage V. IN PMOS transistor M P0 -PMOS transistor M P63The drain is connected to switches D0-D63, and the gate is connected to PMOS transistor M. P65 The gate and drain of the PMOS transistor are connected, and the PMOS transistor M P64 The drain of the transistor is connected to capacitor C2, and capacitor C2 is connected to switches D0-D63; the dynamic comparator includes PMOS transistor M. P66- PMOS transistor M P70 NMOS transistor MN 0-3 PMOS transistor MP 66 The source terminal V IN The gate is connected to the clock signal CLK. B The drain is connected to the PMOS transistor M. P67-68 The source of the PMOS transistor; P67 The gate is connected to the output voltage V OUT The drain is connected to the PMOS transistor M. P69 The source of the PMOS transistor; P68 The gate is connected to the detection signal V SEN The drain is connected to the PMOS transistor M. P70 The source of the PMOS transistor; P69 The gate of the NMOS transistor M N1 The gate of the NMOS transistor M N3 and PMOS transistor MP 70 Drain connected; PMOS transistor M P70 The gate of the NMOS transistor M N3 The gate of the NMOS transistor M N2 and PMOS transistor M P69 Drain connected, NMOS transistor M N0-3 The source of the NMOS transistor is connected to GND; N0-1 Gate and clock signal CLK B Connected; NMOS transistor M N0 The drain of the NMOS transistor M N3 and PMOS transistor MP 70 Drain connected, NMOS transistor M N1 The drain of the NMOS transistor M N2 and PMOS transistor MP 69 The drains are connected; the input signals for the upper and lower counters come from the output signals UP / DN of the dynamic comparator, and the output signal is D. CTRL [5:0] After passing through the decoder, a 64-bit binary code will be generated, which controls switches D0-D63.

[0012] Furthermore, the positive input terminal of the dynamic comparator in the slope control module is connected to the output voltage V. OUT The negative input terminal is connected to the detection signal V. SEN The positive output terminal is the DN signal, and the negative output terminal is the UP signal. When the output voltage VOUT Greater than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is greater than that of the detection signal V. SEN At this time, the output port of the dynamic comparator has UP = '0' and DN = '1', and the up and down counters will perform decrementing counting, i.e., D CTRL [5:0] will decrease. The 64-bit binary code output after decoding increases the number of switches D0-63 that are open, reduces the charging current to capacitor C2, and decreases the soft-start voltage V. SS The rate of increase decreases, reducing the output voltage V. OUT The rate of increase of the output voltage V; when the output voltage V OUT Less than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is less than that of the detection signal V. SEN At this time, the output port of the dynamic comparator has UP = '1' and DN = '0', and the upper and lower counters perform increment counting, i.e., D CTRL [5:0] will increase, and the 64-bit binary code output after the decoder will increase the number of switches D0-D63 closed, increasing the charging current to capacitor C2 and the soft-start voltage V. SS An increase in the rate of rise increases the output voltage V. OUT The rate of increase.

[0013] Furthermore, the comparator COMP1-2 includes a PMOS transistor M P0- M P4 and NMOS transistor M N0-5 Among them, PMOS transistor M P0 PMOS transistor M P3 PMOS transistor M P4 The source and input voltage V IN Connected, PMOS transistor M P0 Gate and bias voltage V B Connected, drain and PMOS transistor M P1- M P The source terminals of transistors 2 and 3 are connected; NMOS transistor M P2 The drain of the NMOS transistor M N2-3 The gate of the NMOS transistor M P1 The drain of the NMOS transistor M N4-5 The gate of the NMOS transistor; N2 The drain and gate of the NMOS transistor are connected. N5 The drain and gate of the NMOS transistor are connected; N1 The drain of the PMOS transistor M P4 The drain is connected to the gate of the PMOS transistor M. P3 The gate of the PMOS transistor is connected to the gate of the PMOS transistor M. P3 The drain of the NMOS transistor MN0 The drains of the NMOS transistors are connected; N0-5 The source is connected to GND.

[0014] The advantages and beneficial effects of this invention are as follows:

[0015] 1. Low quiescent current. This invention proposes a fixed-slope startup circuit for buck converters, which uses almost no dynamic current, thus reducing chip power consumption.

[0016] 2. Low cost and good controllability. The sampling module in the fixed slope start-up circuit of this invention can be used in CLK. A ='0', CLK B When ='1', the output voltage is sampled to obtain the current output voltage information, in CLK A ='1', CLK B When ='0', capacitor C1 will be charged using current source I1 based on the output voltage sampled in the previous moment, and CLK B The rising edge of the sampled signal V after charging SEN The upper and lower counters are compared to determine whether to perform addition or subtraction. The upper and lower counters output signal D. CTRL [5:0] The 64-bit binary code output by the decoder controls the opening and closing of switches D0-D63, thereby controlling the soft-start voltage V. SS The slope of the voltage is determined, which in turn controls the slope of the output voltage.

[0017] 3. More precise control. Fixed-slope soft start can adjust the start-up rate according to the actual changes in output voltage or current. By controlling the output slope, voltage and current changes during the start-up process can be controlled more precisely to meet the system's stability and performance requirements.

[0018] 4. Adaptable to different load conditions. Fixed-ratio soft start can dynamically adjust the starting rate according to different load conditions. Under light load, the starting rate can be increased to reduce starting time; while under heavy load, the starting rate can be decreased to avoid current surges and system instability.

[0019] 5. Reduce startup shock. Fixed-slope soft start smoothly increases output voltage or current, reducing shocks and stress during startup. This helps reduce voltage fluctuations, current peaks, and power line voltage drops in the system, improving system reliability and stability.

[0020] 6. Improve system lifespan. Fixed-ratio soft starts reduce energy waste and instability during startup, thereby extending the lifespan of the power supply and other critical components. By reducing startup shocks and voltage fluctuations, stress and heat in the system can be reduced, minimizing damage to the power supply and load. Attached Figure Description

[0021] Figure 1 This is a preferred embodiment of the fixed-slope startup circuit diagram for a buck converter provided by the present invention.

[0022] Figure 2 This is a circuit diagram of a dynamic comparator according to a preferred embodiment of the present invention;

[0023] Figure 3 This is the circuit diagram for comparator COMP1-2.

[0024] Figure 4 These are the transient simulation waveforms of a fixed slope during startup under different output voltages. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of the present invention.

[0026] The technical solution of the present invention to solve the above-mentioned technical problems is:

[0027] like Figure 1 As shown: A fixed-slope start-up circuit for a buck converter mainly consists of a clock generator, a sampling module, a slope control module, comparators COMP1-2, a data selector, and a non-overlapping clock. Figure 1 (a) shows the overall circuit block diagram of the system. Figure 1 (b) indicates the fixed slope start-up core circuit of the present invention.

[0028] Clock signal CLK of the clock generator A and CLK B Connect the sampling module and the slope control module. The input signal of the sampling module is the output voltage V of the buck converter. OUT Clock signal CLK A and CLK B The input signal to the slope control module is the output voltage V. OUT Detection signal V SEN Clock signal CLK B The output signal is the soft-start voltage V. SS The input signal to the data selector is the reference voltage VREF and the soft-start voltage V. SS The output signal is V CThe negative input signal of comparator COMP2 is the reference voltage V. REF Positive input signal soft-start voltage V SS The output signal is the control signal V of the data selector. G The negative input signal of comparator COMP1 is the feedback voltage V. FB The positive input signal is the output signal V of the data selector. C The output signal is the duty cycle signal V. PWM The input signal for a non-overlapping clock is the duty cycle signal V. PWM The output signal is the drive signal V. GH and V GL .

[0029] The clock generator is used to generate the clock signal CLK. A and CLK B To control the timing of the sampling module and the slope control module; the sampling module will follow the clock signal CLK. A and CLK B Desampled output voltage V OUT And the output signal is the detection signal V. SEN The slope control module will adjust according to the clock signal CLK. B Compare the changes in output voltage V OUT and detection signal V SEN The output signal is the soft-start voltage V. SS It can be controlled by adjusting the soft-start voltage V. SS The rising slope thus controls the output voltage V. OUT The rising slope is used to achieve a fixed slope start-up; the control signal of the data selector is V. G When V G ='0', the output signal V of the data selector C =V SS VC represents the output signal of the data selector, V SS This represents the soft-start voltage. When V G ='1', the output signal V of the data selector C =V REF VC represents the output signal of the data selector, V REF This represents the reference voltage; comparator COMP2 compares the soft-start voltage V. SS and reference voltage V REF The size of V SS <V REF Control signal V G ='0', when V SS >V REF, Control signal V G='1'; The main function of comparator COMP1 is to compare the feedback voltage V FB and the output signal V of the data selector C To generate the duty cycle signal V PWM This ensures the normal operation of the system. The main function of the non-overlapping clock is to prevent the high-side MOS transistor (H_side) and the low-side MOS transistor (L_side) from conducting simultaneously, allowing V... IN Direct connection to GND creates a large current, which can damage the device.

[0030] Preferably, the sampling module is composed of an NMOS device M N1～2 It consists of capacitor C1, current source I1, and NMOS transistor M. N1 The gate is connected to the clock signal CLK A The source is connected to capacitor C1, the drain is connected to current source I1, and the NMOS transistor M... N2 The gate is connected to the clock signal CLK B The source is connected to capacitor C1, and the drain is connected to the output voltage V. OUT NMOS transistor M N1 Capacitor C1 forms the reference slope generation module. In the clock signal CLK... A ='0', CLK B When ='1', NMOS transistor M N2 When turned on, the output voltage V OUT It will be sampled by capacitor C1 in the clock signal CLK A ='1', CLK B When the current is '0', current source I1 will linearly charge capacitor C1, and the detection signal V... SEN It will rise at a constant slope.

[0031] Preferably, the dynamic comparator is a PMOS transistor M P66-70 NMOS transistor MN 0-3 Composition. PMOS transistor MP 66 The source terminal V IN The gate is connected to the clock signal CLK. B The drain is connected to the PMOS transistor M. P67-68 The source of the PMOS transistor; P67 The gate is connected to the output voltage V OUT The drain is connected to the PMOS transistor M. P69 The source of the PMOS transistor; P68 The gate is connected to the detection signal V SEN The drain is connected to the PMOS transistor M. P70 The source of the PMOS transistor; P69 The gate of the NMOS transistor M N1 The gate of the NMOS transistor M N3 and PMOS transistor MP70 Drain connected; PMOS transistor M P70 The gate of the NMOS transistor M N3 The gate of the NMOS transistor M N2 and PMOS transistor M P69 Drain connected, NMOS transistor M N0-3 The source of the NMOS transistor is connected to GND. N0-1 The gate of the NMOS transistor is connected to the clock signal CLKB. N0 The drain of the NMOS transistor M N3 and PMOS transistor MP 70 Drain connected, NMOS transistor M N1 The drain of the NMOS transistor M N2 and PMOS transistor MP 69 The drains are connected.

[0032] Preferably, the positive input terminal of the dynamic comparator in the slope control module is connected to the output voltage V. OUT The negative input terminal is connected to the detection signal V. SEN The positive output terminal is the DN signal, and the negative output terminal is the UP signal. When the output voltage V OUT Greater than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is greater than that of the detection signal V. SEN At this time, the output port of the dynamic comparator has UP = '0' and DN = '1', and the up and down counters will perform decrementing counting, i.e., D CTRL [5:0] will decrease. The 64-bit binary code output after decoding will increase the number of switches D0-D63 that are open, thus reducing the charging current to capacitor C2 and the soft-start voltage V. SS The rate of increase decreases, which in turn reduces the output voltage V. OUT The rate of increase.

[0033] Preferably, when the output voltage V OUT Less than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is less than that of the detection signal V. SEN At this time, the output port of the dynamic comparator has UP = '1' and DN = '0', and the up and down counters will increment, i.e., D CTRL [5:0] will increase, and the 64-bit binary code output after the decoder will increase the number of switches D0-D63 closed, thus increasing the charging current to capacitor C2 and the soft-start voltage V. SS An increase in the rate of rise leads to an increase in the output voltage V. OUT The rate of increase.

[0034] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0035] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0036] The above embodiments should be understood as illustrative only and not as limiting the scope of protection of the present invention. After reading the description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A fixed-slope startup circuit for a buck converter, characterized in that, include: The system includes a clock generator, sampling module, slope control module, comparators COMP1-2, data selector, and non-overlapping clock. The clock signal CLK of the clock generator is also included. A and CLK B All are connected to the sampling module, clock signal CLK B Connect the slope control module; the clock generator is used to generate the clock signal CLK. A and CLK B To control the timing of the sampling module and the slope control module; the sampling module is used to control the timing of the clock signal CLK. A and CLK B Sampling output voltage V OUT And the output signal is the detection signal V. SEN The slope control module is used to control the slope based on the clock signal CLK. B Compare the changes in output voltage V OUT and detection signal V SEN The output signal is the soft-start voltage V. SS By controlling the soft-start voltage V SS The rising slope thus controls the output voltage V. OUT The rising slope is used to achieve a fixed slope start-up; the data selector is used to adjust the control signal V. G The output voltage of the data selector is selected by using '0' or '1', and a soft-start voltage V is used. SS Or use reference voltage V REF Start-up; Comparator COMP2 is used to compare the soft-start voltage V. SS and reference voltage V REF The size of V SS <V REF Control signal V G ='0', when V SS >V REF Control signal V G ='1'; Comparator COMP1 is used to compare the feedback voltage V FB and the output signal V of the data selector C To generate the duty cycle signal V PWM The non-overlapping clock is used to prevent the high-side MOS (H_side) and low-side MOS from conducting simultaneously, so that V... IN A large current is generated by directly connecting it to GND; The input signal of the sampling module is the output voltage V of the buck converter. OUT Clock signal CLK A and CLK B The input signal to the slope control module is the output voltage V. OUT Detection signal V SEN Clock signal CLK B The output signal is the soft-start voltage V. SS The input signal of the data selector is the reference voltage V. REF Soft start voltage V SS The output signal is V C The negative input signal of comparator COMP2 is the reference voltage V. REF Positive input signal soft-start voltage V SS The output signal is the control signal V of the data selector. G The negative input signal of comparator COMP1 is the feedback voltage V. FB The positive input signal is the output signal V of the data selector. C The output signal is the duty cycle signal V. PWM The input signal for the non-overlapping clock is the duty cycle signal V. PWM The output signal is the drive signal V. GH and V GL .

2. The fixed-slope start-up circuit for a buck converter according to claim 1, characterized in that, The sampling module includes an NMOS transistor M. N1、 M N2 Capacitor C1 and current source I1, NMOS transistor M N1 The gate is connected to the clock signal CLK A The source is connected to capacitor C1, the drain is connected to current source I1, and the NMOS transistor M... N2 The gate is connected to the clock signal CLK B The source is connected to capacitor C1, and the drain is connected to the output voltage V. OUT .

3. A fixed-slope start-up circuit for a buck converter according to claim 2, characterized in that, The sampling module contains current source I1 and NMOS transistor M. N1 Capacitor C1 and capacitor C2 together form the reference slope generation module, which generates the slope in response to the clock signal CLK. A ='0', CLK B When ='1', NMOS transistor M N2 When turned on, the output voltage V OUT It will be sampled by capacitor C1 in the clock signal CLK A ='1', CLK B When the value is '0', current source I1 linearly charges capacitor C1, and the detection signal V... SEN It rises at a constant slope.

4. A fixed-slope start-up circuit for a buck converter according to claim 1, characterized in that, The slope control module includes a dynamic comparator, a 6-bit up / down counter, a decoder, and a PMOS transistor. P0 -PMOS transistor M P65 Switches D0-D63 and capacitor C2, including PMOS transistor M. P0 -PMOS transistor M P65 The source is connected to the input voltage V. IN PMOS transistor M P0 -PMOS transistor M P63 The drain is connected to switches D0-D63, and the gate is connected to PMOS transistor M. P65 The gate and drain of the PMOS transistor are connected, and the PMOS transistor M P64 The drain of the capacitor is connected to capacitor C2, and capacitor C2 is connected to switches D0-D63; the dynamic comparator includes PMOS transistor M. P66- PMOS transistor M P70 NMOS transistor MN 0-3 PMOS transistor MP 66 The source terminal V IN The gate is connected to the clock signal CLK. B The drain is connected to the PMOS transistor M. P67-68 The source of the PMOS transistor; P67 The gate is connected to the output voltage V OUT The drain is connected to the PMOS transistor M. P69 The source of the PMOS transistor; P68 The gate is connected to the detection signal V SEN The drain is connected to the PMOS transistor M. P70 The source of the PMOS transistor; P69 The gate of the NMOS transistor M N2 The gate of the NMOS transistor M N3 and PMOS transistor MP 70 Drain connected; PMOS transistor M P70 The gate of the NMOS transistor M N3 The gate of the NMOS transistor M N2 and PMOS transistor M P69 Drain connected, NMOS transistor M N0-3 The source of the NMOS transistor is connected to GND; N0-1 Gate and clock signal CLK B Connected; NMOS transistor M N0 The drain of the NMOS transistor M N3 and PMOS transistor MP 70 Drain connected, NMOS transistor M N1 The drain of the NMOS transistor M N2 and PMOS transistor MP 69 The drains are connected; the input signals for the upper and lower counters come from the output signals UP / DN of the dynamic comparator, and the output signal is D. CTRL [5:0] After passing through the decoder, a 64-bit binary code will be generated, which controls switches D0-D63.

5. A fixed-slope start-up circuit for a buck converter according to claim 4, characterized in that, The positive input terminal of the dynamic comparator in the slope control module is connected to the output voltage V. OUT The negative input terminal is connected to the detection signal V. SEN The positive output terminal is the DN signal, and the negative output terminal is the UP signal. When the output voltage V OUT Greater than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is greater than that of the detection signal V. SEN At this time, the output port of the dynamic comparator has UP='0' and DN='1', and the up and down counters will perform decrementing counting, i.e., D CTRL [5:0] will decrease. The 64-bit binary code output after decoding increases the number of switches D0-D63 that are open, reducing the charging current to capacitor C2 and decreasing the soft-start voltage V. SS The rate of increase decreases, reducing the output voltage V. OUT The rate of increase; when the output voltage V OUT Less than the detection signal V SEN When this occurs, it indicates that the rising slope of the output voltage is less than that of the detection signal V. SEN At this time, the output ports of the dynamic comparator have UP='1' and DN='0', and the upper and lower counters perform increment counting, i.e., D CTRL [5:0] will increase, and the 64-bit binary code output after the decoder will increase the number of switches D0-D63 closed, increasing the charging current to capacitor C2 and the soft-start voltage V. SS An increase in the rate of rise increases the output voltage V. OUT The rate of increase.

6. A fixed-slope start-up circuit for a buck converter according to claim 5, characterized in that, The comparator COMP1-2 includes a PMOS transistor M P0- M P4 and NMOS transistor M N0-5 Among them, PMOS transistor M P0 PMOS transistor M P3 PMOS transistor M P4 The source and input voltage V IN Connected, PMOS transistor M P0 Gate and bias voltage V B Connected, drain and PMOS transistor M P1- M P 2 The source terminals are connected; NMOS transistor M P2 The drain of the NMOS transistor M N2-3 The gate of the NMOS transistor M P1 The drain of the NMOS transistor M N4-5 The gate of the NMOS transistor; N2 The drain and gate of the NMOS transistor are connected. N5 The drain and gate of the NMOS transistor are connected; N1 The drain of the PMOS transistor M P4 The drains are connected, M P4 The gate of the PMOS transistor M P3 The gate of the PMOS transistor is connected to the gate of the PMOS transistor M. P3 The drain of the NMOS transistor M N0 The drains of the NMOS transistors are connected; N0-5 The source is connected to GND.

Images