Reconfigurable frequency multiplier based on fefet

Abstract

This invention discloses a reconfigurable frequency multiplier based on FeFET, comprising several FeFET structures. The FeFET structure is one of a 4nFeFET structure, a 4pFeFET structure, or a 2nFeFET-2pFeFET structure. The 4nFeFET structure includes two nFeFET cells connected in series; the 4pFeFET structure includes two pFeFET cells connected in parallel; the 2nFeFET-2pFeFET structure includes Model 1 and Model 2. Model 1 includes two first complementary FeFET cells connected in series; Model 2 includes two second complementary FeFET cells connected in parallel. The reconfigurable frequency multiplier structures proposed in this invention significantly simplify the circuit area, requiring only a minimum of four transistors to achieve reconfigurable multiple frequency multiplication effects. Simultaneously, due to the simple circuit structure, power consumption is significantly reduced, fully utilizing the programmable characteristics of FeFETs to realize reconfigurable functionality.

Description

Technical Field

[0001] This invention belongs to the field of communication and storage technology, and specifically relates to a reconfigurable frequency multiplier based on FeFET. Background Technology

[0002] In an era of large-scale development in wireless communication technology, especially with the continuous advancement of 5G technology in recent years, signal transmission frequencies have been constantly increasing, even reaching the terahertz band. Therefore, frequency multiplication has become a crucial technology. However, currently widely used frequency multiplication techniques, such as phase-locked loops (PLLs), typically involve complex circuit structures and have high power consumption, making them unsuitable for power-sensitive devices. Therefore, for mobile or embedded devices with strict power constraints, there is an urgent need for a frequency multiplier with a simple circuit structure, low power consumption, and a high maximum operating frequency.

[0003] Recently, a reconfigurable frequency doubler design based on the ambipolar ferroelectric field-effect transistor (ambipolar FeFET) has emerged. This design utilizes the symmetrical parabolic transfer curve of the ambipolar FeFET to achieve frequency doubler functionality. Furthermore, based on the programmable threshold voltage of the FeFET, it achieves reconfigurability, allowing switching between frequency doubler and simple signal transmission functions. However, its limitation to frequency doubler functionality and inability to achieve higher frequency harmonics is a drawback. Combined with its relatively low maximum operating frequency, this limits its widespread application in current communication equipment.

[0004] In summary, it is extremely important to provide a reconfigurable frequency multiplier that can achieve multiple frequency multiplications and has a high maximum operating frequency, making it suitable for widespread use in mobile or embedded devices. Summary of the Invention

[0005] The purpose of this invention is to provide a reconfigurable frequency multiplier based on FeFET, offering three frequency multiplier designs based on 4nFeFET, 4pFeFET, and 2nFeFET-2pFeFET respectively. These designs achieve frequency multiplication (double, triple, or quadruple) while maintaining low power consumption and small area, as well as higher operating frequencies and simpler circuit structures. This addresses the problems of existing frequency multipliers, such as high power consumption, large area, and inability to meet multiple frequency multiplication functions.

[0006] The specific technical solution of this application is as follows:

[0007] A reconfigurable frequency multiplier based on FeFET includes several FeFET structures, wherein the FeFET structure is one of a 4nFeFET structure, a 4pFeFET structure, or a 2nFeFET-2pFeFET structure, wherein...

[0008] The 4nFeFET structure includes two nFeFET cells, a resistor R1, and a capacitor C. out1 Two nFeFET units are connected in series, and each nFeFET unit includes two n-type FeFETs connected in parallel;

[0009] The 4pFeFET structure includes two pFeFET units, a resistor R2, and a capacitor C. out2 Two pFeFET units are connected in parallel, and each pFeFET unit is composed of two p-type FeFETs connected in series;

[0010] The 2nFeFET-2pFeFET structure includes Model 1 and Model 2. Model 1 includes two first complementary FeFET cells, resistor R3, and capacitor C. out3 Model 1 consists of two first complementary FeFET cells connected in series, each consisting of a p-type FeFET and an n-type FeFET connected in parallel; Model 2 includes two second complementary FeFET cells, resistor R4, and capacitor C. out4 Two second complementary FeFET cells are connected in parallel, and each second complementary FeFET cell consists of a p-type FeFET and an n-type FeFET connected in series.

[0011] Furthermore, the 4nFeFET structure includes M1, M2, M3, and M4. M1 and M3 have gate word lines WL1, and M2 and M4 have gate word lines WL2. ScL1 is led out from the connection point of two nFeFET cells. The drains of M1 and M2 are connected to VDD through resistor R1, and the sources of M3 and M4 are connected to VSS. The drains of M1 and M2 are then connected to capacitor C. out Output signal V out During frequency multiplication, word line WL1 and word line WL2 are connected through an analog inverter.

[0012] Furthermore, the 4pFeFET structure includes M5, M6, M7, and M8. The gates of M5 and M6 are connected to word line WL3, and the gates of M7 and M8 are connected to word line WL4. Word line WL3 and word line WL4 are connected through an analog inverter. ScL2 is led out from the connection point of M5 and M7, and ScL3 is led out from the connection point of M6 and M8. The sources of M5 and M6 are connected to VDD through resistor R2. The drains of M7 and M8 are connected to VSS1 and VSS2 respectively. The sources of M5 and M6 are then connected to capacitor C. out1 Output signal Vout .

[0013] Furthermore, the first model includes M9 and M 10 M 11 and M 12 M9 and M 11 Gate connection word line WL5, M 10 and M 12 The gate word line WL6, ScL4 is led out from the connection point of the upper and lower first complementary FeFET cells, and the drain of M9 and M 10 The source of M is connected to VDD through resistor R3. 11 The source and M 12 The drain of M1 is connected to VSS, and the drain of M1 and the source of M2 are connected through capacitor C. out3 Output signal V out .

[0014] Furthermore, the second model includes M 13 M 14 M 15 and M 16 M 13 and M 14 Gate connection word line WL7, M 15 and M 16 Gate connection word line WL8, M 13 and M 15 ScL5 and M are led out from the connection point. 14 and M 16 The ScL6 connector is brought out at the connection point to facilitate writing to the FeFET. 13 and M 14 The source of M is connected to VDD through resistor R4. 15 and M 16 The source terminals are connected to VSS1 and VSS2 respectively, M 13 and M 14 The source electrode is then connected to capacitor C. out4 Output signal V out .

[0015] Furthermore, the operation steps of the 4nFeFET structure are as follows:

[0016] (1) Before starting work, first confirm the required frequency multiplication factor, and write different values ​​to the FeFET according to the different multiplication factors;

[0017] (2) When writing to M1 and M2, set ScL1 to 0 and set VSS to the same voltage as WL1, and write through WL1 and WL2; when writing to M3 and M4, set VSS to 0 and set ScL1 to the same voltage as WL1, and write through WL1 and WL2 in the same way.

[0018] (3) After writing different frequency multiplication modes, connect WL2 and WL1 through an analog inverter so that the signal on WL2 is inverted with the signal on WL1.

[0019] (4) During the frequency multiplication process, ScL is floated, and the signal is input from WL1 through capacitor C. out1 Output signal V out。

[0020] Furthermore, the operation steps of the 4pFeFET structure are as follows:

[0021] (1) Before starting work, first confirm the required frequency multiplication factor, and write different values ​​to the FeFET according to the different multiplication factors;

[0022] (2) When writing to M5, set ScL2 to 0 and set ScL3 to the same voltage as WL3; when writing to M6, set ScL3 to 0 and set ScL2 to the same voltage as WL3, and write through WL3; when writing to M7, set VSS1 to 0 and set VSS2 to the same voltage as WL4; when writing to M8, set VSS2 to 0 and set VSS1 to the same voltage as WL4, and write through WL4.

[0023] (3) After writing different frequency multiplication modes, connect WL4 and WL3 through an analog inverter so that the signal on WL4 is inverted with the signal on WL3.

[0024] (4) During the frequency multiplication process, ScL2 and ScL3 are floated, and the signal is input from WL3 through capacitor C. out2 Output signal V out .

[0025] Furthermore, the writing method of Model 1 is the same as that of the 4nFeFET structure, and the specific operation steps of Model 1 include:

[0026] (1) Before starting work, first confirm the required frequency multiplication factor, and write different values ​​to the FeFET according to the different multiplication factors;

[0027] (2) For M9 and M 10 During writing, set ScL4 to 0, set VSS to the same voltage as WL5, and write through WL5 and WL6; for M 11 and M 12 When writing, set VSS to 0, set ScL4 to the same voltage as WL5, and write through WL5 and WL6 in the same way.

[0028] (3) After writing to different frequency multiplier modes, connect WL5 and WL6 directly;

[0029] (4) During the frequency multiplication process, ScL4 is floated, and signals are input to both WL5 and WL6 through capacitor C. out3 Output signal V out .

[0030] Furthermore, the writing method of Model 2 is the same as that of the 4pFeFET structure, and the specific operation steps of Model 2 include:

[0031] (1) Before starting work, first confirm the required frequency multiplication factor, and write different values ​​to the FeFET according to the different multiplication factors;

[0032] (2) For M 13 When writing, set ScL5 to 0 and set ScL6 to the same voltage as WL7; for M 14 During writing, set ScL6 to 0, set ScL5 to the same voltage as WL7, and write through WL7; for M... 15 When writing, set VSS1 to 0 and set VSS2 to the same voltage as WL8; for M 16 When writing, set VSS2 to 0 and set VSS1 to the same voltage as WL8, then write through WL8;

[0033] (3) After writing to different frequency multiplier modes, connect WL7 and WL8 directly;

[0034] (4) During the frequency multiplication process, ScL5 and ScL6 are floated, and a common input signal is given to WL7 and WL8, which is then passed through capacitor C. out4 Output signal V out .

[0035] Furthermore, the multiplier includes a first harmonic, a second harmonic, a third harmonic, or a fourth harmonic.

[0036] Compared with the prior art, the present invention has the following advantages:

[0037] (1) The reconfigurable frequency multiplier structures proposed in this invention have significantly simplified circuit area compared with traditional frequency multiplication technologies such as phase-locked loops. At least four transistors are needed to achieve the frequency multiplication effect. At the same time, due to the simple circuit structure, the energy consumption is also greatly reduced.

[0038] (2) This invention utilizes the programmable characteristics of FeFET to easily switch the frequency multiplication factor and realize the reconfigurable function;

[0039] (3) For a reconfigurable frequency multiplier with a 4nFeFET structure, since it operates at the bottom of the characteristic curve, the current is relatively small, thus achieving lower power consumption;

[0040] (4) For a reconfigurable frequency multiplier with a 4pFeFET structure, since it operates at the top of the characteristic curve, the current is relatively large and the driving capability is relatively strong, thus achieving a very high maximum operating frequency.

[0041] (5) For the reconfigurable frequency multiplier with 2nFeFET-2pFeFET structure, since two inverting inputs are not required, the circuit area is smaller and simpler than the previous two structures because no analog inverter is needed. Attached Figure Description

[0042] Figure 1 The diagram shows the structure of the present invention. (a) is a reconfigurable frequency multiplier with a 4pFeFET structure, (b) is a reconfigurable frequency multiplier with a 4nFeFET structure, and (c) and (d) are 2nFeFET-2pFeFET reconfigurable frequency multipliers.

[0043] Figure 2 The schematic diagram shows the implementation of 1, 2, 3, and 4 times the frequency using the 4nFeFET and 2nFeFET-2pFeFET of this invention.

[0044] Figure 3 This is a schematic diagram of the 4pFeFET and 2nFeFET-2pFeFET implementation of frequency multiplication of 1, 2, 3, and 4 according to the present invention. Detailed Implementation

[0045] The following description, in conjunction with the accompanying drawings, further illustrates a reconfigurable frequency multiplier based on FeFET according to the present invention.

[0046] A reconfigurable frequency multiplier based on FeFET includes several FeFET structures, wherein the FeFET structure is one of a 4nFeFET structure, a 4pFeFET structure, or a 2nFeFET-2pFeFET structure.

[0047] like Figure 1 As shown in (a), each 4nFeFET structure includes two nFeFET cells, a resistor R1, and a capacitor C. out1 Two nFeFET cells are connected in series, and each nFeFET cell includes two parallel n-type FeFETs; the 4nFeFET structure includes M1, M2, M3 and M4, with gate word lines WL1 for M1 and M3, and gate word lines WL2 for M2 and M4. ScL1 is led out at the connection point of the two nFeFET cells. The drains of M1 and M2 are connected to VDD through resistor R1, and the sources of M3 and M4 are connected to VSS. The drains of M1 and M2 are then connected to capacitor C. out Output signal V out During frequency multiplication, word line WL1 and word line WL2 are connected through an analog inverter.

[0048] The operating steps of the 4nFeFET structure are as follows:

[0049] (1) Before starting work, first confirm the required frequency multiplier, and write different values ​​to the FeFET according to the different multipliers. The multipliers include first multiplier, second multiplier, third multiplier or fourth multiplier.

[0050] (2) When writing to M1 and M2, set ScL1 to 0 and set VSS to the same voltage as WL1, and write through WL1 and WL2; when writing to M3 and M4, set VSS to 0 and set ScL1 to the same voltage as WL1, and write through WL1 and WL2 in the same way.

[0051] (3) After writing different frequency multiplication modes, connect WL2 and WL1 through an analog inverter so that the signal on WL2 is inverted with the signal on WL1.

[0052] (4) During the frequency multiplication process, ScL is floated, and the signal is input from WL1 through capacitor C. out1 Output signal V out .

[0053] Four n-type FeFETs are written to in different ways, forming characteristic curves corresponding to different frequency multiplication modes. The characteristic curves of two nFeFET cells are formed by connecting the characteristic curves of two n-type FeFETs with inverted inputs in parallel, i.e., by superimposing the larger values. Both are parabolas with upward opening, and the characteristic curves of the two nFeFET cells have the same shape. The characteristic curve of the 4nFeFET structure is formed by connecting the characteristic curves of two nFeFET cells in series, i.e., by superimposing the smaller values.

[0054] like Figure 2 As shown, using the nanoampere-level current in the subthreshold region of the nFeFET, frequency doubling is achieved using the monotonic region of the characteristic curve; frequency doubling is achieved using the symmetrical, upward-opening parabolic region of the characteristic curve; frequency tripling is achieved using the centrally symmetrical double-strand curve region of the characteristic curve; and frequency quadrupleling is achieved using the symmetrical triple-strand curve region of the characteristic curve. In frequency doubling mode, the parabolic characteristic curves of the two nFeFET cells coincide, and the I values ​​of these two characteristic curves are... OFF The voltage corresponding to the point shifts to -A, where A is the amplitude of the input signal; in the frequency doubling mode, the parabolic characteristic curves of the two nFeFET cells coincide, and these two characteristic curves I OFF The voltage corresponding to the point is shifted to 0V; in triple frequency mode, the parabolic characteristic curves of the two nFeFET cells are spaced 4A / 3 apart, and the characteristic curve I of the first nFeFET cell is... OFF The voltage corresponding to the point is shifted to -A / 3, and the characteristic curve I of the second nFeFET unit is changed.OFF The voltage corresponding to point A is shifted to point A, where A is the amplitude of the input signal; in quadruple frequency mode, the parabolic characteristic curves of the two nFeFET cells are spaced apart by A, and the characteristic curve I of the first nFeFET cell is... OFF The voltage corresponding to the point is shifted to -A / 2, and the characteristic curve I of the second nFeFET unit is changed. OFF The voltage corresponding to the point shifts to position A / 2, where A is the amplitude of the input signal. The I0 of the two nFeFET cells in different frequency multiplication modes... OFF The current and voltage need to be adjusted to the positions shown in the table below: (where A is the amplitude of the input signal)

[0055]

[0056] like Figure 1 As shown in (b), the 4pFeFET structure includes two pFeFET cells, a resistor R2, and a capacitor C. out2 Two pFeFET cells are connected in parallel, and each pFeFET cell consists of two p-type FeFETs connected in series. The 4pFeFET structure includes M5, M6, M7, and M8. The gates of M5 and M6 are connected to word line WL3, and the gates of M7 and M8 are connected to word line WL4. Word line WL3 and word line WL4 are connected through an analog inverter. ScL2 is led out from the connection point of M5 and M7, and ScL3 is led out from the connection point of M6 and M8. The sources of M5 and M6 are connected to VDD through resistor R2. The drains of M7 and M8 are connected to VSS1 and VSS2 respectively. The sources of M5 and M6 are then connected to capacitor C. out1 Output signal V out .

[0057] The operating steps of the 4pFeFET structure are as follows:

[0058] (1) Before starting work, first confirm the required frequency multiplier, and write different values ​​to the FeFET according to the different multipliers. The multipliers include first multiplier, second multiplier, third multiplier or fourth multiplier.

[0059] (2) When writing to M5, set ScL2 to 0 and set ScL3 to the same voltage as WL3; when writing to M6, set ScL3 to 0 and set ScL2 to the same voltage as WL3, and write through WL3; when writing to M7, set VSS1 to 0 and set VSS2 to the same voltage as WL4; when writing to M8, set VSS2 to 0 and set VSS1 to the same voltage as WL4, and write through WL4.

[0060] (3) After writing different frequency multiplication modes, connect WL4 and WL3 through an analog inverter so that the signal on WL4 is inverted with the signal on WL3.

[0061] (4) During the frequency multiplication process, ScL2 and ScL3 are floated, and the signal is input from WL3 through capacitor C. out2 Output signal V out .

[0062] like Figure 3 As shown, by writing different values ​​to four p-type FeFETs, characteristic curves corresponding to different frequency multiplication modes are constructed. The characteristic curves of two pFeFET cells are formed by connecting the characteristic curves of two inverted p-type FeFETs in series, i.e., by superimposing the smaller values. The characteristic curves of the two pFeFET cells are both parabolas with downward openings, and the characteristic curves of the two pFeFET cells have the same shape. The characteristic curves of the 4pFeFET structure are formed by connecting the characteristic curves of two pFeFET cells in parallel, i.e., by superimposing the larger values. Using the microamp-level current of the pFeFETs, first frequency multiplication is achieved by utilizing the monotonic region of the characteristic curve; second frequency multiplication is achieved by utilizing the symmetrical, downward-opening parabolic region of the characteristic curve; third frequency multiplication is achieved by utilizing the centrally symmetrical double-strand curve region of the characteristic curve; and fourth frequency multiplication is achieved by utilizing the symmetrical triple-strand curve region of the characteristic curve. In the first frequency multiplication mode, the parabolic characteristic curves of the two pFeFET cells coincide, and the voltage corresponding to the maximum current point of these two characteristic curves is shifted to -A, where A is the amplitude of the input signal. In the second frequency multiplication mode, the parabolic characteristic curves of the two pFeFET cells coincide, and the voltage corresponding to the maximum current point of these two characteristic curves is shifted to 0V. In the third frequency multiplication mode, the parabolic characteristic curves of the two pFeFET cells are spaced 4A / 3 apart, and the voltage corresponding to the maximum current point of the first pFeFET cell's characteristic curve is shifted to -A / 3, while the voltage corresponding to the maximum current point of the second pFeFET cell's characteristic curve is shifted to A, where A is the amplitude of the input signal. In the fourth frequency multiplication mode, the parabolic characteristic curves of the two pFeFET cells are spaced A apart, and the voltage corresponding to the maximum current point of the first pFeFET cell's characteristic curve is shifted to -A / 2, while the voltage corresponding to the maximum current point of the second pFeFET cell's characteristic curve is shifted to A / 2, where A is the amplitude of the input signal. The table below shows the required voltage adjustment points for the maximum current points of each pFeFET cell in different frequency multiplication modes: (where A is the amplitude of the input signal).

[0063]

[0064] The 2nFeFET-2pFeFET structure includes Model 1 and Model 2, such as... Figure 1 As shown in (c), Model 1 is a low-power design, including two first complementary FeFET cells, resistor R3 and capacitor C. out3Two first complementary FeFET cells are connected in series, and each first complementary FeFET cell consists of a p-type FeFET and an n-type FeFET connected in parallel; Model 1 includes M9, M 10 M 11 and M 12 M9 and M 11 Gate connection word line WL5, M 10 and M 12 The gate word line WL6, ScL4 is led out from the connection point of the upper and lower first complementary FeFET cells, and the drain of M9 and M 10 The source of M is connected to VDD through resistor R3. 11 The source and M 12 The drain of M1 is connected to VSS, and the drain of M1 and the source of M2 are connected through capacitor C. out3 Output signal V out .

[0065] For Model 1 of the low-power design, the I0 of each complementary FeFET cell in different frequency multiplication modes. OFF The voltage adjustment position corresponding to the current is the same as that of the reconfigurable frequency multiplier in the 4nFeFET structure. The writing method for Model 1 is the same as that for the 4nFeFET structure. The specific operating steps of Model 1 include:

[0066] (1) Before starting work, first confirm the required frequency multiplier, and write different values ​​to the FeFET according to the different multipliers. The multipliers include first multiplier, second multiplier, third multiplier or fourth multiplier.

[0067] (2) For M9 and M 10 During writing, set ScL4 to 0, set VSS to the same voltage as WL5, and write through WL5 and WL6; for M 11 and M 12 When writing, set VSS to 0, set ScL4 to the same voltage as WL5, and write through WL5 and WL6 in the same way.

[0068] (3) After writing to different frequency multiplier modes, connect WL5 and WL6 directly;

[0069] (4) During the frequency multiplication process, ScL4 is floated, and signals are input to both WL5 and WL6 through capacitor C. out3 Output signal V out .

[0070] like Figure 2As shown, by performing different write operations on two n-type FeFETs and two p-type FeFETs, characteristic curves corresponding to different frequency doubling modes are constructed. The characteristic curve of the two complementary FeFET cells is formed by connecting the characteristic curves of an n-type FeFET and a p-type FeFET with in-phase inputs in parallel, i.e., by superimposing the larger values. The characteristic curves of the two complementary FeFET cells are both parabolas with upward openings, and the characteristic curves of the two complementary FeFET cells have the same shape. The characteristic curve of Model 1 is formed by connecting the characteristic curves of the two complementary FeFET cells in series, i.e., by superimposing the smaller values.

[0071] Utilizing the nanoampere-level current in the subthreshold region of complementary FeFETs, frequency doubling is achieved using the monotonic region of the characteristic curve; second harmonic doubling is achieved using the symmetrical, upward-opening parabolic region of the characteristic curve; third harmonic doubling is achieved using the centrally symmetrical double-strand curve region of the characteristic curve; and fourth harmonic doubling is achieved using the symmetrical triple-strand curve region of the characteristic curve. In frequency doubling mode, the parabolic characteristic curves of the two complementary FeFET cells coincide, and the I values ​​of these two characteristic curves are combined. OFF The voltage corresponding to the point shifts to -A, where A is the amplitude of the input signal; in the frequency doubling mode, the parabolic characteristic curves of the two complementary FeFET cells coincide, and these two characteristic curves I OFF The voltage corresponding to the point is shifted to 0V; in triple frequency mode, the parabolic characteristic curves of the two complementary FeFET cells are spaced 4A / 3 apart, and the characteristic curve I of the first complementary FeFET cell is... OFF The voltage corresponding to the point is shifted to -A / 3, and the characteristic curve I of the second complementary FeFET cell is changed. OFF The voltage corresponding to point A is moved to point A, where A is the amplitude of the input signal; in the quadruple frequency mode, the parabolic characteristic curves of the two complementary FeFET cells are spaced apart by A, and the characteristic curve I of the first complementary FeFET cell is... OFF The voltage corresponding to point I is shifted to -A / 2, thus changing the characteristic curve I of the second complementary FeFET cell. OFF The voltage corresponding to the point moves to position A / 2, where A is the amplitude of the input signal.

[0072] like Figure 1 As shown in (d), Model 2 is a high-performance design, including two second complementary FeFET cells, resistor R4 and capacitor C. out4 Two second complementary FeFET cells are connected in parallel, and each second complementary FeFET cell consists of a p-type FeFET and an n-type FeFET connected in series; Model 2 includes M 13 M 14 M 15 and M 16 M13 and M 14 Gate connection word line WL7, M 15 and M 16 Gate connection word line WL8, M 13 and M 15 ScL5 and M are led out from the connection point. 14 and M 16 The ScL6 connector is brought out at the connection point to facilitate writing to the FeFET. 13 and M 14 The source of M is connected to VDD through resistor R4. 15 and M 16 The source terminals are connected to VSS1 and VSS2 respectively, M 13 and M 14 The source electrode is then connected to capacitor C. out4 Output signal V out .

[0073] For Model 2 of the high-performance design, the voltage corresponding to the maximum current point of each complementary FeFET cell in different frequency multiplication modes needs to be adjusted to the same position as the reconfigurable frequency multiplier of the 4pFeFET structure. The writing method for Model 2 is the same as that for the 4pFeFET structure. The specific operating steps of Model 2 include:

[0074] (1) Before starting work, first confirm the required frequency multiplier, and write different values ​​to the FeFET according to the different multipliers. The multipliers include first multiplier, second multiplier, third multiplier or fourth multiplier.

[0075] (2) For M 13 When writing, set ScL5 to 0 and set ScL6 to the same voltage as WL7; for M 14 During writing, set ScL6 to 0, set ScL5 to the same voltage as WL7, and write through WL7; for M... 15 When writing, set VSS1 to 0 and set VSS2 to the same voltage as WL8; for M 16 When writing, set VSS2 to 0 and set VSS1 to the same voltage as WL8, then write through WL8;

[0076] (3) After writing to different frequency multiplier modes, connect WL7 and WL8 directly;

[0077] (4) During the frequency multiplication process, ScL5 and ScL6 are floated, and a common input signal is given to WL7 and WL8, which is then passed through capacitor C. out4 Output signal V out .

[0078] like Figure 3As shown, by performing different write operations on two n-type FeFETs and two p-type FeFETs, characteristic curves corresponding to different frequency doubling modes are constructed. The characteristic curves of the two complementary FeFET cells are both parabolas with downward openings, and the characteristic curves of the two complementary FeFET cells have the same shape; the characteristic curve of Model 2 is formed by superimposing the characteristic curves of the two complementary FeFET cells in parallel, i.e., taking the larger value.

[0079] Using the microampere-level current of complementary FeFETs, frequency doubling is achieved by utilizing the monotonic region in the characteristic curve; frequency doubling is achieved by utilizing the symmetrical, downward-opening parabolic region in the characteristic curve; frequency tripling is achieved by utilizing the centrally symmetrical double-strand curve region in the characteristic curve; and frequency quadrupleling is achieved by utilizing the symmetrical triple-strand curve region in the characteristic curve. In the first frequency multiplication mode, the parabolic characteristic curves of the two complementary FeFET cells coincide, and the voltage corresponding to the maximum current point of these two characteristic curves is shifted to -A, where A is the amplitude of the input signal. In the second frequency multiplication mode, the parabolic characteristic curves of the two complementary FeFET cells coincide, and the voltage corresponding to the maximum current point of these two characteristic curves is shifted to 0V. In the third frequency multiplication mode, the parabolic characteristic curves of the two complementary FeFET cells are spaced 4A / 3 apart, and the voltage corresponding to the maximum current point of the characteristic curve of the first complementary FeFET cell is shifted to -A / 3, and the voltage corresponding to the maximum current point of the characteristic curve of the second complementary FeFET cell is shifted to A, where A is the amplitude of the input signal. In the fourth frequency multiplication mode, the parabolic characteristic curves of the two complementary FeFET cells are spaced A apart, and the voltage corresponding to the maximum current point of the characteristic curve of the first complementary FeFET cell is shifted to -A / 2, and the voltage corresponding to the maximum current point of the characteristic curve of the second complementary FeFET cell is shifted to A / 2, where A is the amplitude of the input signal.

[0080] In summary, the three reconfigurable frequency multiplier structures proposed in this invention significantly simplify the circuit area compared to traditional frequency multiplication techniques such as phase-locked loops, requiring only a minimum of four transistors to achieve the frequency multiplication effect. Furthermore, the simple circuit structure also significantly reduces power consumption. By fully utilizing the storage characteristics of FeFETs, multiple FeFETs are connected in parallel or series to form characteristic curves capable of achieving second, third, and fourth frequency multiplication. The low power consumption of nFeFETs at their operating point is fully utilized to achieve a low-power reconfigurable frequency multiplier. The strong driving capability of pFeFETs is fully utilized to achieve a high-frequency reconfigurable frequency multiplier. The complementary characteristics of nFeFETs and pFeFETs are fully utilized to achieve a simple circuit structure that enables low-power operation or high-frequency reconfigurable frequency multipliers. This invention employs 4nFeFET, 4pFeFET, and 2nFeFET-2pFeFET structures, respectively. Compared to traditional frequency multiplier circuits, this invention has significant advantages in circuit area, power consumption, and reconfigurability.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A FeFET-based reconfigurable frequency multiplier, characterized in that, The reconfigurable frequency multiplier includes several FeFET structures, wherein the FeFET structure is one of a 4nFeFET structure, a 4pFeFET structure, or a 2nFeFET-2pFeFET structure, wherein... The 4nFeFET structure includes two nFeFET cells, a resistor R1, and a capacitor C. out1 Two nFeFET cells are connected in series, and each nFeFET cell includes two parallel n-type FeFETs; the 4nFeFET structure includes M1, M2, M3 and M4, with gate word lines WL1 for M1 and M3, and gate word lines WL2 for M2 and M4. ScL1 is led out from the connection point of the two nFeFET cells. The drains of M1 and M2 are connected to VDD through resistor R1, and the sources of M3 and M4 are connected to VSS. The drains of M1 and M2 are then connected to capacitor C. out Output signal V out During frequency multiplication, word line WL1 and word line WL2 are connected through an analog inverter. The 4pFeFET structure includes two pFeFET units, a resistor R2, and a capacitor C. out2 Two pFeFET cells are connected in parallel, and each pFeFET cell consists of two p-type FeFETs connected in series. The 4pFeFET structure includes M5, M6, M7, and M8. The gates of M5 and M6 are connected to word line WL3, and the gates of M7 and M8 are connected to word line WL4. Word line WL3 and word line WL4 are connected through an analog inverter. ScL2 is led out from the connection point of M5 and M7, and ScL3 is led out from the connection point of M6 and M8. The sources of M5 and M6 are connected to VDD through resistor R2. The drains of M7 and M8 are connected to VSS1 and VSS2 respectively. The sources of M5 and M6 are then connected to capacitor C. out1 Output signal V out ; The 2nFeFET-2pFeFET structure includes Model 1 and Model 2. Model 1 includes two first complementary FeFET cells, resistor R3, and capacitor C. out3 Model 1 consists of two first complementary FeFET cells connected in series, each consisting of a p-type FeFET and an n-type FeFET connected in parallel; Model 2 includes two second complementary FeFET cells, resistor R4, and capacitor C. out4 Two second complementary FeFET cells are connected in parallel, and each second complementary FeFET cell consists of a p-type FeFET and an n-type FeFET connected in series; The first model includes M9 and M 10 M 11 and M 12 M9 and M 11 Gate connection word line WL5, M 10 and M 12 The gate word line WL6, ScL4 is led out from the connection point of the upper and lower first complementary FeFET cells, and the drain of M9 and M 10 The source of M is connected to VDD through resistor R3. 11 The source and M 12 The drain of M1 is connected to VSS, and the drain of M1 and the source of M2 are connected through capacitor C. out3 Output signal V out ; The second model includes M 13 M 14 M 15 and M 16 M 13 and M 14 Gate connection word line WL7, M 15 and M 16 Gate connection word line WL8, M 13 and M 15 ScL5 and M are led out from the connection point. 14 and M 16 The ScL6 connector is brought out at the connection point to facilitate writing to the FeFET. 13 and M 14 The source of M is connected to VDD through resistor R4. 15 and M 16 The source terminals are connected to VSS1 and VSS2 respectively, M 13 and M 14 The source electrode is then connected to capacitor C. out4 Output signal V out .

2. The FeFET-based reconfigurable frequency multiplier of claim 1, wherein, The operation steps of the 4nFeFET structure are as follows: Step 1: Before starting work, first determine the required frequency multiplication factor, and write different values ​​to the FeFET according to different multiplication factors; Step 2: When writing to M1 and M2, set ScL1 to 0 and set VSS to the same voltage as WL1, then write through WL1 and WL2; when writing to M3 and M4, set VSS to 0 and set ScL1 to the same voltage as WL1, then write through WL1 and WL2 in the same way. Step 3: After writing for different frequency multiplication modes, connect WL2 and WL1 through an analog inverter so that the signal on WL2 is inverted with the signal on WL1; Step 4: During frequency doubling, ScLl is floating, from the input signal at WL1, through the capacitor C out1 Output signal V out .

3. The FeFET-based reconfigurable frequency multiplier of claim 1, wherein, The operation steps of the 4pFeFET structure are as follows: Step 1: Before starting work, first determine the required frequency multiplication factor, and write different values ​​to the FeFET according to different multiplication factors; Step 2: When writing to M5, set ScL2 to 0 and set ScL3 to the same voltage as WL3; when writing to M6, set ScL3 to 0 and set ScL2 to the same voltage as WL3, then write through WL3; when writing to M7, set VSS1 to 0 and set VSS2 to the same voltage as WL4; when writing to M8, set VSS2 to 0 and set VSS1 to the same voltage as WL4, then write through WL4. Step 3: After writing for different frequency multiplication modes, connect WL4 and WL3 through an analog inverter so that the signal on WL4 is inverted with the signal on WL3; Step 4: During the frequency multiplication process, ScL2 and ScL3 are floated, and the signal is input from WL3 through capacitor C. out2 Output signal V out .

4. The FeFET-based reconfigurable frequency multiplier of claim 1, wherein, The writing method of Model 1 is the same as that of the 4nFeFET structure. The specific operation steps of Model 1 include: Step 1: Before starting work, first determine the required frequency multiplication factor, and write different values ​​to the FeFET according to different multiplication factors; Step 2: For M9 and M 10 During writing, set ScL4 to 0, set VSS to the same voltage as WL5, and write through WL5 and WL6; for M 11 and M 12 When writing, set VSS to 0, set ScL4 to the same voltage as WL5, and write through WL5 and WL6 in the same way. Step 3: After writing to different multiplier modes, connect WL5 and WL6 directly; Step 4: In the frequency doubling process, ScL4 is floating, and the input signal is input to WL5 and WL6 together, and the output signal V out3 output signal V out .

5. The FeFET-based reconfigurable frequency multiplier of claim 1, wherein, The writing method of Model 2 is the same as that of the 4pFeFET structure. The specific operation steps of Model 2 include: Step 1: Before starting work, first determine the required frequency multiplication factor, and write different values ​​to the FeFET according to different multiplication factors; Step 2: For M 13 When writing, set ScL5 to 0 and set ScL6 to the same voltage as WL7; for M 14 During writing, set ScL6 to 0, set ScL5 to the same voltage as WL7, and write through WL7; for M... 15 When writing, set VSS1 to 0 and set VSS2 to the same voltage as WL8; for M 16 When writing, set VSS2 to 0 and set VSS1 to the same voltage as WL8, then write through WL8; Step 3: After writing to different multiplier modes, connect WL7 and WL8 directly; Step 4: During the frequency multiplication process, ScL5 and ScL6 are floated, and a signal is input to both WL7 and WL8 through capacitor C. out4 Output signal V out .

6. The FeFET-based reconfigurable frequency multiplier of any of claims 2-5, wherein, The multiplier includes first harmonic, second harmonic, third harmonic, or fourth harmonic.

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