Delay measurement circuit and control method thereof

Abstract

The present disclosure relates to a time delay measurement circuit and a control method thereof, wherein a control link module is connected to an output end thereof, and is configured to generate a plurality of control signals with a period of T according to a received first enable signal; a target oscillation module receives a second enable signal which is delayed from the first enable signal by a first preset threshold; each target unit in the target oscillation module is configured to be disconnected from a ground end / supply end for a first preset time T1 and then connected to the ground end / supply end for a second preset time T2 according to the received control signal, the first preset time T1 is a time for a level of the target unit to flip, and the second preset time T2 is a time for the target unit to maintain a logic level, so as to reduce a leakage current of the target unit in the first preset time T1; T1+T2=T / 2; N is an odd number; and the action current between adjacent two target units is prevented from affecting each other, so as to improve the performance and reliability of the ring oscillator.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and to, but is not limited to, a delay measurement circuit and its control method. Background Technology

[0002] A ring oscillator is generally a ring structure formed by connecting the output and input terminals of three or more odd-numbered inverters end to end. Ring oscillators have advantages such as simple circuitry, easy start-up, and easy integration, and are widely used in high-frequency oscillators inside integrated circuits, as well as simple oscillators in ordinary digital circuits.

[0003] However, for ring oscillators that employ complementary metal-oxide-semiconductor (CMOS) NOT gates, the operating currents between adjacent stages can affect each other, making it difficult to determine the electrical parameters of each inverter stage and reducing the performance and reliability of each inverter stage. Summary of the Invention

[0004] Therefore, it is necessary to provide a delay measurement circuit and its control method to address the technical problems mentioned above, so as to at least improve the performance and reliability of the ring oscillator.

[0005] To achieve the above and other objectives, embodiments of this disclosure provide a delay measurement circuit, including a control oscillation module and a target oscillation module. The control link module is configured such that its input terminal is connected to its output terminal, for receiving a first enable signal, and sequentially generating a plurality of control signals with a period time of T according to the first enable signal. The target oscillation module is configured such that its input terminal is connected to its output terminal, for receiving a second enable signal, the second enable signal being delayed by a first preset threshold ΔT compared to the first enable signal. The target oscillation module includes N series-connected target units. Each target unit is used to disconnect from the ground / power supply terminal within a first preset time T1 according to the received control signal, and then reconnect to the ground / power supply terminal within a second preset time T2. The first preset time T1 is the time for the target unit level to flip, and the second preset time T2 is the time for the target unit to maintain a logic level, thereby reducing the leakage current of the target unit within the first preset time T1; T1 + T2 = T / 2; N is an odd number.

[0006] The delay measurement circuit in the above embodiment sets the control oscillation module to sequentially generate several control signals with a period of time T according to the first enable signal, and sets the target oscillation module to trigger the action of its target units at each level in response to the second enable signal. This allows each target unit in the target oscillation module to disconnect from the target potential within a first preset time T1 according to the received control signal, and then connect to the target potential within a second preset time T2. The target unit maintains a logic level within the second preset time T2 to reduce the leakage current during the level flipping period of the target unit in response to the input signal within the first preset time T1, and to avoid mutual interference between the operating currents of adjacent target units. This improves the accuracy of the electrical parameters of each target unit in the delay measurement circuit and enhances the performance and reliability of the ring oscillator.

[0007] In some embodiments, the target oscillation module outputs a target output signal at its output terminal; the target oscillation module includes a first logic control unit and a target link unit, the first logic control unit being configured to: have a first input terminal for receiving the target output signal, a second input terminal for receiving the second enable signal, and an output terminal for outputting a first initial delay signal; the target link unit is configured to: have a first input terminal for receiving the first initial delay signal, and a second input terminal for receiving a control signal, for generating the target output signal based on the control signal and the first initial delay signal.

[0008] In some embodiments, the first logic control unit includes a first NAND gate, which is used to receive the target output signal and output a first initial delay signal when the second enable signal is valid, wherein the level state of the first initial delay signal is opposite to that of the target output signal.

[0009] In some embodiments, the target link unit includes N series target units; N>2; the input terminal of the first target unit is connected to the output terminal of the first logic control unit to receive a first initial delay signal; the output terminal of the last target unit serves as the output terminal of the target link unit; each target unit is further configured such that: the control terminal is used to receive a corresponding control signal, the first terminal is connected to a first potential, and the second terminal is connected to the target potential.

[0010] In some embodiments, the target unit includes a sub-target unit and a controllable switch unit. The sub-target unit is configured such that: its input terminal is connected to the output terminal of the adjacent previous target unit, its first terminal is connected to the first potential, and its second terminal is connected to the target potential via the controllable switch unit; when the control signal is within a first level range, the controllable switch unit is disconnected within a first preset time T1, and when the control signal is within a second level range, the controllable switch unit is turned on within a second preset time T2.

[0011] In some embodiments, the target potential includes a ground terminal; the controllable switching unit includes a first switching unit; the first switching unit is configured such that: a first terminal is connected to the sub-target unit, a control terminal receives a corresponding control signal, and a second terminal is connected to the ground terminal; the potential difference between the first potential and the ground terminal is greater than zero.

[0012] In some embodiments, the target potential includes a power supply terminal; the controllable switching unit includes a second switching unit; the second switching unit is configured such that: a first terminal is connected to the power supply terminal, a control terminal receives a corresponding control signal, and a second terminal is connected to the sub-target unit; the potential difference between the power supply terminal and the first potential is greater than zero.

[0013] In some embodiments, the sub-target unit includes a first transistor and a second transistor. The first transistor is configured such that: a first terminal is connected to a first potential, a control terminal is connected to the output terminal of the adjacent previous target unit, and a second terminal serves as the output terminal of the current target unit; the second transistor is configured such that: a first terminal is connected to the second terminal of the first transistor, the second terminal is connected to a ground terminal via a first switching unit, and a control terminal is connected to the control terminal of the first transistor.

[0014] In some embodiments, the first switching unit includes a third transistor, which is configured such that: a first terminal is connected to a second terminal of a second transistor, a control terminal receives a corresponding control signal, and the second terminal is connected to a ground terminal; wherein, the third transistor is used to turn on in response to the control signal after being turned off within a first preset time T1, and then turn on within a second preset time T2.

[0015] In some embodiments, the sub-target unit includes a first transistor and a second transistor. The first transistor is configured such that: a first terminal is connected to the second terminal of the second switching unit, a control terminal is connected to the output terminal of the adjacent previous target unit, and the second terminal serves as the output terminal of the current target unit; the second transistor is configured such that: a first terminal is connected to the second terminal of the first transistor, the second terminal is connected to a ground terminal, and a control terminal is connected to the control terminal of the first transistor.

[0016] In some embodiments, the second switching unit includes a fourth transistor, which is configured such that: a first terminal is connected to a power supply terminal, a control terminal receives a corresponding control signal, and a second terminal is connected to the first terminal of the first transistor; wherein the fourth transistor is used to turn on in response to the control signal after being turned off within a first preset time T1, and then turn on within a second preset time T2.

[0017] In some embodiments, the delay measurement circuit further includes a delay module coupled to the target oscillation module. The delay module is configured to: have an input terminal for receiving a first enable signal and an output terminal connected to the input terminal of the target oscillation module, for generating a second enable signal based on the first enable signal and providing it to the target oscillation module.

[0018] In some embodiments, the output terminal of the control oscillation module outputs an initial output signal. The control oscillation module includes a second logic control unit and a control link unit. The second logic control unit is configured to: have a first input terminal for receiving the initial output signal, a second input terminal for receiving a first enable signal, and an output terminal for outputting a first control signal. The control link unit includes N series-connected control units, which are used to sequentially generate N-1 control signals and the initial output signal based on the received first control signal. The first-level control unit is connected to the output terminal of the second logic control unit, and the output terminal of the last-level control unit serves as the output terminal of the control oscillation module. The input terminal of each control unit is connected to the control terminal of the corresponding target unit.

[0019] In some embodiments, the second logic control unit includes a second NAND gate, which is configured to receive an initial output signal and output a first control signal when the first enable signal is valid, the first control signal having a level opposite to that of the initial output signal.

[0020] In some embodiments, the control unit includes a first inverter; the N-stage series-connected first inverters are used to sequentially generate N-1 control signals and an initial output signal according to the received first control signal, wherein the input terminal of each first inverter is connected to the control terminal of the corresponding target unit.

[0021] In some embodiments, T1+MT≤△T<(M+0.5)T, where M is a positive integer.

[0022] In some embodiments, the delay measurement circuit further includes an address circuit, which receives an address signal and generates a plurality of first enable signals based on the address signal to provide to the control oscillation module, thereby triggering the corresponding control oscillation module and target oscillation module to operate.

[0023] A second aspect of this disclosure provides a delay measurement circuit control method, comprising:

[0024] Based on the control oscillation module responding to the first enable signal and sequentially generating several control signals with a period of time T;

[0025] A second enable signal is generated based on the first enable signal, and the second enable signal is delayed by a first preset threshold ΔT compared with the first enable signal;

[0026] In the target oscillation module, each target unit disconnects from the target potential within a first preset time T1 according to the received control signal, and then connects to the target potential within a second preset time T2. The target unit maintains a logic level within the second preset time T2. The first preset time T1 is the time for the target unit level to flip, so as to reduce the leakage current of the target unit within the first preset time T1; T1+T2=T / 2; N is an odd number. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of a delay measurement circuit provided in the first embodiment of this disclosure;

[0029] Figure 2a This is a schematic diagram of a delay measurement circuit provided in the second embodiment of this disclosure;

[0030] Figure 2b This is a schematic diagram of a delay measurement circuit provided in the third embodiment of this disclosure;

[0031] Figure 3a This is a schematic diagram of a delay measurement circuit provided in the fourth embodiment of this disclosure;

[0032] Figure 3b This is a schematic diagram of a delay measurement circuit provided in the fifth embodiment of this disclosure;

[0033] Figure 4a This is a circuit diagram of a delay measurement circuit provided in the first embodiment of the present disclosure;

[0034] Figure 4b This is a circuit diagram of a delay measurement circuit provided in the second embodiment of the present disclosure;

[0035] Figure 5 This is a schematic diagram of the working timing of a delay measurement circuit provided in one embodiment of the present disclosure;

[0036] Figure 6a This is a circuit diagram of a delay measurement circuit provided in the third embodiment of this disclosure;

[0037] Figure 6b This is a circuit diagram of a delay measurement circuit provided in the fourth embodiment of the present disclosure;

[0038] Figure 7a This is a circuit diagram of a delay measurement circuit provided in the fifth embodiment of this disclosure;

[0039] Figure 7b This is a circuit diagram of a delay measurement circuit provided in the sixth embodiment of this disclosure;

[0040] Figure 8This is a flowchart illustrating a delay measurement circuit control method provided in one embodiment of the present disclosure.

[0041] Explanation of reference numerals in the attached figures:

[0042] 100. Delay measurement circuit; 10. Control oscillation module; 102. Second logic control unit; 101. Delay link unit; 20. Target oscillation module; 21. First logic control unit; 22. Target link unit; 2201. Sub-target unit; 2202. First switching unit; 30. Delay module; 40. Address circuit; 50. Frequency divider module; 60. Output buffer module. Detailed Implementation

[0043] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0045] Additionally, certain terms used throughout the specification and following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements with different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". Similarly, the term "connection" is intended to express either indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection may be accomplished through a direct electrical connection or through an indirect electrical connection with other devices and connectors.

[0046] It should be understood that although the terms "first," "first," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a first element, and similarly, a first element may be referred to as a first component.

[0047] Please note that in the embodiments of this disclosure, the amplitude of the first potential VDD1 is VDD1, the amplitude of the second potential VDD2 is VDD2, and the amplitude of the third potential VDD3 is VDD3; the grounding terminal includes, but is not limited to, potential points with a potential less than the input voltage.

[0048] Please refer to Figure 1 In one embodiment of this disclosure, a delay measurement circuit 100 is provided, including a control oscillation module 10 and a target oscillation module 20. The control oscillation module 10 is configured such that: a first input terminal is connected to the output terminal of the control oscillation module 10, and a second input terminal receives a first enable signal Ens, used to sequentially generate a plurality of control signals ctli with a period duration of T according to the first enable signal Ens; the target oscillation module 20 is configured such that: a first input terminal is connected to the output terminal of the target oscillation module 20, and a second input terminal receives a second enable signal Delay_Ens, the second enable signal Delay_Ens being delayed by a first preset threshold ΔT compared to the first enable signal Ens; wherein, the target oscillation module 20 includes N levels of target units connected in series, such as target units 221, ..., target units 22i, ... and target units 22N, each target unit 22i generating a delay measurement signal ctli according to the received control signal ctli. After being disconnected from the target potential V0 within the first preset time T1, the target unit 22i is connected to the target potential V0 within the second preset time T2. The target unit 22i maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22i in response to the input signal within the first preset time T1. Before the target unit 22i recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to be connected to the target potential V0 within the second preset time T2, so as not to affect the dynamic current change of the target unit 22i during the recovery period. i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0049] As an example, please continue to refer to Figure 1During the static period of the delay measurement circuit, the input current i_1 of the drive power port in the target unit 22i can be measured, and during the oscillation period of the delay measurement circuit, the input current i_2 of the drive power port in the target unit 22i can be measured. The difference i_c between current i_2 and current i_1 is the effective drive current of the delay measurement circuit. The drive voltage of the drive power port is set to V_d. Based on the effective drive current i_c and drive voltage V_d of the delay measurement circuit, the equivalent resistance of the delay measurement circuit can be obtained. Then, based on the quotient of the delay time and the equivalent resistance of the delay measurement circuit, the equivalent capacitance of the delay measurement circuit can be obtained. Since each target unit 22i in the target oscillation module 20 disconnects from the target potential V0 within the first preset time T1 according to the received control signal ctli, and then connects to the target potential V0 within the second preset time T2, and the target unit 22i maintains a logic level within the second preset time T2, the leakage current generated by the adjacent previous target unit during the level flipping of the target unit 22i in response to the input signal within the first preset time T1 is reduced. Furthermore, before the target unit 22i recovers, the corresponding control signal has already controlled the adjacent previous target unit to connect to the target potential V0 within the second preset time T2, so it will not affect the dynamic current change of the target unit 22i during the recovery period; i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0050] For example, please refer to Figures 2a-2bThe target potential V0 may include a ground terminal GND or a power supply terminal VDD2. The output terminal of the target oscillation module 20 outputs a target output signal outd. The target oscillation module 20 includes a first logic control unit 21 and a target link unit 22. The first logic control unit 21 is configured such that: a first input terminal is connected to the output terminal of the target oscillation module 20 to receive the target output signal outd; a second input terminal receives a second enable signal Delay_Ens, used to generate a first initial delay signal s1 based on the second enable signal Delay_Ens and the target output signal outd. The target link unit 22 is configured such that: a first input terminal is connected to the output terminal of the first logic control unit 21 to receive the first initial delay signal s1; a second input terminal receives a control signal, used to generate a target output signal outd based on the control signal and the first initial delay signal. In the target link unit 22, the target unit 22i generates the target output signal outd based on the received control signal ctli at a first preset time. After being disconnected from the ground terminal GND / power terminal VDD2 within T1, it is connected to the ground terminal GND / power terminal VDD2 within the second preset time T2. The target unit 22i maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22i in response to the input signal within the first preset time T1. Before the target unit 22i recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to be connected to the ground terminal GND / power terminal VDD2 within the second preset time T2, so as not to affect the dynamic current change of the target unit 22i during the recovery state. i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0051] As an example, please continue to refer to Figures 2a-2bThe target link unit 22 includes N series-connected target units 221, ..., target units 22i, ... and target units 22N. The first terminals of target units 221, ..., target units 22i, ... and target units 22N are all connected to a first potential VDD1, and their second terminals are connected to ground GND / power supply VDD2. The input terminal of the first-stage target unit 221 is connected to the output terminal of the first logic control unit 21 to receive a first initial delay signal s1. The output terminal of the last-stage target unit 22N serves as the output terminal of the target link unit 22 to output a target output signal outd. Target unit 22i is configured such that: its control terminal receives the corresponding control signal ctli; its first terminal is connected to the first potential; and its second terminal is connected to ground GND / power supply VDD2. Target unit 22i, according to the received control signal ctli, communicates with ground GND / power supply VDD2 within a first preset time T1. After DD2 is disconnected, it is connected to the ground terminal GND / power terminal VDD2 within the second preset time T2. The target unit 22i maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22i in response to the input signal within the first preset time T1. Before the target unit 22i recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to connect to the ground terminal GND / power terminal VDD2 within the second preset time T2, so as not to affect the dynamic current change of the target unit 22i during the recovery period; i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0052] As an example, please continue to refer to Figures 2a-2bThe control oscillation module 10 includes a second logic control unit 102 and a control link unit 101. The second logic control unit 102 is configured such that: its first input terminal is connected to the output terminal of the control link unit 101 to receive the initial output signal out0; and its second input terminal receives a first enable signal Ens, used to generate a first control signal ctl1 based on the first enable signal Ens and the initial output signal out0. The control link unit 101 includes control units 121, ..., 12i, ... and 12N connected in series. The first terminals of control units 121, ..., 12i, ... and 12N are all connected to a third potential VDD3. The potential difference between the first potential VDD1 and the third potential VDD3 can be set to be greater than 0. The first control signal ctl1 is used to trigger the first control unit 121 to generate a second control signal ctl2, ..., the i-th control signal ctli is used to trigger the i-th control unit 12i to generate the (i+1)-th control signal ctli+1, ..., the N-th control signal ctlN is used to trigger the N-th control unit. 12N generates an initial output signal out0; causing the target unit 22i to disconnect from the ground terminal GND / power terminal VDD2 within the first preset time T1 according to the received control signal ctli, and then connect to the ground terminal GND / power terminal VDD2 within the second preset time T2. The target unit 22i maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22i in response to the input signal within the first preset time T1. Before the target unit 22i recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to connect to the ground terminal GND / power terminal VDD2 within the second preset time T2, so as not to affect the dynamic current change of the target unit 22i during the recovery state; i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0053] As an example, please continue to refer to Figures 2a-2b The number of control units in the control oscillation module 10 can be determined according to the actual needs of the specific application scenario. Those skilled in the art can undoubtedly determine that all equivalent / identical modifications made under the inventive concept of this disclosure are within the protection scope of the embodiments of this disclosure.

[0054] For example, please refer to Figure 3aThe target unit 22j includes a sub-target unit 2201 and a first switch unit 2202. The sub-target unit 2201 is configured such that its input terminal is connected to the output terminal of the adjacent preceding target unit, and its first terminal is connected to a first potential VDD1. The first switch unit 2202 is configured such that its first terminal is connected to the sub-target unit 2201, its control terminal receives the corresponding control signal, and its second terminal is connected to the ground terminal GND. When the control signal ctlj is within a first level range, for example, a low level, the first switch unit 2202 is disconnected from the ground terminal GND within a first preset time T1. Afterward, when the control signal ctlj is within a second level range, for example, a high level, the first switch unit 2202 is connected to the ground terminal GND again within a second preset time T2, and the sub-target unit 2201... 01. The logic level is maintained within the second preset time T2 to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22j in response to the input signal within the first preset time T1. Before the target unit 22j recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to be connected to the ground terminal GND within the second preset time T2, so as not to affect the dynamic current change of the target unit 22j during the recovery state; j∈[2,N], j and N are both integers greater than or equal to 2, N is an odd number, T1+T2=T / 2; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0055] For example, please refer to Figure 3bThe target unit 22j includes a sub-target unit 2201 and a second switching unit 2203. The sub-target unit 2201 is configured such that its input terminal is connected to the output terminal of the adjacent preceding target unit, and its first terminal is connected to a first potential VDD1. The second switching unit 2203 is configured such that its input terminal is connected to the second terminal of the sub-target unit 2201, its control terminal receives the corresponding control signal, and its first terminal is connected to the power supply terminal VDD2. When the control signal ctlj is within the first level range, for example, a high level, the second switching unit 2203 is disconnected within a first preset time T1. Afterward, when the control signal ctlj is within the second level range, for example, a low level, the second switching unit 2203 is connected to the power supply terminal VDD2 again within a second preset time T2, and the sub-target unit 2201 remains connected within the second preset time T2. The logic level is used to reduce the leakage current generated by the adjacent previous stage target unit during the level flipping of the target unit 22j in response to the input signal within the first preset time T1. Before the target unit 22j recovers, the corresponding control signal has already controlled the adjacent previous stage target unit to be connected to the power supply terminal VDD2 within the second preset time T2, so as not to affect the dynamic current change of the target unit 22j during the recovery state; j∈[2,N], j and N are both integers greater than or equal to 2, N is an odd number, T1+T2=T / 2; the potential difference between the power supply terminal VDD2 and the first potential VDD1 is greater than zero; to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100, and improving the performance and reliability of the ring oscillator.

[0056] For example, please refer to Figures 4a-4bThe target link unit includes N-stage target units 221, 222, 223, 224, and 225 connected in series. The input terminal of the first-stage target unit 221 is connected to the output terminal of the first logic control unit 21 to receive the first initial delay signal s1. The output terminal of the last-stage target unit 225 serves as the output terminal of the target link unit 22 to output the target output signal outd. The target unit 22k is configured such that: the control terminal is used to receive the corresponding control signal ctlk; the first terminal is connected to the first potential VDD1; and the second terminal is connected to the ground terminal GND. The first logic control unit 21 is configured as follows: The first input terminal is connected to the output terminal of the target oscillation module 20 to receive the target output signal outd. The second input terminal receives the second enable signal Delay_Ens, which is used to generate a first initial delay signal s1 based on the second enable signal Delay_Ens and the target output signal outd. The level flipping in the first initial delay signal s1 is used to trigger the level flipping action of the output signal of the first-stage target unit 221. The level flipping of the output signal of the first-stage target unit 221 triggers the level flipping action of the output signal of the second-stage target unit 222. The level flipping of the output signal of the second-stage target unit 222 triggers the level flipping action of the output signal of the third-stage target unit 222. The level-flipping action of the output signal of target unit 223 at level 3 triggers the level-flipping action of the output signal of target unit 224 at level 4, which in turn triggers the output signal of target unit 225 at level 5 to output the target output signal outd. Target unit 22k disconnects from ground terminal GND / power terminal VDD2 within a first preset time T1 according to the received control signal ctlk, and then reconnects to ground terminal GND / power terminal VDD2 within a second preset time T2. Target unit 22k maintains a logic level during the second preset time T2 to reduce the target... During the level flipping of the input signal in unit 22k, the leakage current generated by the adjacent previous stage target unit is controlled by the corresponding control signal before the target unit 22k is restored to the state. The adjacent previous stage target unit is connected to the ground terminal GND / power terminal VDD2 in the second preset time T2, which will not affect the dynamic current change of target unit 22k during the restoration state. k∈[2,5], k is an integer, to avoid mutual influence between the operating currents of adjacent two stage target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0057] As an example, please continue to refer to Figures 4a-4b The number of control units in the control oscillation module can be determined according to the actual needs of the specific application scenario. Those skilled in the art can undoubtedly determine that all equivalent / identical modifications made under the inventive concept of this disclosure are within the protection scope of the embodiments of this disclosure.

[0058] For example, please refer to Figure 3a , Figure 4a and Figure 5The sub-target unit 2201 includes a first transistor M11 and a second transistor M21. The first switching unit 2202 includes a third transistor M3. The third transistor M3 is configured such that: its first terminal is connected to the sub-target unit 2201, its control terminal receives a corresponding control signal, and its second terminal is connected to the ground terminal GND; wherein, the third transistor M3 is used to disconnect within a first preset time T1 and then turn on within a second preset time T2 in response to the corresponding control signal. The first transistor M11 is configured such that: its first terminal is connected to a first potential VDD1, its control terminal is connected to the output terminal of the adjacent previous target unit, and its second terminal serves as the output terminal of the current target unit; the second transistor M21 is configured such that: its first terminal is connected to the second terminal of the first transistor M11, its control terminal is connected to the control terminal of the first transistor M11, and its second terminal is connected to the ground terminal GND via the third transistor M3. The first logic control unit 21 is configured such that: a first input terminal is connected to the output terminal of the target oscillation module 20 to receive the target output signal outd; and a second input terminal receives a second enable signal Delay_Ens, used to generate a first initial delay signal s1 based on the second enable signal Delay_Ens and the target output signal outd; the level inversion in the first initial delay signal s1 is used to trigger the second transistor M21 in the first-stage target unit 221 to be connected to the ground terminal GND via the third transistor M3. The target output signal outd and the first initial delay signal s1 are inverse signals of each other.Because the second transistor M21 in the first-stage target unit 221 is grounded, the first-stage target unit 221 provides a level-flipping control signal to the second-stage target unit 222. The second-stage target unit 222 responds to this level-flipping control signal by disconnecting the second transistor M21 from the ground terminal GND via the third transistor M3 within a first preset time T1. During the level-flipping period, the current flow path shown in I0 is generated. The third transistor M3 in the first-stage target unit 221 has already disconnected from the ground terminal GND in response to the first control signal, thus cutting off the current flow path shown in I1. Therefore, the current during the conduction period of the second transistor M21 in the second-stage target unit 222 is prevented from flowing to ground through the third transistor M3 in the first-stage target unit 221. Therefore, the leakage current during the level-flipping period of the output signal of the second-stage target unit 222 is effectively reduced. Furthermore, during the period when the second transistor M21 returns from the on state to the off state, the first control signal ctl1 has already controlled the third transistor M3 in the target unit 221 to connect to the ground terminal GND within the second preset time T2, which will not affect the dynamic current change of the target unit 221 during the recovery state. Similarly, after each target unit disconnects from the ground terminal GND within the first preset time T1 according to the received control signal, it connects to the ground terminal GND within the second preset time T2. The target unit maintains a logic level within the second preset time T2 to reduce the leakage current generated through the adjacent previous target unit during the target unit's response level flip control signal action, and avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0059] For example, please refer to Figure 3b , Figure 4b and Figure 5Sub-target unit 2201 includes a first transistor M12 and a second transistor M22. Second switching unit 2203 includes a fourth transistor M4. The fourth transistor M4 is configured such that: its first terminal is connected to the power supply terminal VDD2, its control terminal receives a corresponding control signal, and its second terminal is connected to the first terminal of the first transistor M12; the fourth transistor M4 is used to disconnect within a first preset time T1 and then turn on within a second preset time T2 in response to the corresponding control signal. The first transistor M12 is configured such that: its first terminal is connected to the second terminal of the fourth transistor M4, its control terminal is connected to the output terminal of the adjacent previous target unit, and its second terminal serves as the output terminal of the current target unit; the second transistor M22 is configured such that: its second terminal is connected to the second terminal of the first transistor M12, its second terminal is connected to the ground terminal GND, and its control terminal is connected to the control terminal of the first transistor M12. The first logic control unit 21 is configured such that: a first input terminal is connected to the output terminal of the target oscillation module 20 to receive the target output signal outd; and a second input terminal receives a second enable signal Delay_Ens, used to generate a first initial delay signal s1 based on the second enable signal Delay_Ens and the target output signal outd; the level flip in the first initial delay signal s1 is used to trigger the first transistor M12 in the first-stage target unit 221 to be connected to the ground terminal GND via the second transistor M22, causing the first-stage target unit 221 to provide a level flip control signal to the second-stage target unit 222. During the level flip of the second-stage target unit 222, a current flow path as shown in Im is generated. The fourth transistor M4 in the first-stage target unit 221 has been disconnected from the power supply terminal VDD2, cutting off the current flow path as shown in ip. Therefore, the current during the conduction of the second transistor M22 in the second-stage target unit 222 is prevented from being shunted to the fourth transistor in the first-stage target unit 221. Therefore, the leakage current during the level flip of the output signal of the second-stage target unit 222 is effectively reduced. Furthermore, when the second transistor M22 recovers from the on state to the off state, the first control signal ctl1 has already controlled the fourth transistor M4 in the target unit 221 to connect to the power supply terminal VDD2 within the second preset time T2, which will not affect the dynamic current change of the target unit 221 during the recovery state. Similarly, after each target unit disconnects from the power supply terminal VDD2 within the first preset time T1 according to the received control signal, it connects to the power supply terminal VDD2 again within the second preset time T2, and the target unit maintains a logic level within the second preset time T2. This reduces the leakage current generated through the adjacent previous-stage target unit during the target unit's response to the level flip control signal, avoiding mutual influence between the operating currents of adjacent target units, thereby improving the accuracy of the electrical parameters of each stage of the target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0060] As an example, please continue to refer to Figures 4a-4bThe first transistor M11 and the first transistor M12 can be set as PMOS transistors, the second transistor M21 and the second transistor M22 as NMOS transistors, the third transistor M3 as NMOS transistors, and the fourth transistor M4 as PMOS transistor.

[0061] As an example, please continue to refer to Figure 4a , Figure 4b and Figure 5 The first logic control unit 21 includes a first NAND gate Nand2_1, which is configured such that: its first input terminal is connected to the output terminal of the target oscillation module 20 to receive the target output signal outd, and its second input terminal receives a second enable signal Delay_Ens, for generating a first initial delay signal s1 based on the second enable signal Delay_Ens and the target output signal outd; wherein, when the second enable signal Delay_Ens is valid, the first NAND gate Nand2_1 receives the target output signal outd and outputs the first initial delay signal s1, and the level state of the first initial delay signal s1 is opposite to that of the target output signal outd. The level shift in the first initial delay signal s1 is used to trigger the level shift of the output signal of the first-level target unit 221. The level shift of the output signal of the first-level target unit 221 triggers the level shift of the output signal of the second-level target unit 222. The level shift of the output signal of the second-level target unit 222 triggers the level shift of the output signal of the third-level target unit 223. The level shift of the output signal of the third-level target unit 223 triggers the level shift of the output signal of the fourth-level target unit 224. The level shift of the output signal of the fourth-level target unit 224 triggers the level shift of the output signal of the fifth-level target unit 225. The target unit outputs the signal outd. Each target unit disconnects from the ground terminal GND / power supply terminal VDD2 within the first preset time T1 according to the received control signal, and then connects to the ground terminal / power supply terminal within the second preset time T2. The target unit maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous target unit during the level flipping of the target unit in response to the input signal within the first preset time T1. This avoids the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0062] As an example, please continue to refer to Figure 4a , Figure 4b and Figure 5The second logic control unit 102 includes a second NAND gate Nand2_2, which is configured such that: its first input is connected to the output of the delay link unit 101 to receive the initial output signal out0; and its second input receives a first enable signal Ens, which is used to generate a first control signal ctl1 based on the first enable signal Ens and the initial output signal out0; wherein, when the first enable signal Ens is valid, the second NAND gate Nand2_2 receives the initial output signal out0 and outputs the first control signal ctl1, and the level state of the first control signal ctl1 is opposite to that of the initial output signal out0. The control link unit 101 includes five series-connected control units 121, 122, 123, 124, and 125. The first terminals of each control unit 121, 122, 123, 124, and 125 are connected to a third potential VDD3, allowing the potential difference between VDD3 and the first potential VDD1 to be greater than 0. Each control unit includes a first inverter inv_1. The control link unit 101 includes five series-connected first inverters inv_1. The input terminal of the first-stage first inverter inv_1 is connected to the output terminal of the second NAND gate Nand2_2 to receive a first control signal ctl1. The first control signal ctl1 triggers the first-stage first inverter inv_1 to generate a second control signal ctl2. The second control signal ctl2 triggers the second-stage first inverter inv_1 to generate a third control signal ctl3. The third-stage first inverter inv_1 is used to generate a fourth control signal ctl4, which in turn triggers the fourth-stage first inverter inv_1 to generate a fifth control signal ctl5. The fifth control signal ctl5 triggers the fifth-stage first inverter inv_1 to generate an initial output signal out0. This ensures that each target unit disconnects from the ground terminal GND / power terminal VDD2 within a first preset time T1, and then reconnects to the ground terminal GND / power terminal VDD2 within a second preset time T2, based on the received control signal with a period of T. The target unit maintains a logic level within the second preset time T2 to reduce the leakage current generated by the adjacent previous target unit during the level flipping of the target unit's response to the input signal within the first preset time T1. This avoids mutual interference between the operating currents of adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0063] For example, please refer to Figure 6a , Figure 6bThe delay measurement circuit 100 also includes a delay module 30, which is configured to receive a first enable signal Ens at its input terminal and connect its output terminal to the input terminal of the target oscillation module 20. The delay module 30 is used to generate a second enable signal Delay_Ens based on the first enable signal Ens and provide it to the target oscillation module 20.

[0064] As an example, please continue to refer to Figure 6a , Figure 6b The delay module 30 includes a second inverter inv_2 connected in series with four stages; the first enable signal Ens is sequentially passed through the second inverter inv_2 connected in series with four stages, and then provides a second enable signal Delay_Ens to the target oscillation module 20. The second enable signal Delay_Ens is delayed by a first preset threshold ΔT compared with the first enable signal Ens.

[0065] As an example, please continue to refer to Figure 5 , Figure 6a and Figure 6b The first preset threshold ΔT is greater than or equal to T1+MT and less than (M+0.5)T, where M is a positive integer. This ensures that each target unit in the target oscillation module disconnects from the ground terminal GND / power terminal VDD2 within the first preset time T1 according to the received control signal, and then connects to the ground terminal GND / power terminal VDD2 within the second preset time T2. The target unit maintains a logic level within the second preset time T2 to reduce the leakage current during the level flipping of the target unit in response to the input signal within the first preset time T1. This avoids mutual interference between the operating currents of adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit and improving the performance and reliability of the ring oscillator.

[0066] For example, please refer to Figure 7a and Figure 7b The delay measurement circuit 100 also includes an address circuit 40, which receives the address signal ads and generates several first enable signals Ens based on the address signal ads, and provides them to the corresponding control oscillation module and delay module 30 to trigger the control oscillation module and target oscillation module of the corresponding address to work.

[0067] As an example, please continue to refer to Figure 7a and Figure 7b The delay measurement circuit 100 also includes a frequency divider module 50, which is connected to the output terminal of the target oscillation module. The frequency divider module 50 is used to receive the target output signal outd and divide the target output signal outd to generate an initial frequency divider signal f0 to meet the needs of different functional units inside the integrated circuit for multiple different frequencies.

[0068] As an example, please continue to refer to Figure 7a and Figure 7b The delay measurement circuit 100 also includes an output buffer module 60, which is connected to the output terminal of the frequency divider module 50. The output buffer module 60 is used to receive the initial frequency divider signal f0 and generate the target frequency divider signal fout based on the initial frequency divider signal f0. Since each target unit 22i in the target oscillation module 20 is disconnected from the ground terminal GND / power terminal VDD2 within the first preset time T1 according to the received control signal ctli with a period of T, and then connected to the ground terminal GND / power terminal VDD2 within the second preset time T2, and the target unit maintains a logic level within the second preset time T2, the leakage current generated by the target unit 22i through the adjacent previous target unit is reduced during the operation of the response level flipping control signal. i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; the operation current between adjacent target units will not affect each other, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0069] As an example, please continue to refer to Figure 7a and Figure 7b The power supply terminals of the frequency divider module 50 and the output buffer module 60 can be connected to the third potential VDD3, which reduces the number of power supply ports in the delay measurement circuit 300, improves the circuit integration, reduces the product size, and reduces manufacturing complexity.

[0070] As an example, please continue to refer to Figure 7a and Figure 7b The output buffer module 60 can be configured to include one or more of a drive unit, a buffer, and a read / write conversion unit. The type and number of electrical components included in the output buffer module 60 can be determined based on the functional components in the actual circuit of the specific application scenario. Those skilled in the art can undoubtedly determine that equivalent / identical modifications made under the inventive concept of this disclosure fall within the protection scope of the embodiments of this disclosure.

[0071] For example, please refer to Figure 8 In one embodiment of this disclosure, a delay measurement circuit control method 400 is provided, comprising the following steps:

[0072] Step S410: Based on the response of the first enable signal to the control oscillation module, generate a number of control signals with a period of time T in sequence;

[0073] Step S420: Generate a second enable signal based on the first enable signal, wherein the second enable signal is delayed by a first preset threshold ΔT compared to the first enable signal;

[0074] Step S430: After each target unit in the target oscillation module disconnects from the target potential within a first preset time T1 according to the received control signal, it connects to the target potential within a second preset time T2. The target unit maintains a logic level within the second preset time T2. The first preset time T1 is the time for the target unit level to flip, so as to reduce the leakage current of the target unit within the first preset time T1; T1+T2=T / 2; N is an odd number.

[0075] For details, please continue to refer to Figure 8 and Figure 1 The target potential can include ground terminal GND or power terminal VDD2. The control oscillation module 10 generates several control signals sequentially based on the first enable signal Ens, such as control signals ctl1, ..., ctli, ... and ctlN. The target oscillation module 20 includes several target units, such as target units 221, ..., target units 22i, ... and target units 22N. Each target unit 22i disconnects from ground terminal GND / power terminal VDD2 within a preset time according to the received control signal ctli, and then reconnects to ground terminal GND / power terminal VDD2 within a second preset time T2. The target unit maintains a logic level during the second preset time T2. To reduce the leakage current generated by the adjacent previous stage target unit during the level flipping period of the target unit 22i's response input signal in the first preset time T1, and to ensure that the control signal of the target unit 22i has connected the adjacent previous stage target unit to the ground terminal GND / power terminal VDD2 in the second preset time T2 during the recovery state, the dynamic current change of the target unit 22i during the recovery state will not be affected; i∈[1,N], i and N are both integers greater than or equal to 1, N is an odd number, T1+T2=T / 2; to avoid mutual influence between the operating currents of adjacent two-stage target units, thereby improving the accuracy of the electrical parameters of each stage target unit in the delay measurement circuit 100, and improving the performance and reliability of the ring oscillator.

[0076] As an example, please continue to refer to Figure 8 and Figure 1During the static period of the delay measurement circuit, the input current i_1 of the drive power port in the target unit 22i can be measured, and during the oscillation period of the delay measurement circuit, the input current i_2 of the drive power port in the target unit 22i can be measured. The difference i_c between current i_2 and current i_1 is the effective drive current of the delay measurement circuit. The drive voltage of the drive power port is set to V_d. Based on the effective drive current i_c and drive voltage V_d of the delay measurement circuit, the equivalent resistance of the delay measurement circuit can be obtained. Then, based on the quotient of the delay time and the equivalent resistance of the delay measurement circuit, the equivalent capacitance of the delay measurement circuit can be obtained. Since each target unit 22i in the target oscillation module 20 disconnects from the ground terminal GND / power terminal VDD2 within a preset time according to the received control signal ctli, and then connects to the ground terminal GND / power terminal VDD2 within a second preset time T2, and the target unit maintains a logic level within the second preset time T2, the leakage current generated through the adjacent previous target unit during the operation of the target unit 22i responding to the level flip control signal is reduced, i∈[1,N], where i and N are both integers greater than or equal to 1, so as to avoid the mutual influence of the operating current between adjacent target units, thereby improving the accuracy of the electrical parameters of each target unit in the delay measurement circuit 100 and improving the performance and reliability of the ring oscillator.

[0077] For specific limitations on the delay measurement circuit control method in the above embodiments, please refer to the limitations on the delay measurement circuit above, which will not be repeated here.

[0078] It should be understood that, although Figure 8 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 8 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this disclosure can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0080] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on the present invention.

[0081] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A delay measurement circuit, characterized in that, include: The control oscillation module is configured such that its input terminal is connected to its output terminal, for receiving a first enable signal, and sequentially generating a number of control signals with a period time of T according to the first enable signal; The target oscillation module is configured such that its input is connected to its output to receive a second enable signal, wherein the second enable signal is delayed by a first preset threshold ΔT compared to the first enable signal. The target oscillation module includes N series-connected target units. The control oscillation module generates N control signals. The N series-connected target units are respectively connected to the N control signals. Each target unit is used to disconnect from the target potential within a first preset time T1 and then reconnect to the target potential within a second preset time T2 according to the received control signal. The first preset time T1 is the time for the target unit level to flip, and the second preset time T2 is the time for the target unit to maintain the logic level, so as to reduce the leakage current of the target unit within the first preset time T1; T1 + T2 = T / 2; N is an odd number.

2. The delay measurement circuit according to claim 1, characterized in that, The target oscillation module outputs a target output signal at its output terminal; the target oscillation module includes: The first logic control unit is configured to: have a first input terminal for receiving the target output signal, a second input terminal for receiving the second enable signal, and an output terminal for outputting a first initial delay signal; The target link unit is configured to receive the first initial delay signal at a first input terminal and a control signal at a second input terminal, for generating the target output signal based on the control signal and the first initial delay signal.

3. The delay measurement circuit according to claim 2, characterized in that, The first logic control unit includes: A first NAND gate is used to receive the target output signal and output the first initial delay signal when the second enable signal is valid. The first initial delay signal has the opposite level to the target output signal.

4. The delay measurement circuit according to claim 2, characterized in that, The target link unit comprises N levels of the target unit cascaded together; N>2; The input terminal of the first-level target unit is connected to the output terminal of the first logic control unit to receive the first initial delay signal; The output of the final target unit serves as the output of the target link unit. Each target unit is further configured such that: a control terminal is used to receive a corresponding control signal, a first terminal is connected to a first potential, and a second terminal is connected to the target potential.

5. The delay measurement circuit according to claim 4, characterized in that, The target unit includes a sub-target unit and a controllable switch unit; The sub-target unit is configured such that: its input terminal is connected to the output terminal of the adjacent previous target unit, its first terminal is connected to the first potential, and its second terminal is connected to the target potential via the controllable switch unit; When the control signal is within the first level range, the controllable switch unit is disconnected within the first preset time T1; when the control signal is within the second level range, the controllable switch unit is turned on within the second preset time T2.

6. The delay measurement circuit according to claim 5, characterized in that, The target potential includes a ground terminal; the controllable switching unit includes a first switching unit; The first switching unit is configured such that: a first terminal is connected to the sub-target unit, a control terminal receives the corresponding control signal, and a second terminal is connected to the ground terminal; the potential difference between the first potential and the ground terminal is greater than zero.

7. The delay measurement circuit according to claim 5, characterized in that, The target potential includes a power supply terminal; the controllable switching unit includes a second switching unit; The second switching unit is configured such that: a first terminal is connected to the power supply terminal, a control terminal receives the corresponding control signal, and a second terminal is connected to the sub-target unit; the potential difference between the power supply terminal and the first potential is greater than zero.

8. The delay measurement circuit according to claim 6, characterized in that, The sub-target unit includes: The first transistor is configured such that: its first terminal is connected to the first potential, its control terminal is connected to the output terminal of the adjacent previous target unit, and its second terminal serves as the output terminal of the current target unit; The second transistor is configured such that: a first terminal is connected to a second terminal of the first transistor, the second terminal is connected to a ground terminal via the first switching unit, and a control terminal is connected to the control terminal of the first transistor.

9. The delay measurement circuit according to claim 8, characterized in that, The first switching unit includes: The third transistor is configured such that: its first terminal is connected to the second terminal of the second transistor, its control terminal receives a corresponding control signal, and its second terminal is connected to the ground terminal; The third transistor is used to turn on in response to the control signal after being turned off within a first preset time T1 and then turned on within a second preset time T2.

10. The delay measurement circuit according to claim 7, characterized in that, The sub-target unit includes: The first transistor is configured such that: its first terminal is connected to the second terminal of the second switching unit, its control terminal is connected to the output terminal of the adjacent previous target unit, and its second terminal serves as the output terminal of the current target unit; The second transistor is configured such that: its first terminal is connected to the second terminal of the first transistor, its second terminal is connected to the ground terminal, and its control terminal is connected to the control terminal of the first transistor.

11. The delay measurement circuit according to claim 10, characterized in that, The second switching unit includes: The fourth transistor is configured such that: its first terminal is connected to the power supply terminal, its control terminal receives a corresponding control signal, and its second terminal is connected to the first terminal of the first transistor; The fourth transistor is used to turn on in response to the control signal after being turned off within a first preset time T1 and then turned on within a second preset time T2.

12. The delay measurement circuit according to any one of claims 1-10, characterized in that, Also includes: The delay module, coupled to the target oscillation module, is configured such that: its input terminal is used to receive the first enable signal, and its output terminal is connected to the input terminal of the target oscillation module, for generating the second enable signal according to the first enable signal and providing it to the target oscillation module.

13. The delay measurement circuit according to any one of claims 1-10, characterized in that, The output terminal of the control oscillation module outputs an initial output signal, and the control oscillation module includes: The second logic control unit is configured to: have a first input terminal for receiving the initial output signal, a second input terminal for receiving the first enable signal, and an output terminal for outputting the first control signal; and The control link unit includes N series-connected control units, used to sequentially generate N-1 control signals and the initial output signal based on the first received control signal; The first-level control unit is connected to the output of the second logic control unit, the output of the last-level control unit serves as the output of the control oscillation module, and the input of each control unit is connected to the control terminal of the corresponding target unit.

14. The delay measurement circuit according to claim 13, characterized in that, The second logic control unit includes: The second NAND gate is used to receive the initial output signal and output the first control signal when the first enable signal is valid. The level of the first control signal is opposite to that of the initial output signal.

15. The delay measurement circuit according to claim 13, characterized in that, The control unit includes a first inverter; The first inverter, which is connected in series with N stages, is used to generate N-1 control signals and the initial output signal in sequence according to the first received control signal, wherein the input terminal of each first inverter is connected to the control terminal of the corresponding target unit.

16. The delay measurement circuit according to any one of claims 1-10, characterized in that, T1+MT≤△T<(M+0.5)T, where M is a positive integer.

17. The delay measurement circuit according to any one of claims 1-10, characterized in that, Also includes: The address circuit is used to receive the address signal and generate a plurality of first enable signals based on the address signal to provide to the control oscillation module.

18. A method for controlling a delay measurement circuit, characterized in that, include: Based on the control oscillation module responding to the first enable signal and sequentially generating several control signals with a period of time T; A second enable signal is generated based on the first enable signal; the second enable signal is delayed by a first preset threshold ΔT compared to the first enable signal; The control oscillation module generates N control signals. The target oscillation module includes N series-connected target units, each of which is connected to one of the N control signals. Each target unit in the control target oscillation module disconnects from the target potential within a first preset time T1 according to the received control signal, and then reconnects to the target potential within a second preset time T2. The target unit maintains a logic level within the second preset time T2. The first preset time T1 is the time for the target unit's level to flip, in order to reduce the leakage current of the target unit within the first preset time T1. T1 + T2 = T / 2; N is an odd number.

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