A method and a circuit for preventing temperature drift of a gate drive of a MOS device

Abstract

The application relates to a MOS device gate driving method and a driving circuit for preventing temperature drift, which comprises the following steps: when a switching device in a circuit needs to be turned on, a turn-on gate voltage is input to the gate of the switching device; when the switching device in the circuit needs to be turned off, the voltage input to the gate of the switching device becomes a first turn-off gate voltage, so as to ensure the fast turn-off of the switching device; after the switching device is turned off in a steady state, the voltage input to the gate of the switching device becomes a second turn-off gate voltage, so as to suppress the threshold value drift of the switching device; and when the switching device is subjected to dynamic disturbance, the voltage input to the gate of the switching device becomes the first turn-off gate voltage, so as to enhance the anti-crosstalk capability of the switching device. The application adopts three gate driving voltages, i.e., the turn-on gate voltage, the first turn-off gate voltage and the second turn-off gate voltage, so as to not only suppress the threshold value drift of a silicon carbide device, but also retain the advantages of strong anti-crosstalk capability of negative turn-off voltage, fast turn-off speed and the like under various working conditions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gate driving method and driving circuit for preventing temperature drift in MOS devices. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, boasts superior performance compared to silicon (Si). SiC's bandgap is three times that of silicon, allowing it to maintain a low intrinsic carrier concentration even at high temperatures. Its critical breakdown electric field is ten times that of silicon, enabling a significant reduction in active region thickness at the same voltage rating. Furthermore, its thermal conductivity is three times that of silicon, reducing chip thermal resistance. Therefore, compared to silicon-based semiconductor devices, SiC power semiconductor devices offer higher voltage ratings, higher switching frequencies, higher operating temperatures, and lower switching losses. At the same voltage rating, SiC-based devices exhibit lower on-resistance. These advantages significantly enhance the performance of power electronic systems. In recent years, with the rapid development of emerging applications such as new energy power generation, electric vehicles, communication power supplies, and smart grids, silicon-based devices, represented by IGBTs, have gradually become unable to meet the stringent efficiency and environmental requirements of power electronic devices in practical applications. Silicon carbide MOSFETs overcome the material performance limitations of traditional Si devices, meeting the power device demands of next-generation power electronic applications and possessing a very broad market application space.

[0003] However, due to the characteristics of silicon carbide materials, silicon carbide MOSFETs still have reliability issues. Among these, the insufficient long-term stability of the threshold voltage is the most critical. Due to the influence of external stress, the threshold voltage can change (drift), potentially increasing (positive drift) or decreasing (negative drift). The impact on the device is as follows: negative threshold voltage drift can easily lead to false turn-on during operation; positive threshold voltage drift increases the device's on-resistance; and threshold voltage drift can increase the device's threshold voltage dispersion, leading to uneven current distribution in parallel operation.

[0004] The threshold voltage stability problem, from a physical mechanism perspective, stems from the high-density traps in the SiC / SiO2 system. Generally, under positive gate voltage stress, the threshold voltage drifts positively; under negative gate voltage stress, the threshold voltage drifts negatively. In actual switching conditions, the gate voltage alternates between positive and negative, and it was once thought that the positive and negative drifts partially canceled each other out. However, recent research shows that the threshold voltage drift induced by switching gate stress can far exceed that of a constant gate voltage, and is a function of the cumulative number of switching operations, rather than a superposition of positive and negative drifts. This indicates that the switching event itself triggers a new physical mechanism. Research shows that for square wave gate voltage stress, the threshold voltage drift is only significant when the gate voltage meets certain conditions. Furthermore, the greater the rate of rise or fall of the gate voltage, the faster the threshold voltage drift of the silicon carbide MOSFET.

[0005] Existing technologies propose a scheme that uses two single-channel driver chips to form a three-level drive topology to reduce the threshold drift rate of silicon carbide MOSFETs. The topology is as follows: Figure 1 As shown. When the output of single-channel driver 2 is high, the single-channel driver 1 provides the turn-on voltage V to the controlled device DUT. GSon and the turn-off voltage V GSoff When the single-channel drive 2 outputs a low level, the DUT gate is clamped to the intermediate level V. plat Its control timing and drive waveform are as follows: Figure 2 As shown, t0~t1 and t1~t2 are both device turn-on processes, with the intermediate level V. plat The aim is to change the slope of the gate voltage during device turn-on, with a very short duration or even zero. This scheme requires close coordination of instructions from two single-channel driver chips in software programming, which carries a high risk of driver waveform instability. Driver chip 2 simultaneously provides switching signals to two components with different ground potentials, NMOS and PMOS, making it difficult to achieve close coordination of the switching moments of each path.

[0006] There are also proposed driving schemes that utilize RC circuits to automatically switch to zero-level, with topologies such as... Figure 3 As shown. When the single-channel driver chip outputs the turn-off voltage V... GSoff At that time, the gate voltage of the controlled device DUT is V GSoff After capacitor C1 discharges for a period of time, the PMOS transistor turns on, and the gate voltage of the DUT is clamped to zero; until the single-channel driver chip outputs the turn-on voltage V. GSon Afterwards, the gate voltage of the DUT becomes the turn-on voltage V. GSon Furthermore, capacitor C1 charges to a positive voltage, and the PMOS transistor turns off. The driving waveform of this circuit is as follows: Figure 4 As shown, t1~t2 is the turn-off transient; t2~t3 is the turn-off steady state; t3~t4 is the intermediate level transition time, during which the device remains in the turn-off steady state; t4~t5 is the zero-level steady state; and t5~t6 is the turn-on transient. During the zero-level period, the device remains off and is not part of the device's turn-on or turn-off process. The intermediate level of this scheme can only be zero, i.e., V... GS =0V, and during this period, there is a large voltage and current across the drive resistor Rg, resulting in high drive power consumption and a potential risk of damaging the drive chip.

[0007] Therefore, existing solutions using two single-channel driver chips to form a three-level drive topology, where driver chip 2 simultaneously provides switching signals to both NMOS and PMOS components with different ground potentials, make it difficult to achieve close coordination between the switching moments of each path, resulting in a high risk of drive waveform instability. Another solution, using an RC circuit to automatically switch to zero level, suffers from a complex circuit topology and significant voltage and current across the drive resistor Rg during the maintenance of the intermediate level, leading to high drive power consumption and the potential for damaging the driver chip.

[0008] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of the prior art and provide a gate driving method and driving circuit for MOS devices to prevent temperature drift, thus solving the deficiencies of the prior art.

[0010] The objective of this invention is achieved through the following technical solution: a gate driving method for a MOS device to prevent temperature drift, the driving method comprising:

[0011] When the switching device in the circuit needs to be turned on, the gate voltage is input to the gate of the switching device to turn it on.

[0012] When the switching device in the circuit needs to be turned off, the voltage at the gate of the input switching device becomes the first turn-off gate voltage with a large absolute value to ensure the rapid turn-off of the switching device. After the switching device reaches a steady state after being turned off, the voltage at the gate of the input switching device becomes the second turn-off gate voltage with a small absolute value to suppress the threshold drift of the switching device.

[0013] When the number of switching devices in a circuit is greater than 1 and there are at least two switching devices connected in series, the turn-on of one switching device will cause dynamic disturbance to the other switching device. At this time, it is necessary to change the voltage input to the gate of the other switching device from the second turn-off gate voltage with a smaller absolute value to the first turn-off gate voltage with a larger absolute value to enhance the anti-crosstalk capability between the switching devices.

[0014] The circuit includes a half-bridge circuit, which comprises two series-connected switching devices Q1 and Q2. When the switching devices Q1 and Q2 are complementaryly turned on, the driving method includes:

[0015] During one driving cycle in which the two switching devices are complementary in conduction, from time t0 to t2, a second turn-off gate voltage with a small absolute value is continuously input to the gate of switching device Q1, causing switching device Q1 to turn off; from time t0 to t1, an on-gate voltage is continuously input to the gate of switching device Q2, causing switching device Q2 to turn on, and at time t1, the voltage input to the gate of switching device Q2 is changed from the on-gate voltage to the first turn-off gate voltage with a large absolute value and is maintained for a period of time, so as to ensure that after switching device Q2 is quickly turned off, the first turn-off gate voltage is changed to the second turn-off gate voltage with a small absolute value.

[0016] At time t2, the voltage input to the gate of switching device Q1 is changed from the second turn-off gate voltage to the turn-on gate voltage, so that switching device Q1 is turned on and continues until time t3; it is determined whether there is a dynamic disturbance after switching device Q2 is turned off in steady state, and the voltage input to the gate of switching device Q2 is determined to be either the first turn-off gate voltage or the second turn-off gate voltage based on the determination result.

[0017] Between t2 and t3, a turn-on gate voltage is continuously input to the gate of the switching device Q1 to turn it on. At t3, the voltage input to the gate of the switching device Q1 becomes the first turn-off gate voltage and continues until t4. This ensures that after the switching device Q1 is turned off quickly, the first turn-off gate voltage is then changed to the second turn-off gate voltage with a smaller absolute value.

[0018] The step of determining whether the voltage input to the gate of the switching device Q2 is the first turn-off gate voltage or the second turn-off gate voltage based on the judgment result includes:

[0019] If there is a dynamic disturbance after the switching device Q2 is turned off in steady state, then at time t2, the voltage input to the gate of the switching device Q2 is changed from the second turn-off gate voltage with a smaller absolute value to the first turn-off gate voltage with a larger absolute value and maintained for a period of time to enhance the anti-crosstalk capability. Then, the voltage input to the gate of the switching device Q2 is changed from the first turn-off gate voltage with a larger absolute value to the second turn-off gate voltage with a smaller absolute value and maintained at the second turn-off gate voltage to suppress threshold drift.

[0020] If there is no dynamic disturbance after the switching device Q2 is turned off in steady state, the voltage input to the gate of the switching device Q2 will continue until time t4 after the first turn-off gate voltage changes to the second turn-off gate voltage with a smaller absolute value.

[0021] The circuit includes a half-bridge circuit, which comprises two series-connected switching devices Q1 and Q2. When the switching devices Q1 and Q2 are not complementary in conducting, the driving method includes:

[0022] During the period when switching device Q1 is repeatedly switched on and off while switching device Q2 is always off, switching device Q1 periodically changes from the second turn-off gate voltage to the turn-on gate voltage and holds for a period of time, then changes from the turn-on gate voltage to the first turn-off gate voltage and holds for a period of time to accelerate the turn-off speed. Finally, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift. During each dynamic process of switching device Q1 being turned on, the gate input voltage of switching device Q2 changes from the second turn-off voltage to the first turn-off voltage and holds for a period of time to enhance the anti-crosstalk capability. Then, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift.

[0023] During the period when switching device Q2 is repeatedly switched on and off while switching device Q1 is normally off, the switching process of the gate input voltage of switching device Q2 is the same as the switching process of the gate input voltage of switching device Q1 described above.

[0024] The gate voltage is a positive voltage, and its range includes greater than or equal to 10V and less than or equal to 25V.

[0025] The first turn-off gate voltage is a negative voltage, and its range includes greater than or equal to -10V and less than or equal to -2V.

[0026] The second turn-off gate voltage is located between the device threshold voltage and the first turn-off gate power supply, and its range includes greater than or equal to -5V and less than or equal to 1V.

[0027] A three-level gate drive circuit for preventing temperature drift in a MOS device includes a first, second, and third level selection channel and a switching device. Each level selection channel is connected to the gate of the switching device and is connected to a switching signal. The first level selection channel provides an on-gate voltage to the gate of the switching device, while the second and third level selection channels provide a second off-gate voltage and a first off-gate voltage, respectively. The on- and off states of each level selection channel are controlled by adjusting the level of the connected switching signal, thereby controlling the input voltage to the gate of the switching device.

[0028] Each level selection channel includes two switching components connected in series and an adjustable resistor. The adjustable resistor is connected to the gate of the switching device. The two switching components are connected and share a switching signal. The high or low level of the switching signal controls the two switching components to turn on or off simultaneously, thereby connecting or disconnecting the voltage input to the gate of the switching device of the level selection channel. The voltage change rate when switching from other level selection channels to this level selection channel is adjusted by adjusting the value of the adjustable resistor, thereby controlling the transition time between the turn-on gate voltage, the first turn-off gate voltage, and the second turn-off gate voltage.

[0029] When the switch signal connected to the first level selection channel is high and the switch signals connected to the other two level selection channels are low, the turn-on gate voltage output by the first level selection channel is connected to the gate of the switching device, and the switching device is turned on.

[0030] When the switch signal connected to the third level channel is high and the switch signal connected to the other two level selection channels is low, the first turn-off gate voltage output by the third level selection channel is connected to the gate of the switching device. At this time, the switching device is quickly turned off with a first turn-off gate voltage with a large absolute value.

[0031] When the switch signal connected to the second level selection channel is high and the switch signal connected to the other two level selection channels is low, the second turn-off gate voltage output by the second level selection channel is connected to the gate of the switching device, and the switching device is turned off at this time.

[0032] Each level selection channel also includes a power supply, the power supply output of which is connected to one end of one of the switching components.

[0033] The gate voltage is a positive voltage, and its range includes greater than or equal to 10V and less than or equal to 25V.

[0034] The first turn-off gate voltage is a negative voltage, and its range includes greater than or equal to -10V and less than or equal to -2V.

[0035] The second turn-off gate voltage is located between the device threshold voltage and the first turn-off gate power supply, and its range includes greater than or equal to -5V and less than or equal to 1V.

[0036] The present invention has the following advantages: a gate driving method and driving circuit for preventing temperature drift of MOS devices. By using three gate driving voltages, namely the turn-on gate voltage, the turn-off gate voltage one, and the turn-off gate voltage two, it can not only suppress the threshold drift of silicon carbide devices, but also retain the advantages of strong anti-crosstalk capability and fast turn-off speed of negative turn-off voltage under various operating conditions. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the driving circuit of prior art 1;

[0038] Figure 2 This is a schematic diagram of the driving waveform in prior art 1;

[0039] Figure 3 This is a schematic diagram of the driving circuit in prior art 2;

[0040] Figure 4 This is a schematic diagram of the driving waveform of prior art 2;

[0041] Figure 5This is a schematic diagram of the half-bridge circuit of Embodiment 1 of the present invention and the ordinary two-level complementary conduction drive waveform;

[0042] Figure 6 This is a schematic diagram of the driving waveform timing of Embodiment 1 of the present invention;

[0043] Figure 7 This is a schematic diagram of the driving waveform timing of Embodiment 2 of the present invention;

[0044] Figure 8 This is a schematic diagram of the three-level driving circuit of Embodiment 3 of the present invention;

[0045] Figure 9 This is a schematic diagram of the three-level drive voltage waveform. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of this application provided below with reference to the accompanying drawings is not intended to limit the scope of protection of the claimed application, but merely represents selected embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. The present invention will be further described below with reference to the accompanying drawings.

[0047] One embodiment of the present invention relates to a three-level gate driving method for a MOS device to prevent temperature drift, which involves turning on the gate voltage (V... GSon ), turn-off gate voltage one (V GSoff1 ) and the turn-off gate voltage (V GSoff2 The device is driven by two different gate turn-off voltages when it is turned off. It can be used in any circuit with switching devices. When the number of switching devices in the circuit is greater than 1 and there are at least two switching devices connected in series, the turn-on of one switching device will cause crosstalk to the other switching device, causing the other switching device to be falsely turned on. The following embodiment uses a half-bridge circuit as an example. The circuit includes two switching devices. The turn-off process of the switching device and the turn-on process of the other arm device of the same half-bridge use a gate turn-off negative voltage with a larger absolute value. Its typical duration is 1.5 to 3 times the time required for the device to switch. The remaining turn-off time of this device uses a turn-off gate voltage with a smaller absolute value.

[0048] like Figure 5 The half-bridge circuit shown in (a) uses... Figure 5 The example of the lower bridge arm switching device Q2 drive waveform shown in (b) illustrates this. At time t1, the lower bridge arm Q2 is turned off, requiring a relatively large absolute turn-off negative voltage at the gate to ensure rapid turn-off. At time t2, the upper bridge arm Q1 is turned on, again requiring a relatively large absolute turn-off negative voltage at the gate to enhance crosstalk immunity. During the Q2 turn-off period from t2 to t4, using a smaller absolute turn-off voltage helps suppress threshold drift. The same analysis process applies to the gate drive voltage of the upper bridge arm switching device Q1.

[0049] Specifically, during one driving cycle in which the two switching devices are complementary in conduction, from time t0 to t2, a small absolute value off-gate voltage 2 is continuously input to the gate of switching device Q1, causing switching device Q1 to turn off; from time t0 to t1, an on-gate voltage is continuously input to the gate of switching device Q2, causing switching device Q2 to turn on, and at time t1, the voltage input to the gate of switching device Q2 is changed from the on-gate voltage to the large absolute value off-gate voltage 1 and maintained for a period of time, so as to ensure that after switching device Q2 is quickly turned off, the off-gate voltage 1 is changed to the small absolute value off-gate voltage 2.

[0050] At time t2, the voltage input to the gate of switching device Q1 is changed from the off-gate voltage 2 to the on-gate voltage, so that switching device Q1 is turned on and continues until time t3. At this time, the dead time of switching device Q2 and the duration of the off-gate voltage 1 are judged, and the voltage input to the gate of switching device Q2 is determined to be either the off-gate voltage 1 or the off-gate voltage 2 based on the judgment result.

[0051] Between t2 and t3, a turn-on gate voltage is continuously input to the gate of switching device Q1 to turn it on. At t3, the voltage input to the gate of switching device Q1 becomes the turn-off gate voltage and continues until t4. This ensures that after switching device Q1 is quickly turned off, the turn-off gate voltage is changed to the turn-off gate voltage with a smaller absolute value.

[0052] Therefore, for this example, the following applies: Figure 6 The gate voltage drive waveform and timing shown are shown. In this example, the smaller absolute value of the turn-off gate voltage (turn-off voltage II, V) is used. GSoff2 Take 0V; it is worth noting that if the dead time t DeadBand Less than the absolute value of the large turn-off gate voltage (turn-off voltage 1, V) GSoff1 Duration t off1 Therefore, a second turn-off gate voltage of 1 (V) is not required after t2. GSoff1 The criterion for judgment is that during the dynamic process of Q1 being turned on, Q2 must be a shut-off negative pressure with a larger absolute value.

[0053] Specifically, if there is a dynamic disturbance after the switching device Q2 is turned off in steady state, then at time t2, the voltage input to the gate of the switching device Q2 is changed from the smaller absolute value of the turn-off gate voltage 2 to the larger absolute value of the turn-off gate voltage 1 and maintained for a period of time to enhance the anti-crosstalk capability. Then, the voltage input to the gate of the switching device Q2 is changed from the larger absolute value of the turn-off gate voltage 1 to the smaller absolute value of the turn-off gate voltage 2 and maintained at the turn-off gate voltage 2 to suppress threshold drift.

[0054] If there is no dynamic disturbance after the switching device Q2 is turned off in steady state, that is, the dead time is very short, then the voltage input to the gate of the switching device Q2 will continue until time t4 after the gate voltage I turns off to the gate voltage II with a smaller absolute value.

[0055] In another embodiment of the present invention, if the upper and lower arms of the half-bridge circuit are not complementary in conduction, such as unipolar modulation, etc. Figure 7 In case (a) above, one switching device is repeatedly switched on and off, while the other switching device is always off, such as in applications like unipolar modulation inverters. Figure 7 As shown, (a) represents a typical dual-level unipolar modulation drive waveform, and (b) represents the drive scheme of this embodiment for this waveform; during the period when one bridge arm is normally off, the other bridge arm is turned on and off multiple times, so a negative voltage with a larger absolute value should be used each time to enhance the anti-crosstalk capability.

[0056] Specifically, during the period when switching device Q1 is repeatedly switched on and off while switching device Q2 is always off, switching device Q1 periodically changes from the second turn-off gate voltage to the turn-on gate voltage and holds for a period of time, then changes from the turn-on gate voltage to the first turn-off gate voltage and holds for a period of time to accelerate the turn-off speed. Finally, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift. During each dynamic process of switching device Q1 being turned on, the gate input voltage of switching device Q2 changes from the second turn-off voltage to the first turn-off voltage and holds for a period of time to enhance the anti-crosstalk capability. Then, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift.

[0057] During the period when switching device Q2 is repeatedly switched on and off while switching device Q1 is normally off, the switching process of the gate input voltage of switching device Q2 is the same as the switching process of the gate input voltage of switching device Q1 described above.

[0058] Another embodiment of the present invention relates to a three-level gate drive circuit for preventing temperature drift in a MOS device, such as... Figure 8 As shown, the circuit has three level selection channels, each providing a turn-on gate voltage (V) to one switching device. GSon ), gate voltage off (V) GSoff1) and the turn-off gate voltage (V GSoff2 ), give V in sequence g1 V g2 and V g3 A three-level drive waveform can be obtained from the switching signal. Each level selection channel includes two NMOS transistors connected in series, an adjustable resistor, and a power supply. The power supply is connected to the drain of one of the NMOS transistors, and the adjustable resistor is connected to the gate of the switching device. The gates of the two NMOS transistors are connected and share a switching signal. The high or low level of the switching signal controls the two NMOS transistors to turn on or off simultaneously, thereby connecting or disconnecting the voltage input to the gate of the switching device of the level selection channel. The voltage change rate when switching from other level selection channels to this level selection channel is adjusted by adjusting the value of the adjustable resistor, thereby controlling the transition time between the turn-on gate voltage, the first turn-off gate voltage, and the second turn-off gate voltage.

[0059] The NMOS transistor can be replaced with other types of switching devices or combinations of switching devices, which can completely turn on and completely cut off the path.

[0060] Its specific switching sequence is as follows Figure 9 As shown, when V g1 High level, V g2 and V g3 When V is low, the gate of the switching device DUT is at the turn-on voltage; when V g3 High level, V g1 and V g2 When V is low, the gate of the switching device DUT is at the turn-off gate voltage; when V g2 High level, V g1 and V g3 When the voltage is low, the gate of the switching device DUT is at the turn-off gate voltage. Adjusting R1 can change V. GSoff2 To V GSon The rate of voltage change during the switching process; adjusting R2 can change V GSoff1 To V GSoff2 The rate of voltage change during the switching process; adjusting R3 can change V GSon To V GSoff1 The rate of voltage change during the switching process.

[0061] Furthermore, the turn-on gate voltage (V GSon The gate voltage is positive, typically between 10V and 25V (inclusive); the gate-off voltage is - (V GSoff1 The gate voltage is negative, typically between -10V and -2V (inclusive); the gate-off voltage is two (V). GSoff2 ) at the device threshold voltage (V th ) and turn-off voltage Turn-off gate voltage one (VGSoff1 The voltage is between -5V and 1V (excluding), with typical values ​​between -5V and 1V (inclusive); the turn-off process of the switching device and the turn-on process of the other arm device of the same half-bridge adopt the turn-off gate voltage, the typical duration of which is 1.5 to 3 times the time required for the device to switch.

[0062] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and improvements, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A gate driving method for a MOS device to prevent temperature drift, characterized in that: The driving method includes: When the switching device in the circuit needs to be turned on, the gate voltage is input to the gate of the switching device to turn it on. When the switching device in the circuit needs to be turned off, the voltage at the gate of the input switching device becomes the first turn-off gate voltage with a large absolute value to ensure the fast turn-off of the switching device. After the switching device is in a steady state after being turned off, the voltage at the gate of the input switching device is changed to the second turn-off gate voltage with a small absolute value to suppress the threshold drift of the switching device. When the number of switching devices in the circuit is greater than 1 and there are at least two switching devices connected in series, the turn-on of one switching device will cause dynamic disturbance to the other switching device. At this time, it is necessary to change the voltage input to the gate of the other switching device from the second turn-off gate voltage with a smaller absolute value to the first turn-off gate voltage with a larger absolute value to enhance the anti-crosstalk capability between the switching devices. The circuit includes a half-bridge circuit, which comprises two series-connected switching devices Q1 and Q2. When the switching devices Q1 and Q2 are complementaryly turned on, the driving method includes: During one driving cycle in which the two switching devices are complementary in conduction, from time t0 to t2, a second turn-off gate voltage with a small absolute value is continuously input to the gate of switching device Q1, causing switching device Q1 to turn off; from time t0 to t1, an on-gate voltage is continuously input to the gate of switching device Q2, causing switching device Q2 to turn on. At time t1, the voltage input to the gate of switching device Q2 is changed from the on-gate voltage to the first turn-off gate voltage with a large absolute value and is maintained for a period of time, so as to ensure that after switching device Q2 is quickly turned off, the first turn-off gate voltage is changed to the second turn-off gate voltage with a small absolute value. At time t2, the voltage input to the gate of switching device Q1 is changed from the second turn-off gate voltage to the turn-on gate voltage, so that switching device Q1 is turned on and continues until time t3; it is determined whether there is a dynamic disturbance after switching device Q2 is turned off in steady state, and the voltage input to the gate of switching device Q2 is determined to be either the first turn-off gate voltage or the second turn-off gate voltage based on the determination result. At times t2 to t3, the gate voltage of the switching device Q1 is continuously input to turn on the switching device Q1. At time t3, the voltage input to the gate of the switching device Q1 becomes the first gate voltage and continues until time t4, so as to ensure that after the switching device Q1 is turned off quickly, the first gate voltage is changed to the second gate voltage with a smaller absolute value. The step of determining whether the voltage input to the gate of the switching device Q2 is the first turn-off gate voltage or the second turn-off gate voltage based on the judgment result includes: If there is a dynamic disturbance after the switching device Q2 is turned off in steady state, then at time t2, the voltage input to the gate of the switching device Q2 is changed from the second turn-off gate voltage with a smaller absolute value to the first turn-off gate voltage with a larger absolute value and maintained for a period of time to enhance the anti-crosstalk capability. Then, the voltage input to the gate of the switching device Q2 is changed from the first turn-off gate voltage with a larger absolute value to the second turn-off gate voltage with a smaller absolute value and maintained at the second turn-off gate voltage to suppress threshold drift. If there is no dynamic disturbance after the switching device Q2 is turned off in steady state, the voltage input to the gate of the switching device Q2 will continue until time t4 after the first turn-off gate voltage changes to the second turn-off gate voltage with a smaller absolute value.

2. The gate driving method for preventing temperature drift in a MOS device according to claim 1, characterized in that: The circuit includes a half-bridge circuit, which comprises two series-connected switching devices Q1 and Q2. When the switching devices Q1 and Q2 are not complementary in conducting, the driving method includes: During the period when switching device Q1 is repeatedly switched on and off while switching device Q2 is always off, switching device Q1 periodically changes from the second turn-off gate voltage to the turn-on gate voltage and holds for a period of time, then changes from the turn-on gate voltage to the first turn-off gate voltage and holds for a period of time to accelerate the turn-off speed. Finally, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift. During each dynamic process of switching device Q1 being turned on, the gate input voltage of switching device Q2 changes from the second turn-off voltage to the first turn-off voltage and holds for a period of time to enhance the anti-crosstalk capability. Then, it changes from the first turn-off gate voltage to the second turn-off gate voltage and holds for a period of time to suppress threshold drift. During the period when switching device Q2 is repeatedly switched on and off while switching device Q1 is normally off, the switching process of the gate input voltage of switching device Q2 is the same as the switching process of the gate input voltage of switching device Q1 described above.

3. The gate driving method for preventing temperature drift in a MOS device according to claim 1 or 2, characterized in that: The gate voltage is a positive voltage, and its range includes greater than or equal to 10V and less than or equal to 25V. The first turn-off gate voltage is a negative voltage, and its range includes greater than or equal to -10V and less than or equal to -2V. The second turn-off gate voltage is located between the device threshold voltage and the first turn-off gate power supply, and its range includes greater than or equal to -5V and less than or equal to 1V.

4. A three-level gate drive circuit for preventing temperature drift in a MOS device, characterized in that: It consists of a first, second, and third level selection channel and a switching device. Each level selection channel is connected to the gate of the switching device, and each level selection channel is connected to a switching signal. The first level selection channel provides the turn-on gate voltage to the gate of the switching device, and the second and third level selection channels provide the second turn-off gate voltage and the first turn-off gate voltage to the gate of the switching device, respectively. By controlling the high and low levels of the connected switching signal, the turn-on and turn-off states of each level selection channel are controlled, thereby controlling the input voltage of the gate of the switching device.

5. A three-level gate drive circuit for preventing temperature drift in a MOS device according to claim 4, characterized in that: Each level selection channel includes two switching components connected in series and an adjustable resistor. The adjustable resistor is connected to the gate of the switching device. The two switching components are connected and share a switching signal. The high or low level of the switching signal controls the two switching components to turn on or off simultaneously, thereby connecting or disconnecting the voltage input to the gate of the switching device of the level selection channel. The voltage change rate when switching from other level selection channels to this level selection channel is adjusted by adjusting the value of the adjustable resistor, thereby controlling the transition time between the turn-on gate voltage, the first turn-off gate voltage, and the second turn-off gate voltage.

6. The three-level gate drive circuit for preventing temperature drift of a MOS device according to claim 5, characterized in that: When the switch signal connected to the first level selection channel is high and the switch signals connected to the other two level selection channels are low, the turn-on gate voltage output by the first level selection channel is connected to the gate of the switching device, and the switching device is turned on. When the switch signal connected to the third level channel is high and the switch signal connected to the other two level selection channels is low, the first turn-off gate voltage output by the third level selection channel is connected to the gate of the switching device. At this time, the switching device is quickly turned off with a first turn-off gate voltage with a large absolute value. When the switch signal connected to the second level selection channel is high and the switch signal connected to the other two level selection channels is low, the second turn-off gate voltage output by the second level selection channel is connected to the gate of the switching device, and the switching device is turned off at this time.

7. A three-level gate drive circuit for preventing temperature drift in a MOS device according to any one of claims 4-6, characterized in that: The gate voltage is a positive voltage, and its range includes greater than or equal to 10V and less than or equal to 25V. The first turn-off gate voltage is a negative voltage, and its range includes greater than or equal to -10V and less than or equal to -2V. The second turn-off gate voltage is located between the device threshold voltage and the first turn-off gate power supply, and its range includes greater than or equal to -5V and less than or equal to 1V.

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