Time synchronization method and apparatus, computer device, and storage medium

Abstract

The application relates to a time synchronization method and device, computer equipment and a storage medium. The method comprises the following steps: a first core of a multi-core processor acquires a time encoding signal provided by a time service unit and decodes the time encoding signal; whenever time data of a unit time frame in the time encoding signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit timestamp is transmitted to a second core of the multi-core processor; a time synchronization instruction triggered when the unit time frame is decoded is transmitted to the second core; and the second core synchronizes system time of an operating system run by the second core based on the unit timestamp in response to the time synchronization instruction. The method can reduce hardware complexity.

Description

Technical Field

[0001] This application relates to the field of electronic information technology, and in particular to a time synchronization method, apparatus, computer equipment, and storage medium. Background Technology

[0002] With the development of electronic information technology, time synchronization technology has emerged. This technology receives external time reference signals and outputs time synchronization signals and time information to the outside world according to the required time accuracy.

[0003] However, current time synchronization methods require adding dedicated devices to parse the received external time reference signal, and then transmitting the parsed time synchronization signal and time information to the system for time synchronization, which results in high hardware complexity. Summary of the Invention

[0004] Therefore, it is necessary to provide a time synchronization method, apparatus, computer device, computer-readable storage medium, and computer program product that can reduce hardware complexity in response to the above-mentioned technical problems.

[0005] Firstly, this application provides a time synchronization method. The method includes:

[0006] The first core of the multi-core processor acquires and decodes the time-encoded signal provided by the timing unit; whenever time data of a unit time frame in the time-encoded signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit timestamp is transmitted to the second core of the multi-core processor; and a time synchronization instruction triggered when the unit time frame is decoded is transmitted to the second core.

[0007] The second kernel responds to the time synchronization command and synchronizes the system time of the operating system running the second kernel based on the unit timestamp.

[0008] In one embodiment, the unit time frame includes a first preset number of symbols, and the time data is encoded into a second preset number of symbols in the unit time frame, the second preset number being less than the first preset number; the step of transmitting the unit timestamp to the second core of the multi-core processor; and transmitting a time synchronization instruction triggered when the unit time frame is decoded to the second core includes: when the second preset number of symbols in the unit time frame is decoded, obtaining the time data, converting the time data into a unit timestamp of a preset time synchronization format, and transmitting the unit timestamp to the second core of the multi-core processor; and transmitting a time synchronization instruction to the second core when the first preset number of symbols in the unit time frame is decoded.

[0009] In one embodiment, the second preset number of symbols in the unit time frame are encoded with verification data, and the method further includes: when the second preset number of symbols in the unit time frame are decoded, obtaining the verification data and transmitting the verification data to the second kernel;

[0010] The second kernel responds to the time synchronization instruction by synchronizing the system time of the operating system running on the second kernel based on the unit timestamp, including: the second kernel responds to the time synchronization instruction by synchronizing the system time of the operating system running on the second kernel based on the unit timestamp if the verification data passes verification.

[0011] In one embodiment, the verification data includes time quality data and check bit data. The method further includes: when the time quality data indicates that the time precision of the unit timestamp is within a preset range and the check bit data is successfully verified, the verification data passes verification; when the time quality data indicates that the time precision of the unit timestamp exceeds the preset range, or the check bit data fails verification, the verification data fails verification.

[0012] In one embodiment, the step of transmitting the unit timestamp to the second core of the multi-core processor and transmitting the time synchronization instruction triggered when the unit time frame is decoded to the second core includes: transmitting the unit timestamp to the second core of the multi-core processor immediately through the message processing unit of the multi-core processor when the unit timestamp is obtained; and transmitting the time synchronization instruction to the second core immediately through the message processing unit of the multi-core processor when the unit time frame is decoded.

[0013] The second kernel responds to the time synchronization instruction and synchronizes the system time of the operating system running the second kernel based on the unit timestamp, including: the second kernel responds to the time synchronization instruction by triggering an interrupt, obtaining the unit timestamp from the first kernel, and synchronizing the unit timestamp to the system time of the operating system running the second kernel.

[0014] In one embodiment, the step of transmitting the unit timestamp to the second core of the multi-core processor and transmitting the time synchronization instruction triggered when the unit time frame is decoded to the second core includes: upon obtaining the unit timestamp, immediately writing the unit timestamp and a first flag bit to the shared memory between the first and second cores of the multi-core processor, such that when the second core reads the first flag bit from the shared memory, it reads the unit timestamp; upon decoding the unit time frame, immediately writing a second flag bit to the shared memory, the second flag bit being used to indicate the time synchronization instruction;

[0015] The second kernel responds to the time synchronization instruction by synchronizing the system time of the operating system running the second kernel based on the unit timestamp, including: when the second kernel reads the second flag bit from the shared memory, synchronizing the system time of the operating system running the second kernel based on the read unit timestamp.

[0016] In one embodiment, the method further includes: synchronizing the unit timestamp currently being transmitted by the first kernel to the second kernel to the real-time clock of the second kernel at intervals of multiple unit time periods.

[0017] Secondly, this application also provides a time synchronization device. The device includes:

[0018] The first module is used to instruct the first core of the multi-core processor to acquire and decode the time-encoded signal provided by the timing unit; whenever the time data of a unit time frame in the time-encoded signal is decoded, the corresponding unit timestamp is determined based on the time data; and the unit timestamp and the time synchronization instruction triggered when the unit time frame is decoded are transmitted to the second core of the multi-core processor.

[0019] The second module is used to instruct the second kernel to respond to the time synchronization instruction and synchronize the system time of the operating system running the second kernel based on the unit timestamp.

[0020] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0021] The first core of the multi-core processor acquires and decodes the time-encoded signal provided by the timing unit; whenever time data of a unit time frame in the time-encoded signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit timestamp is transmitted to the second core of the multi-core processor; and a time synchronization instruction triggered when the unit time frame is decoded is transmitted to the second core.

[0022] The second kernel responds to the time synchronization command and synchronizes the system time of the operating system running the second kernel based on the unit timestamp.

[0023] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0024] The first core of the multi-core processor acquires and decodes the time-encoded signal provided by the timing unit; whenever time data of a unit time frame in the time-encoded signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit timestamp is transmitted to the second core of the multi-core processor; and a time synchronization instruction triggered when the unit time frame is decoded is transmitted to the second core.

[0025] The second kernel responds to the time synchronization command and synchronizes the system time of the operating system running the second kernel based on the unit timestamp.

[0026] The aforementioned time synchronization method, apparatus, computer equipment, storage medium, and computer program product acquire and decode time-encoded signals through the first core of a multi-core processor to obtain unit timestamps. After decoding a unit time frame, a time synchronization instruction can be used to instruct the second core of the multi-core processor to synchronize the system time of the operating system on the second core. With a multi-core processor, time synchronization can be achieved without adding other hardware devices, reducing hardware complexity compared to traditional methods that require dedicated components. Attached Figure Description

[0027] Figure 1 This is a diagram illustrating the application environment of a time synchronization method in one embodiment;

[0028] Figure 2 This is a flowchart illustrating a time synchronization method in one embodiment;

[0029] Figure 3 This is a schematic diagram of an ARM multi-core processor in one embodiment;

[0030] Figure 4 This is a flowchart illustrating a time synchronization method in one embodiment;

[0031] Figure 5 This is a structural block diagram of a time synchronization device in one embodiment;

[0032] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] The time synchronization method provided in this application can be applied to, for example, Figure 1In the application environment shown, terminal 102 communicates with server 104 via a network. A data storage system can store the data that server 104 needs to process. The data storage system can be integrated onto server 104, or it can be located in the cloud or on other servers. Terminal 102 can be, but is not limited to, various desktop computers, protection devices, fault recorders, measurement and control devices, or monitoring devices. Server 104 can be implemented using a standalone server or a server cluster composed of multiple servers. Server 104 includes a multi-core processor, internal memory, and a timing unit. The multi-core processor includes at least two cores, and the cores of the multi-core processor can communicate with each other through the message handling unit (MHU) of the multi-core processor, or through shared memory in the internal memory. The multi-core processor can obtain a time-coded signal encoded according to a time coding protocol from the timing unit, and decode the time-coded signal to obtain the time data encoded in the time-coded signal. Server 104 can be an industrial server, specifically a power industry server, and further, a substation automation industry server.

[0035] In one embodiment, such as Figure 2 As shown, a time synchronization method is provided, which can be applied to... Figure 1 Taking server 104 as an example, the following steps are included:

[0036] Step 202: The first core of the multi-core processor acquires and decodes the time-encoded signal provided by the timing unit; whenever the time data of a unit time frame in the time-encoded signal is decoded, the corresponding unit timestamp is determined based on the time data; the unit timestamp is transmitted to the second core of the multi-core processor; and the time synchronization instruction triggered when the unit time frame is decoded is transmitted to the second core.

[0037] The server's multi-core processor integrates at least two complete cores. A core is a hardware module with logical operation capabilities, which can be a Central Processing Unit (CPU) or a Microcontroller Unit (MCU). The cores can be structurally and functionally identical and can serve as backups for each other; or they can be structurally and functionally different and not serve as backups for each other, but are responsible for different functions.

[0038] The time synchronization unit is used to provide accurate time data, which can be Coordinated Universal Time (UTC), also known as World Unified Time, World Standard Time, or International Coordinated Time. UTC is a time measurement system based on the atomic second and designed to be as close as possible to Universal Time in terms of time.

[0039] The time-coded signal can be the InterRange Instrumentation Group (IRIG) standard timecode, used for transmitting time data between systems or between devices within a system. The IRIG standard timecode can be in parallel timecode format or serial timecode format.

[0040] A unit-time frame is a coding unit in a time-coded signal, divided into units of time. The frame length of a unit-time frame is one unit of time, and each unit-time frame encodes time data transmitted within one unit of time. The unit of time is a pre-agreed fixed time interval. The unit of time can be 1 second, or other values ​​that are more or less than 1 second.

[0041] Specifically, the multi-core processor has a first core and a second core. The first core obtains the time-encoded signal provided by the timing unit and decodes the time-encoded signal frame by frame to obtain the time data in the currently decoded unit time frame. The first core adjusts the format of the decoded time data to a format suitable for time synchronization to obtain a unit timestamp. The first core transmits the unit timestamp and a time synchronization instruction to the second core, wherein the time synchronization instruction is triggered at the moment when the unit time frame containing the time data on which the unit timestamp is based is decoded.

[0042] Step 204: The second kernel responds to the time synchronization instruction and synchronizes the system time of the operating system running on the second kernel based on the unit timestamp.

[0043] An operating system is a computer program that manages computer hardware and software resources. An operating system can be Windows or Linux, and it is used for resource management, program control, and human-computer interaction.

[0044] Specifically, when the second kernel receives a time synchronization command, it responds by synchronizing the system time on the operating system running on the second kernel with the received unit timestamp. In one embodiment, the second kernel can convert the unit timestamp to a time format supported by the operating system it is running, thereby synchronizing the unit timestamp of that time format to the operating system's system time.

[0045] The aforementioned time synchronization method obtains and decodes the time-encoded signal through the first core of a multi-core processor to obtain a unit timestamp. After decoding a unit time frame, a time synchronization instruction can be used to instruct the second core of the multi-core processor to synchronize the system time of the operating system on the second core. With a multi-core processor, time synchronization can be achieved without adding other hardware devices, reducing hardware complexity compared to traditional methods that require dedicated components.

[0046] In one embodiment, the time-coded signal can be IRIG-B code. IRIG-B code has three code elements: "P" code, logic "1" code, and logic "0" code. The time width of each code element in IRIG-B is 10 milliseconds. The "P" code element has 8 milliseconds of high potential and the remaining 2 milliseconds of low potential; the "1" code element has 5 milliseconds of high potential and the remaining 5 milliseconds of low potential; the "0" code element has 2 milliseconds of high potential and the remaining 8 milliseconds of low potential. These three code elements are combined in a specific way to encode time data and obtain a unit time frame, where the unit time is 1 second. In this embodiment, transmitting time data using IRIG-B code has higher accuracy compared to traditional NTP network methods.

[0047] In one embodiment, the first kernel obtains the time-coded signal provided by the time synchronization unit. Specifically, it may do so by actively requesting the time-coding signal from the time synchronization unit when a time synchronization event is triggered or by passively receiving the time-coded signal output by the time synchronization unit in unit time frames.

[0048] This embodiment provides different methods for acquiring time-coded signals, applicable to various usage scenarios. Active request and passive reception can be configured through a user-facing control interface on the operating system running on the second kernel, allowing for convenient user control.

[0049] In one embodiment, a unit timestamp is transmitted to the second core of the multi-core processor; a time synchronization instruction triggered upon decoding a unit time frame is transmitted to the second core, including: when the first core triggers the time synchronization instruction, it immediately transmits both the unit timestamp and the time synchronization instruction to the second core simultaneously. In this embodiment, the first core can transmit the information required for time synchronization to the second core using a lower communication frequency.

[0050] In one embodiment, a unit timestamp is transmitted to the second core of the multi-core processor; a time synchronization instruction triggered upon decoding a unit time frame is transmitted to the second core. This includes: the first core immediately transmits the unit timestamp to the second core after obtaining it, and immediately triggers a time synchronization instruction upon decoding the unit time frame, and then transmits the time synchronization instruction to the second core. In this embodiment, the first core transmits the unit timestamp to the second core immediately after obtaining it, allowing sufficient time for transmission; the time synchronization instruction is triggered and sent to the second core immediately upon decoding the unit time frame. The second core can respond immediately upon receiving the time synchronization instruction to perform time synchronization, ensuring the accuracy of time synchronization.

[0051] In one embodiment, a unit timestamp is passed to the second core of the multi-core processor; a time synchronization instruction triggered upon completion of decoding the unit time frame is passed to the second core. This includes: the first core passing a unit timestamp to the second core at any time between decoding and obtaining time data and completing the decoding of the entire unit time frame; and immediately triggering a time synchronization instruction after completing the decoding of the unit time frame, and passing the time synchronization instruction to the second core. This embodiment can also ensure the accuracy of time synchronization to a certain extent.

[0052] In one embodiment, a unit time frame includes a first preset number of symbols, and time data is encoded into a second preset number of symbols in the unit time frame, where the second preset number is less than the first preset number. A unit timestamp is transmitted to the second core of the multi-core processor; a time synchronization instruction triggered upon decoding the unit time frame is transmitted to the second core, including: when the second preset number of symbols in the unit time frame is decoded, obtaining time data, converting the time data into a unit timestamp of a preset time synchronization format, and transmitting the unit timestamp to the second core of the multi-core processor; and when the first preset number of symbols in the unit time frame is decoded, transmitting a time synchronization instruction to the second core.

[0053] The time-coded signal can be a serially encoded signal. A symbol is the basic unit that makes up a unit time frame, and a unit time frame includes multiple symbols. A unit time frame includes a first preset number of coded bits from beginning to end, and each coded bit is encoded using one of the multiple symbols. Some coded bits can express information independently, while some adjacent coded bits express information through combinations of coded bits. The preset time synchronization format for the unit timestamp can be year / month / day / hour / minute / second, or second / minute / hour / day / month / year, etc.

[0054] In one embodiment, when the time-coded signal adopts the IRIG-B code format, the first quantity can be 100, and the second preset quantity can be 59 or 76. Specifically, the first 59 symbols of a unit time frame already include basic time data, and the time data is basically decoded based on the first 59 symbols. The 60th to 76th symbols of a unit time frame encode verification data for verifying the time data.

[0055] For example, the first 59 bits of a unit time frame are encoded sequentially with an initial flag and time data. The time data is arranged in the order of seconds (units), seconds (tens), minutes (units), minutes (tens), hours (units), hours (tens), days (units), days (tens), days (hundreds), years (units), and years (tens). The initial flag identifies the start position of a unit time frame. After decoding the first 59 or 76 bits, the first kernel can obtain the time data. This time data is expressed in a specific format. This specific formatted time data is then converted according to the timestamp format to obtain the unit timestamp.

[0056] The decoded time data can be in BCD (Binary-Coded Decimal) format, with the least significant digit first. BCD uses 4 binary bits to represent the digits 0-9 of a single decimal number; it's a binary-encoded decimal code. If the decoded tens digit is 0011 and the units digit is 0010, then after conversion to a pre-defined time synchronization format, the unit timestamp will have 32 seconds. The other time digits of the unit timestamp follow the same logic.

[0057] In this embodiment, a unit time frame includes a first preset number of symbols. Time data is encoded into a second preset number of symbols within the unit time frame, and the second preset number is less than the first preset number. Therefore, the decoding progress can be accurately located using the decoded symbol position and count value. When the second preset number of symbols in the unit time frame has been decoded, the structure of the unit time frame indicates that the time data has been decoded. The time data is converted into a unit timestamp and transmitted to the second kernel, allowing the second kernel to obtain the unit timestamp required for time synchronization. When the first preset number of symbols in the unit time frame has been decoded, the unit time frame has been completely decoded. At this point, a time synchronization command is triggered and transmitted to the second kernel, allowing the second kernel to complete time synchronization in real time, ensuring the accuracy of time synchronization.

[0058] In one embodiment, verification data is encoded in a second preset number of symbols within a unit time frame; the time synchronization method further includes: obtaining the verification data after decoding the second preset number of symbols in the unit time frame, and transmitting the verification data to the second kernel. Step 204 includes: in response to a time synchronization instruction, the second kernel synchronizes the system time of the operating system running on the second kernel based on a unit timestamp if the verification data passes verification.

[0059] The verification data encoded in a unit time frame is used to verify the time data encoded in that unit time frame. This verification data may include leap seconds, time quality data, and check bit data.

[0060] Specifically, after decoding the time data, the first kernel can continue decoding to obtain verification data. The first kernel can send a unit timestamp determined based on the time data to the second kernel immediately after decoding the time data, and then send the verification data to the second kernel after decoding the verification data. Alternatively, the first kernel can simultaneously send the unit timestamp derived from the time data and the verification data to the second kernel after both decoding the time data and further decoding to obtain the verification data.

[0061] In one embodiment, time data can be encoded into the first third preset number of symbols in a unit time frame, where the third preset number is less than the second preset number; verification data can be encoded into symbols in the second preset number of symbols in a unit time frame that are after the third preset number of symbols.

[0062] In one embodiment, the second kernel responds to the time synchronization command by performing verification based on the received verification data. If verification passes, the second kernel immediately synchronizes the system time of the operating system it runs with based on the unit timestamp. If verification fails, the second kernel discards the received unit timestamp and abandons the time synchronization for that unit of time. This embodiment enables time synchronization based on unit times, ensuring the accuracy of the time synchronization.

[0063] In one embodiment, after receiving the unit timestamp and verification data from the first kernel, the second kernel verifies the unit timestamp based on the verification data and saves the verification result corresponding to the unit timestamp. Upon receiving the time synchronization command from the first kernel, the second kernel responds. If the saved verification result indicates successful verification, the second kernel immediately synchronizes the unit timestamp to the system time of the operating system running on the second kernel. If the saved verification result indicates failed verification, the second kernel abandons the time synchronization for this unit time.

[0064] In the above embodiments, the verification data in the time-coded signal can be used to ensure the correctness of the time data in the time-coded signal. Therefore, after verification based on the verification data, time synchronization can be performed, which can further ensure the accuracy of time synchronization.

[0065] In one embodiment, the verification data includes time quality data and parity bit data. Time quality data characterizes the time precision of the time data within a given time frame. Time precision is represented by different identifiers, indicating the magnitude of the time synchronization error. Examples of different time precision values ​​include: normal time synchronization, time synchronization error less than 1 nanosecond, time synchronization error less than 10 nanoseconds… time synchronization error less than 1 second, time synchronization error less than 10 seconds, or time synchronization failure. Parity bit data is used to detect errors in the encoded data within a time frame, thereby avoiding encoding errors in the time-coded signal, such as parity check bits.

[0066] In one embodiment, the time synchronization method further includes: when the time quality data represents the time precision of the unit timestamp within a preset range and the check bit data verification is successful, the verification data passes the verification. In another embodiment, the time synchronization method further includes: when the time quality data represents the time precision of the unit timestamp exceeding a preset range, or when the check bit data verification fails, the verification data fails the verification.

[0067] Specifically, time quality data can use different identifiers to represent different time precisions per unit timestamp. When the time quality data indicates time precision within a preset range, the time quality data passes verification; if the time quality data indicates time precision outside the preset range, the time quality data fails verification. For example, if the preset range is time precision no greater than 10 nanoseconds, then if the time quality data indicates time precision less than 10 seconds, the time quality data fails verification; if the time quality data indicates time precision less than 1 nanosecond, the time quality data passes verification.

[0068] The check bit data is verified by using a pre-agreed algorithm to process the data corresponding to the check bit data in a unit time frame. The result of the operation is then compared with the check bit data. If the result matches the check bit data, the check bit data is verified successfully; otherwise, the check bit data is verified unsuccessfully.

[0069] The verification data passes if both the time quality data and the checksum data pass verification. The verification data fails if only the time quality data fails verification, or only the checksum data fails verification, or both the time quality data and the checksum data fail verification.

[0070] In the above embodiments, the verification data includes time quality data and check bit data. The time quality data can be used to verify the time synchronization reliability of a unit timestamp, while the check bit data can be used to verify the transmission reliability of a unit timestamp. Combining the time quality data and check bit data can further ensure the accuracy of time synchronization.

[0071] In one embodiment, step 202, transmitting a unit timestamp to the second core of the multi-core processor and transmitting a time synchronization instruction triggered when the unit time frame is decoded to the second core, includes: upon obtaining the unit timestamp, immediately transmitting the unit timestamp to the second core of the multi-core processor through the message processing unit of the multi-core processor; and immediately transmitting a time synchronization instruction to the second core through the message processing unit of the multi-core processor when the unit time frame is decoded. Step 204 includes: the second core responding to the interrupt triggered by the time synchronization instruction, obtaining the unit timestamp from the first core, and synchronizing the unit timestamp to the system time of the operating system running on the second core.

[0072] The Message Handling Unit (MHU) is the unit in a multi-core processor that supports inter-core communication. After obtaining the unit timestamp, the first core immediately writes the unit timestamp to the MHU. The first core also writes both the unit timestamp and the verification data to the MHU after decoding the verification data. Finally, after decoding the unit time frame, the first core writes the time synchronization instruction to the MHU.

[0073] The second kernel uses the interrupt routines provided by the operating system for the message processing unit to parse the data written in the message processing unit. When a unit timestamp is found in the message processing unit, it is saved to a global variable. When verification data is found in the message processing unit, the interrupt routine saves the verification data to a global variable. When a time synchronization instruction is found in the message processing unit, the interrupt routine triggers an interrupt and verifies the verification data saved in the global variable. If the verification is successful, the unit timestamp saved in the global variable is synchronized to the operating system.

[0074] In other embodiments, when the interrupt routine parses the verification data written to the message processing unit, it can directly perform verification based on the verification data, save the verification result, and trigger an interrupt when it parses the time synchronization instruction written to the message processing unit. If the verification result indicates that the verification is successful, the unit timestamp saved in the global variable is synchronized to the operating system.

[0075] In the above embodiments, by utilizing the message processing unit in the multi-core processor that supports communication between the first core and the second core, accurate time synchronization can be achieved at low cost and high efficiency.

[0076] In one embodiment, step 202, which involves transmitting a unit timestamp to the second core of the multi-core processor and transmitting a time synchronization instruction triggered upon decoding a unit time frame to the second core, includes: upon obtaining the unit timestamp, immediately writing the unit timestamp and a first flag bit to the shared memory between the first and second cores of the multi-core processor, such that when the second core reads the first flag bit from the shared memory, it reads the unit timestamp; upon decoding a unit time frame, immediately writing a second flag bit to the shared memory, the second flag bit being used to indicate the time synchronization instruction; step 204 includes: when the second core reads the second flag bit from the shared memory, synchronizing the system time of the operating system running on the second core based on the read unit timestamp.

[0077] The shared memory is shared by the first and second cores of the multi-core processor, and both cores can access it. The first core obtains time data during the decoding of unit time frames, converts this time data into a unit timestamp, and writes this unit timestamp and a corresponding first flag bit into the shared memory. The first flag bit indicates that the corresponding unit timestamp is stored in the shared memory. When the second core detects the first flag bit, it can read the corresponding unit timestamp.

[0078] Furthermore, after decoding the unit time frame, the first kernel immediately writes a second flag bit, used to indicate a time synchronization instruction, to the shared memory. When the second kernel reads the second flag bit from the shared memory, it reads the time synchronization instruction, responds to the instruction, and synchronizes the unit timestamp to the operating system's system time.

[0079] In one embodiment, after decoding and obtaining the verification data, the first kernel writes the unit timestamp, the verification data, and a first flag bit into shared memory. This allows the second kernel to read the unit timestamp and verification data from the shared memory when it reads the first flag bit, and then perform verification based on the verification data. When the second kernel reads the second flag bit, it responds, and if the verification based on the verification data passes, it synchronizes the unit timestamp to the operating system's system time.

[0080] In one embodiment, the shared memory has fixed fields, and the first kernel performs an overwrite operation each time it writes data to the shared memory. Specifically, the shared memory has a flag field, a time field, and a verification data field, where the flag field stores a first flag and a second flag, the time field stores a unit timestamp, and the verification data field stores the verification field. The shared memory may also have a header field and a tail field, with the flag field, time field, and verification data field located between the header field and the tail field. When the header field stores a first preset value, it indicates the start position of the field in the shared memory. When the tail field stores a second preset value, it indicates the end position of the field in the shared memory.

[0081] In one embodiment, the second kernel can read the values ​​of the header field and the tail field from shared memory. If they are the first preset value and the second preset value, respectively, then it reads the values ​​of the flag field, the time field, and the verification data field, and responds based on the read values. If the value of the header field is not the first preset value or the value of the tail field is not the second preset value, then the current time synchronization is abandoned. In other embodiments, the second kernel can also read values ​​and respond sequentially in the order of header field, intermediate field, and tail field, where the intermediate field includes the flag field, the time field, and the verification data field.

[0082] In the above embodiments, by utilizing the shared memory of the first kernel and the second kernel, accurate time synchronization can be achieved at low cost and high efficiency.

[0083] In one embodiment, the time synchronization method further includes: synchronizing the unit timestamp currently being transmitted from the first kernel to the second kernel to the real-time clock of the second kernel at intervals of multiple unit time periods.

[0084] In this embodiment, the second kernel has a real-time clock (RTC). The second kernel can not only synchronize the system time of the operating system at unit time intervals, but also run an independent thread to synchronize the real-time clock of the second kernel at time intervals of multiple unit time intervals.

[0085] In other embodiments, the second kernel may perform verification based on the verification data corresponding to the unit timestamp currently transmitted by the first kernel to the second kernel at intervals of multiple time units. After successful verification, the unit timestamp currently transmitted by the first kernel to the second kernel is synchronized to the real-time clock of the second kernel.

[0086] In the above embodiments, the system time data of the synchronous operating system can be used to synchronize the real-time clock of the second kernel, thereby improving resource utilization.

[0087] In one embodiment, the operating system running on the second kernel can provide a user-facing control interface through which the first kernel can be controlled, allowing the user to control the decoding of time-encoded signals on the first kernel through the operating system, and to control the automatic time synchronization function to be enabled or disabled.

[0088] In one embodiment, refer to Figure 3The multi-core processor is an ARM processor (a type of processor). The first core is the MCU (microcontroller unit) of the multi-core processor. Specifically, the functions implemented by the first core in the embodiments of this application can be achieved by the SCP (System Control Processor) in the first core. It can receive the time encoding information of the timing unit through the RS485 interface of the SCP. The second core can be a 64-bit core of the ARM processor. The process of the time synchronization method in this embodiment is described below, referring to... Figure 4 Upon receiving the time-encoded signal from the timing unit, the SCP decodes it and begins counting upon decoding the first symbol. Simultaneously, it continues decoding received symbols, saving the time information. After decoding a second preset number of symbols, the SCP writes the timestamp information and verification data to the MHU. After decoding another preset number of symbols, the SCP writes a time synchronization instruction to the MHU and resets the count to zero. The MHU interrupt routine in the CPU core parses the data information. Upon encountering the time synchronization instruction, it verifies it based on the verification data. If the verification passes, it synchronizes the timestamp information with the system time.

[0089] Based on the same inventive concept, this application also provides a time synchronization device for implementing the time synchronization method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more device embodiments provided below can be found in the limitations of the time synchronization method described above, and will not be repeated here.

[0090] In one embodiment, such as Figure 5 As shown, a time synchronization device is provided, comprising: a first module 502 and a second module 504, wherein:

[0091] The first module 502 is used to instruct the first core of the multi-core processor to acquire and decode the time-encoded signal provided by the timing unit; whenever the time data of a unit time frame in the time-encoded signal is decoded, the corresponding unit timestamp is determined based on the time data; and the unit timestamp and the time synchronization instruction triggered when the unit time frame is decoded are transmitted to the second core of the multi-core processor.

[0092] The second module 504 is used to instruct the second kernel to respond to a time synchronization instruction and synchronize the system time of the operating system running the second kernel based on a unit timestamp.

[0093] In one embodiment, a unit time frame includes a first preset number of symbols, and time data is encoded into a second preset number of symbols in the unit time frame, the second preset number being less than the first preset number. The first module 502 is further configured to instruct the first core to obtain time data when it has decoded the second preset number of symbols in the unit time frame, convert the time data into a unit timestamp in a preset time synchronization format, and transmit the unit timestamp to the second core of the multi-core processor; and to transmit a time synchronization instruction to the second core when it has decoded the first preset number of symbols in the unit time frame.

[0094] In one embodiment, the second preset number of symbols in the unit time frame are encoded with verification data. The first module 502 is further configured to instruct the first kernel to obtain the verification data when it has decoded the second preset number of symbols in the unit time frame, and to transmit the verification data to the second kernel. The second module 504 is further configured to instruct the second kernel to synchronize the system time of the operating system running the second kernel based on the unit timestamp when the verification data passes the verification.

[0095] In one embodiment, the verification data includes time quality data and check bit data. When the time quality data represents the time precision of the unit timestamp within a preset range and the check bit data is successfully verified, the verification data passes the verification. When the time quality data represents the time precision of the unit timestamp beyond the preset range, or the check bit data fails to be verified, the verification data fails the verification.

[0096] In one embodiment, the first module 502 is further configured to instruct the first kernel to immediately transmit the unit timestamp to the second kernel of the multi-core processor through the message processing unit of the multi-core processor when it obtains the unit timestamp; and to immediately transmit a time synchronization instruction to the second kernel through the message processing unit of the multi-core processor when the unit time frame is decoded; the second module 504 is further configured to instruct the second kernel to respond to the interrupt triggered by the time synchronization instruction, obtain the unit timestamp from the first kernel, and synchronize the unit timestamp to the system time of the operating system running by the second kernel.

[0097] In one embodiment, the first module 502 is further configured to instruct the first kernel to immediately write the unit timestamp and a first flag bit to the shared memory between the first and second kernels of the multi-core processor when it obtains the unit timestamp, so that when the second kernel reads the first flag bit from the shared memory, it reads the unit timestamp; when the unit time frame is decoded, it immediately writes the second flag bit to the shared memory, the second flag bit being used to indicate a time synchronization instruction; the second module 504 is further configured to instruct the second kernel to synchronize the system time of the operating system running the second kernel based on the read unit timestamp when it reads the second flag bit from the shared memory.

[0098] In one embodiment, at intervals of multiple unit time lengths, the unit timestamp currently being transmitted from the first kernel to the second kernel is synchronized to the real-time clock of the second kernel.

[0099] The modules in the aforementioned time synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0100] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, this computer device includes a time synchronization unit, a multi-core processor, memory, input / output (I / O) interfaces, and a communication interface. The time synchronization unit, multi-core processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The multi-core processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores time data. The I / O interfaces are used for exchanging information between the multi-core processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the multi-core processor, it implements a time synchronization method.

[0101] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0102] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0103] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0104] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0105] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A time synchronization method, characterized in that, The method includes: The first core of the multi-core processor acquires and decodes the time-encoded signal provided by the timing unit; whenever the time data of a unit time frame in the time-encoded signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit time frame includes a first preset number of symbols, and the time data is encoded into a second preset number of symbols in the unit time frame, the second preset number being less than the first preset number. The process includes: transmitting the unit timestamp to the second core of the multi-core processor; transmitting a time synchronization instruction triggered when the unit time frame is decoded to the second core, including: obtaining time data when a second preset number of symbols in the unit time frame is decoded, converting the time data into a unit timestamp in a preset time synchronization format, and transmitting the unit timestamp to the second core of the multi-core processor; and transmitting a time synchronization instruction to the second core when a first preset number of symbols in the unit time frame is decoded. The second kernel responds to the time synchronization command and synchronizes the system time of the operating system running the second kernel based on the unit timestamp.

2. The method according to claim 1, characterized in that, The process of synchronizing the system time of the operating system running the second kernel based on the unit timestamp includes: The system converts the unit timestamp into a time format supported by the operating system and synchronizes the unit timestamp of the time format to the system time of the operating system.

3. The method according to claim 1, characterized in that, The second preset number of symbols in the unit time frame are encoded with verification data, and the method further includes: When the second preset number of symbols in the unit time frame has been decoded, the verification data is obtained and transmitted to the second kernel; In response to the time synchronization instruction, the second kernel synchronizes the system time of the operating system running the second kernel based on the unit timestamp, including: In response to the time synchronization instruction, the second kernel synchronizes the system time of the operating system running the second kernel based on the unit timestamp, provided that the verification data passes verification.

4. The method according to claim 3, characterized in that, The verification data includes time quality data and check bit data, and the method further includes: When the time quality data indicates that the time precision of the unit timestamp is within a preset range, and the verification bit data is successfully verified, the verification data passes the verification. When the time quality data indicates that the time precision of the unit timestamp exceeds a preset range, or when the verification of the check bit data fails, the verification data fails.

5. The method according to any one of claims 1 to 4, characterized in that, The unit timestamp is transmitted to the second core of the multi-core processor; The time synchronization instruction triggered when the unit time frame is decoded is passed to the second kernel, including: Upon obtaining the unit timestamp, the unit timestamp is immediately transmitted to the second core of the multi-core processor through the message processing unit of the multi-core processor. Upon completion of decoding the unit time frame, a time synchronization instruction is immediately transmitted to the second core via the message processing unit of the multi-core processor. In response to the time synchronization instruction, the second kernel synchronizes the system time of the operating system running the second kernel based on the unit timestamp, including: The second kernel responds to the interrupt triggered by the time synchronization instruction, obtains the unit timestamp from the first kernel, and synchronizes the unit timestamp to the system time of the operating system running on the second kernel.

6. The method according to any one of claims 1 to 4, characterized in that, The unit timestamp is transmitted to the second core of the multi-core processor; The time synchronization instruction triggered when the unit time frame is decoded is passed to the second kernel, including: Upon obtaining the unit timestamp, the unit timestamp and the first flag bit are immediately written to the shared memory between the first core and the second core of the multi-core processor, so that when the second core reads the first flag bit from the shared memory, it reads the unit timestamp. Upon completion of decoding the unit time frame, a second flag bit is immediately written to the shared memory. The second flag bit is used to indicate a time synchronization command. In response to the time synchronization instruction, the second kernel synchronizes the system time of the operating system running the second kernel based on the unit timestamp, including: When the second kernel reads the second flag bit from the shared memory, it synchronizes the system time of the operating system running the second kernel based on the read unit timestamp.

7. The method according to any one of claims 1 to 4, characterized in that, The method further includes: At regular intervals of several unit time periods, the unit timestamp currently being transmitted from the first kernel to the second kernel is synchronized to the real-time clock of the second kernel.

8. A time synchronization device, characterized in that, The device includes: The first module is used to instruct the first core of the multi-core processor to acquire and decode the time-encoded signal provided by the timing unit; whenever time data of a unit time frame in the time-encoded signal is decoded, a corresponding unit timestamp is determined based on the time data; the unit time frame includes a first preset number of symbols, and the time data is encoded into a second preset number of symbols in the unit time frame, the second preset number being less than the first preset number; the module transmits the unit timestamp and a time synchronization instruction triggered when the unit time frame is decoded to the second core of the multi-core processor, including: when the second preset number of symbols in the unit time frame is decoded, acquiring the time data, converting the time data into a unit timestamp of a preset time synchronization format, and transmitting the unit timestamp to the second core of the multi-core processor; when the first preset number of symbols in the unit time frame is decoded, transmitting a time synchronization instruction to the second core; The second module is used to instruct the second kernel to respond to the time synchronization instruction and synchronize the system time of the operating system running the second kernel based on the unit timestamp.

9. A computer device comprising a memory and a multi-core processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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