A circuit board, an electronic device, and a method for manufacturing the circuit board.

Abstract

This disclosure provides a circuit board, an electronic device, and a method for manufacturing the circuit board. The circuit board includes: a substrate; a plurality of pad areas located on the substrate; a first reflective layer located on the same side of the substrate as the plurality of pad areas, the first reflective layer including a plurality of mutually spaced reflective patterns with gaps between adjacent reflective patterns, and the first reflective layer having a first cutout in the area of ​​each of the plurality of pad areas.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a circuit board, an electronic device, and a method for manufacturing a circuit board. Background Technology

[0002] Light-emitting diode (LED) display refers to the technology of arraying and miniaturizing traditional LEDs and then massively transferring them onto a circuit board to form ultra-small pitch LEDs. This further miniaturizes the length of LEDs from millimeters to micrometers to achieve ultra-high pixel count and ultra-high resolution, theoretically adaptable to screens of various sizes. Summary of the Invention

[0003] This disclosure provides a circuit board, an electronic device, and a method for manufacturing the circuit board. The circuit board includes:

[0004] Substrate;

[0005] Multiple pad areas are located on the substrate;

[0006] A first reflective layer is located on the same side of the substrate as the plurality of pad areas. The first reflective layer includes a plurality of mutually spaced reflective patterns with gaps between adjacent reflective patterns. The first reflective layer has a first cutout in the area where each of the plurality of pad areas is located.

[0007] In one possible implementation, at least one of the plurality of pad areas is distributed within the area enclosed by at least one of the outer contours of the reflective pattern.

[0008] In one possible implementation, the minimum size of any of the reflective patterns is greater than the maximum size of the pad area within the area enclosed by the reflective pattern, and only one of the plurality of pad areas is distributed within the area enclosed by the outer contour of at least one of the reflective patterns.

[0009] In one possible implementation, at least one of the outer contour shapes of the reflective pattern is different from the shape of the pad area within the area enclosed by the reflective pattern.

[0010] In one possible implementation, at least one of the outer contours of the reflective pattern is a circle, rectangle, polygon, or ellipse, and the pad area within the area enclosed by the reflective pattern is rectangular.

[0011] In one possible implementation, the plurality of pad areas include a first component pad area and / or a second component pad area, wherein the number of pads or the size of pads included in the first component pad area and the second component pad area are different.

[0012] In one possible implementation, the circuit board includes a plurality of device areas; the device areas include at least one first component pad area and / or at least one second component pad area;

[0013] At least one of the device regions is distributed within the area enclosed by the outer contour of at least one of the reflective patterns.

[0014] In one possible implementation, at least one of the reflection patterns includes a first sub-reflection pattern and a second sub-reflection pattern;

[0015] The at least two first element pad areas of the same device region are distributed in an array within the area enclosed by the outer contour of the first sub-reflective pattern.

[0016] The second element pad area of ​​the same device area is distributed in the second sub-reflection pattern.

[0017] In one possible implementation, in at least one of the reflective patterns, the first sub-reflective pattern and the second sub-reflective pattern are interconnected and form an integral structure.

[0018] In one possible implementation, the outer contour shape of at least one of the reflective patterns projected onto the substrate is similar to the shape formed by the distribution areas of the first element pad area and the second element pad area within the same device region.

[0019] In one possible implementation, all of the reflected patterns have the same shape.

[0020] In one possible implementation, at least two of the reflective patterns have different shapes.

[0021] In one possible implementation, the reflective patterns are arranged in an array; along a first direction, the minimum spacing between two adjacent reflective patterns is the same, and along a second direction, the minimum spacing between two adjacent reflective patterns is the same.

[0022] In one possible implementation, the ratio of the minimum spacing between two adjacent pad areas in the plurality of pad areas to the minimum spacing between two adjacent reflection patterns along the first direction ranges from 3 to 10.

[0023] Along the second direction, the ratio of the minimum spacing between two adjacent pad areas in the plurality of pad areas to the minimum spacing between two adjacent reflection patterns along the second direction ranges from 3 to 10.

[0024] In one possible implementation, along the first direction, the minimum spacing between two adjacent reflective patterns is greater than 2 mm;

[0025] Along the second direction, the minimum spacing e2 between two adjacent reflection patterns is greater than 2 mm.

[0026] In one possible implementation, the material of the first reflective layer is white ink.

[0027] In one possible implementation, the circuit board further includes a second reflective layer located on the side of the first reflective layer opposite to the substrate.

[0028] In one possible implementation, the second reflective layer has a second cutout in the area where the pad area is located;

[0029] The projected area of ​​the second cutout on the substrate is larger than the projected area of ​​the first cutout on the substrate, and the projected area of ​​the first cutout on the substrate is located within the projected area of ​​the second cutout on the substrate.

[0030] In one possible implementation, the area of ​​the second reflective layer other than the second cutout, in its orthogonal projection onto the substrate, at least covers the orthogonal projection of the gap between two adjacent reflective patterns onto the substrate.

[0031] In one possible implementation, the orthographic projection of the area of ​​the second reflective layer other than the second cutout onto the substrate overlaps with a portion of the orthographic projection of at least one of the reflective patterns onto the substrate.

[0032] In one possible implementation, within the circuit board, the minimum spacing between each of the second cutouts and the pad area located in the orthographic projection is approximately the same.

[0033] In one possible implementation, along the first direction, the minimum distance between the second cutout and the pad area located within the orthographic projection is less than the minimum distance between two adjacent pad areas among the plurality of pad areas.

[0034] In one possible implementation, an adhesive layer is further provided between the second reflective layer and the first reflective layer.

[0035] In one possible implementation, the viscosity of the adhesive layer is in the range of 800 Pa·s to 2000 Pa·s.

[0036] In one possible implementation, the second reflective layer includes a substrate, a first film layer located on the side of the substrate away from the first reflective layer, and a second film layer located on the side of the substrate facing the first reflective layer.

[0037] In one possible implementation, the substrate contains dispersed scattering particles and / or microbubbles.

[0038] In one possible implementation, the substrate is made of polyethylene terephthalate or polypropylene; the first film layer is made of titanium dioxide; and the second film layer is made of a white oil coating.

[0039] This disclosure also provides an electronic device, which includes the circuit board as provided in this disclosure, and a plurality of first elements and / or a plurality of second elements, wherein each of the plurality of first elements is connected to a pad area of ​​a first element, and each of the plurality of second elements is connected to a pad area of ​​a second element.

[0040] In one possible implementation, the first elements in the same device region are interconnected.

[0041] This disclosure also provides a method for manufacturing a circuit board as described in the embodiments of this disclosure, comprising:

[0042] Provide a substrate;

[0043] A first reflective layer having multiple mutually spaced reflective patterns is formed on one side of the substrate.

[0044] In one possible implementation, forming a first reflective layer having a plurality of mutually spaced reflective patterns on one side of the substrate includes:

[0045] A first reflective film is coated on one side of the substrate;

[0046] A first reflective layer is formed by a partitioned exposure process, having multiple mutually spaced reflective patterns and exposing at least a portion of the multiple pad areas, wherein at least one device area is distributed within at least one of the reflective patterns.

[0047] In one possible implementation, forming a first reflective layer having a plurality of mutually spaced reflective patterns on one side of the substrate includes:

[0048] A first reflective film is coated on one side of the substrate;

[0049] A first reflective layer is formed by a regional exposure process, having multiple mutually spaced reflective patterns and exposing at least a portion of the multiple pad areas, wherein at least one of the multiple pad areas is distributed within at least one of the reflective patterns.

[0050] In one possible implementation, after forming a first reflective layer having a plurality of mutually spaced reflective patterns on one side of the substrate, the fabrication method further includes:

[0051] A reflective structure is provided, wherein the reflective structure includes a second reflective layer, an adhesive layer located on one side of the second reflective layer, a first protective layer located on the side of the adhesive layer opposite to the second reflective layer, and a second protective layer located on the side of the second reflective layer opposite to the adhesive layer.

[0052] The reflective structure is baked at a temperature higher than the initial temperature Tg, where the initial temperature Tg is the temperature at which the cooling rate and the volume discharge rate are mismatched.

[0053] Remove the first protective layer of the cooled reflective structure, and attach the second reflective layer to the side of the first reflective layer away from the substrate using the adhesive layer;

[0054] Remove the second protective layer. Attached Figure Description

[0055] Figure 1 A schematic diagram of the process flow for forming a white oil layer;

[0056] Figure 2 This is a cross-sectional schematic diagram of a reflective sheet structure;

[0057] Figure 3 This is one of the top views of a circuit board provided in an embodiment of this disclosure;

[0058] Figure 4 for Figure 3 Enlarged schematic diagram of the dashed coil S1 in the middle;

[0059] Figure 5 for Figure 3 Enlarged schematic diagram of the dashed coil S2;

[0060] Figure 6 This is one of the top views of a circuit board provided in an embodiment of this disclosure;

[0061] Figure 7A This is one of the magnified schematic diagrams of the reflection pattern according to an embodiment of the present disclosure;

[0062] Figure 7B This is a schematic diagram showing that the reflective pattern of an embodiment of this disclosure is rectangular;

[0063] Figure 8 This is a second enlarged schematic diagram of the reflective pattern according to an embodiment of the present disclosure;

[0064] Figure 9 This is the third top view of the circuit board provided in the embodiments of this disclosure;

[0065] Figure 10 A schematic diagram showing a first sub-pad area including two pads is provided for embodiments of this disclosure;

[0066] Figure 11 A schematic diagram showing a second sub-pad area comprising four pads, provided for embodiments of this disclosure;

[0067] Figure 12A This is one of the schematic cross-sectional views of a circuit board provided in the embodiments of this disclosure;

[0068] Figure 12B This is a second schematic cross-sectional view of a circuit board provided in an embodiment of this disclosure;

[0069] Figure 13 This is a top view schematic diagram of the second reflective layer provided in an embodiment of the present disclosure;

[0070] Figure 14 Fourth top view of the circuit board provided in the embodiments of this disclosure;

[0071] Figure 15 Fifth top view of the circuit board provided in the embodiments of this disclosure;

[0072] Figure 16 This is the third schematic cross-sectional view of the circuit board provided in the embodiments of this disclosure;

[0073] Figure 17A One of the schematic diagrams comparing the warpage values ​​of a circuit board under different conditions provided in this embodiment of the disclosure;

[0074] Figure 17B This is the second schematic diagram comparing the warpage values ​​of the circuit board under different conditions provided in the embodiments of this disclosure.

[0075] Figure 18 This is one of the cross-sectional schematic diagrams of an electronic device provided in the embodiments of this disclosure;

[0076] Figure 19 This is a second cross-sectional schematic diagram of an electronic device provided in an embodiment of the present disclosure;

[0077] Figure 20 This is the third cross-sectional schematic diagram of an electronic device provided in the embodiments of this disclosure;

[0078] Figure 21 A schematic diagram showing the series connection of different light-emitting elements in the same light-emitting area provided in an embodiment of this disclosure;

[0079] Figure 22 This is one of the schematic diagrams of the circuit board manufacturing process provided in the embodiments of this disclosure;

[0080] Figure 23 This is the second schematic diagram of the circuit board manufacturing process provided in the embodiments of this disclosure;

[0081] Figure 24 This is a schematic diagram of a reflective structure provided in an embodiment of the present disclosure. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0084] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0085] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes do not represent the precise shapes of the illustrated regions and are not intended to limit the scope of the claims.

[0086] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0087] In related technologies, passive display panels require a backlight to provide display brightness. To ensure high brightness, a high-reflectivity reflective structure is essential in the backlight to maximize light emission efficiency and increase brightness. For example, one option for the high-reflectivity film layer is white ink. Figure 1 The process for creating a photosensitive white ink layer on a substrate involves first cleaning the substrate, then printing a solid-liquid mixed state photosensitive white ink material onto a specific area of ​​the substrate, followed by pre-curing and final curing to obtain a photosensitive white ink layer with high reflectivity. Another option for a high-reflectivity film is a reflective sheet, which is typically a multi-layered structure, such as... Figure 2 As shown, the backlight may include, for example, a lower protective film 042, an adhesive film 043, a reflective layer 04, and an upper protective film 041. In use, first peel off the bottommost lower protective film 042, then firmly attach the reflective layer 04 to the surface to be adhered to using the adhesive of the adhesive film 043, and finally peel off the upper protective film 041. Therefore, a white ink layer or a reflective layer can be selected in the backlight to improve the brightness of the emitted light. In some cases, a reflective sheet can be placed on the substrate with the white ink layer to further increase the substrate reflectivity and reduce energy consumption.

[0088] In the preparation process of the white ink layer, the white ink material needs to be cured to form a white ink layer. After curing, the white ink material will generate tensile stress, which manifests as warping on the substrate.

[0089] Warpage indicates that a cross-section that was originally planar no longer remains planar, i.e., deformation occurs. This can affect the reliability and quality of a product. For example, in the manufacturing process of circuit boards, a vacuum adsorption device is needed to fix the substrate for subsequent processes (such as the process of connecting components to pads on the substrate). However, vacuum adsorption equipment also has certain limitations. If the warpage of the substrate is too large, the adsorption device cannot adsorb and fix the workpiece, thus making it impossible to carry out subsequent processes. For the substrate in the backlight, the area of ​​the white ink layer projected onto the substrate exceeds 80% of the total planar area of ​​the substrate, and these areas are interconnected. The inventors investigated the warping of the substrate after applying the aforementioned patterned white ink layer. For a quadrilateral substrate with a white ink layer (e.g., the area of ​​the white ink layer projected onto the substrate exceeds 90% of the total planar area), warping values ​​were tested at equidistant points (e.g., a total of 10 points) in four regions near the four edges of the substrate. It was found that the warping values ​​at multiple locations on the substrate exceeded 2.6 mm. In this case, the vacuum adsorption equipment could not adsorb and fix the substrate on the stage, thus hindering stable support, accurate alignment, or the performance of corresponding processes. Therefore, the substrate warping value has a significant impact on subsequent processes.

[0090] The inventors further discovered that if a white ink layer is already applied to the substrate, applying a reflective layer not only increases substrate warpage due to the tensile stress generated after the white ink cures, but also, because the reflective layer 04 is adhered to the white ink layer via a high-viscosity (>3000 Pa·s) adhesive film 043, subsequent high-temperature processes (e.g., 150°C, for processes where protective structures are applied to components via drop-casting or printing) further increase substrate stress and warpage. Furthermore, if the process temperature (100°C–150°C) in subsequent processes exceeds the reflective sheet's initial temperature Tg (the temperature at which the cooling rate and volume ejection rate of the reflective sheet do not match), the reflective layer 04 will shrink, exhibiting a warped morphology. This negatively impacts subsequent processes such as reliable connection, testing, and rework of electronic components (e.g., micro-LEDs) to the substrate, and also affects the overall product yield.

[0091] For example, in experiments, before the reflective sheet was applied to the white ink layer, the maximum substrate warpage was 1.55 mm. After the reflective sheet was applied to the white ink layer, under process conditions of +150°C, the maximum substrate warpage increased to 4.75 mm (the equipment can handle warpage <2.6 mm). Therefore, after attaching the reflective sheet, the substrate warpage further fails to meet the equipment requirements for subsequent processes. Thus, a process method to improve substrate warpage is urgently needed.

[0092] In view of this, see Figures 3-6 ,as well as Figure 12A As shown, where, Figure 4 for Figure 3 An enlarged schematic diagram at the dashed circle S1 Figure 5 for Figure 3 Enlarged schematic diagram at the dashed circle S2 Figure 12A for Figure 3 A cross-sectional schematic diagram along the dashed line AA'. This disclosure provides a circuit board, comprising:

[0093] Substrate 1;

[0094] Multiple pad areas 3 are located on substrate 1;

[0095] A first reflective layer 20 is located on the same side of the substrate 1 as the pad area 3. The first reflective layer 20 includes a plurality of mutually spaced reflective patterns 2 with gaps between adjacent reflective patterns 2. The reflective patterns 2 have a first cutout 30 in the area where the pad area 3 is located. Specifically, the area exposed at the first cutout 30 is the area of ​​the substrate 1.

[0096] In this embodiment of the present disclosure, the first reflective layer includes a plurality of mutually spaced reflective patterns 2, with gaps between adjacent reflective patterns 2. The first reflective layer is formed as a film layer with a plurality of mutually spaced reflective patterns 2. Compared with a first reflective layer that is interconnected everywhere, the first film layer with a plurality of mutually spaced reflective patterns 2 can release the tensile stress generated by the circuit board due to the setting of the first reflective layer 2, and greatly reduce the probability of the circuit board warping.

[0097] In one possible implementation, at least one pad area 3 is distributed within the area enclosed by the outer contour of each reflective pattern 2. For example, as... Figure 3 In the image, five pad areas 3 are distributed within the area enclosed by the outer contour of a reflective pattern 2. For example, such as... Figure 6In this embodiment, a pad area 3 is distributed within the area enclosed by the outer contour of a reflective pattern 2. For example, the reflective pattern 2 includes a first sub-reflective pattern 21 and a second sub-reflective pattern 22, wherein a first component pad area 31 is distributed within each first sub-reflective pattern 21, and a second component pad area 32 is distributed within each second sub-reflective pattern 22. The areas enclosed by the outer contours of the first sub-reflective pattern 21 and the second sub-reflective pattern 22 are almost the same. However, it can be understood that the size of the first cutout 30 of the first sub-reflective pattern 21 is adapted to the size and shape of the first component pad area 31, in order to fully expose each pad in the first component pad area 31 and to consider process accuracy in the design. Similarly, the size of the first cutout 30 of the second sub-reflective pattern 22 is adapted to the size and shape of the second component pad area 32, in order to fully expose each pad in the second component pad area 32 and to consider process accuracy in the design. Of course, in specific implementations, other numbers of pad areas 3 may also be distributed within the area enclosed by the outer contour of a reflective pattern 2, and this embodiment is not limited thereto.

[0098] In one possible implementation, such as Figure 6 As shown, the minimum size of the reflective pattern 2 is larger than the maximum size of the pad area 3, and only one pad area 3 is distributed within the area enclosed by the outer contour of the reflective pattern 2. In this embodiment of the invention, only one pad area 3 is distributed within the area enclosed by the outer contour of the reflective pattern 2. When forming the reflective pattern 3, the film layer forming the reflective pattern 3 is exposed in regions (with one pad area 3 as one region). The first reflective layer may include a large number of reflective patterns, but each has a small surface area. The tensile stress generated by the circuit board due to the setting of the first reflective layer 2 is released more thoroughly, greatly reducing the probability of circuit board warping.

[0099] Specifically, the minimum size of the reflective pattern 2 can be understood as the perimeter of the outer contour of the orthographic projection of the reflective pattern 2 onto the substrate 1, or the side length / diagonal / diameter / major axis of the shape defined by the orthographic projection; the maximum size of the pad area 3 can be understood as the perimeter of the outer contour of the orthographic projection of the pad area 3 onto the substrate 1, or the side length / diagonal / diameter of the shape defined by the orthographic projection. For example, with... Figure 7A Taking the example shown, the shape defined by the outer contour of the orthographic projection of the reflective pattern 2 onto the substrate 1 is a polygon, and the shape defined by the outer contour of the orthographic projection of the pad area 3 onto the substrate 1 is a quadrilateral. The minimum size of the reflective pattern 2 can be understood as the length d1 of the shortest side of the polygon, and the maximum size of the pad area 3 can be understood as the length d2 of the long side of the rectangle, where d1 > d2. It can be understood that the apex corners of the polygon can have a rounded shape. For example, taking... Figure 7BTaking the example shown, the shape defined by the outer contour of the orthographic projection of the reflective pattern 2 onto the substrate 1 is rectangular, and the shape defined by the outer contour of the orthographic projection of the pad area 3 onto the substrate 1 is also rectangular. The minimum size of the reflective pattern 2 can be understood as the length of the shorter side d1 of the rectangle, and the maximum size of the pad area 3 can be understood as the length of the longer side d2 of the rectangle, where d1 > d2. For another example, taking... Figure 8 As shown in the example, the shape defined by the outer contour of the orthographic projection of the reflective pattern 2 onto the substrate 1 is a circle, and the shape defined by the outer contour of the orthographic projection of the pad area 3 onto the substrate 1 is a rectangle. The minimum size of the reflective pattern 2 can be understood as the diameter L0 of the circle, and the maximum size of the pad area 3 can be understood as the length d2 of the long side of the rectangle, where L0 > d2.

[0100] In one possible implementation, the shape of the reflective pattern 2 differs from the shape of the pad area 3. For example, as... Figure 3 As shown, the shape defined by the outer contour of the orthographic projection of the reflective pattern 2 onto the substrate 1 is a polygon, and the shape defined by the outer contour of the orthographic projection of the pad area 3 onto the substrate 1 is a rectangle; for example, as... Figure 6 As shown, the outer contour of the reflection pattern 2 projected onto the substrate 1 is circular, and the outer contour of the pad area 3 projected onto the substrate 1 is rectangular.

[0101] In one possible implementation, such as Figure 3 or Figure 9 As shown, multiple pad areas 3 include a first component pad area 31 and / or a second component pad area 32, wherein the number of pads or the pad size of the first component pad area 31 and the second component pad area 32 are different. Specifically, for example, Figure 10 As shown, the first component pad area 31 includes two pads 33; as Figure 11 As shown, the second component pad area 32 includes at least four pads 33.

[0102] In one possible implementation, such as Figure 3 or Figure 9 As shown, the circuit board includes multiple device areas 5; each device area 5 includes at least one first component pad area 31 and / or at least one second component pad area 32; at least one device area 5 is distributed within the area enclosed by the outer contour of the reflective pattern 2. In this embodiment, at least one device area 5 is distributed within the area where the reflective pattern 3 is located. When forming the reflective pattern 3, the film layer forming the reflective pattern 3 is divided into sections (each section having at least one device area 5) for exposure, so that at least one device area 5 is distributed within the area enclosed by the outer contour of the reflective pattern 2. Compared to a first reflective layer that is interconnected everywhere, this can release the tensile stress generated by the circuit board due to the provision of the first reflective layer 2, and avoid the problem of warping of the circuit board when forming a first reflective layer that is interconnected everywhere.

[0103] It should be noted that, Figure 9 This is an illustrative example of two device areas 5 distributed within the area enclosed by the outer contour of a reflective pattern 2. In specific implementations, other numbers of device areas 5 may also be distributed within the area enclosed by the outer contour of a reflective pattern 2. This embodiment is not limited to this. For example, three device areas 5 may be distributed within the area enclosed by the outer contour of a reflective pattern 2, four device areas 5 may be distributed within the area enclosed by the outer contour of a reflective pattern 2, and five device areas 5 may be distributed within the area enclosed by the outer contour of a reflective pattern 2.

[0104] In one possible implementation, combining Figure 3 As shown, only one device area 5 is distributed within the area enclosed by the outer contour of the reflective pattern 2.

[0105] In practical implementation, the first component pad area 31 can be used to solder to a first component, which can be a light-emitting element, such as a mini light-emitting diode (Mini-LED). Mini-LEDs are small in size and have high brightness, and can be widely used in the backlight modules of display devices to finely adjust the backlight, thereby achieving the display of high-dynamic range (HDR) images. For example, the typical size (e.g., length) of a Mini-LED is 50 micrometers to 200 micrometers, such as 80 micrometers to 150 micrometers.

[0106] In practical implementation, the second component pad area 32 can be used for soldering with a second component, which can be a microcontroller chip, a microsensor, a capacitor, an inductor, a resistor, etc. Specifically, after multiple first pad areas 31 of a device area 5 are soldered one-to-one with multiple light-emitting elements, and the second pad area 32 is soldered with the corresponding microcontroller chip, a light-emitting area is formed. Thus, the microcontroller chip within a light-emitting area can control the light emission of multiple light-emitting elements within that area, realizing zoned control and local dimming of the circuit board.

[0107] Specifically, the Mini-LED may include two pins (N and P pins), which are respectively soldered to two pads 33 in the first component pad area 31. The microcontroller chip may include at least four pins, which can be soldered one-to-one to multiple pads 33 in the second component pad area 32. When the reflective pattern 2 is formed, a first cutout 30 simultaneously exposes two pads 33 for bonding with the two pins of the Mini-LED, or simultaneously exposes four pads 33 for bonding with the four pins of the microcontroller chip.

[0108] The circuit board can be divided into multiple device areas arranged in an array. Each device area includes at least a first element pad area for connecting to at least one first element. In some embodiments, each device area also includes a first element pad area for connecting to at least one second element. The first element pad area is used to connect to the first element that implements the main function of the circuit board, while the second element pad area is used to connect to the second element that cooperates with the first element to implement a corresponding function. For example, the first element may include a Mini-LED, whose main function is to provide illumination; the second element may include a microcontroller chip for providing control signals to the Mini-LED; it may also include a microsensor chip for sensing signals from electrical structures / devices on the circuit board, such as the Mini-LED; and it may also include commonly used electronic components such as capacitors, inductors, and resistors.

[0109] In one possible implementation, combining Figure 3 As shown, the reflection pattern 2 includes a first sub-reflection pattern 21 and a second sub-reflection pattern 22; at least two first component pad areas 31 belonging to the same device area 5 are distributed in the area where the first sub-reflection pattern 21 is located; and the second component pad areas 32 of the same device area 5 are distributed in the second sub-reflection pattern 22.

[0110] In one possible implementation, combining Figure 3 As shown, in at least one reflective pattern 2, the first sub-reflective pattern 21 and the second sub-reflective pattern 22 are interconnected and form an integral structure.

[0111] In some embodiments, such as Figure 3 As shown, each reflective pattern 2 corresponds one-to-one with each device region, i.e., they are arranged in an array. Along the first direction X, the minimum spacing e1 between two adjacent reflective patterns 2 is the same; along the second direction Y, the minimum spacing e2 between two adjacent reflective patterns 2 is the same. The first sub-reflective pattern 21 can be rectangular, and the second sub-reflective pattern 22 can be rectangular. In the same direction, the size of the first sub-reflective pattern 21 is larger than the size of the second reflective pattern 22. Each second sub-reflective pattern 22 is located on the same side of each first sub-reflective pattern 21, for example, as... Figure 3 In the middle, each second sub-reflective pattern 22 extends from the first sub-reflective pattern 21 along the second direction Y to form an integral structure.

[0112] In one possible implementation, combining Figure 3 As shown, along the first direction X, the ratio of the minimum spacing e3 between two adjacent pad areas 3 to the minimum spacing e1 between two adjacent reflective patterns 2 ranges from 3 to 10; along the second direction Y, the ratio of the minimum spacing e4 between two adjacent pad areas 3 to the minimum spacing e2 between two adjacent reflective patterns 2 ranges from 3 to 10.

[0113] It is understood that the first direction intersects the second direction; multiple pad areas are arranged at intervals along the first direction and / or the second direction. In some embodiments, the first direction and the second direction are perpendicular to each other, such as... Figure 3 As shown, any two adjacent pad areas in the multiple pad areas are distributed at intervals along the first direction or the second direction; or any two adjacent pad areas in the multiple pad areas may also be distributed at intervals along the first direction or the second direction with a certain angle between them, the angle being in the range of 0° to 60°; or at least two pad areas in the multiple pad areas are distributed at intervals along the first direction, and at the same time, at least two pad areas in the multiple pad areas are distributed at intervals along the second direction.

[0114] In one possible implementation, combining Figure 3 As shown, along the first direction X, the minimum spacing e1 between two adjacent reflective patterns 2 is greater than 2 mm; along the second direction Y, the minimum spacing between two adjacent reflective patterns is greater than 2 mm. In this embodiment of the present disclosure, the minimum spacing e1 between two adjacent reflective patterns 2 is greater than 2 mm along the first direction X, and the minimum spacing e2 between two adjacent reflective patterns 2 is greater than 2 mm along the second direction Y. This allows for a more obvious dividing line between adjacent reflective patterns 2, provided that the accuracy of the exposure and development equipment allows it, thereby releasing the tensile stress generated on the circuit board due to the installation of the first reflective layer 2.

[0115] Specifically, e1 and e2 can be approximately equal, and e3 and e4 can be approximately equal; specifically, 2mm < e1 < 50mm, 2mm < e2 < 50mm; specifically, 6mm < e3 < 100mm, 6mm < e4 < 100mm.

[0116] In one possible implementation, combining Figure 3 As shown, the outer contour shape of the orthographic projection of the reflective pattern 2 onto the substrate 1 is similar to the shape formed by the distribution areas of the first component pad area 31 and the second component pad area 32 within the same device region 5. Specifically, for example, as... Figure 7A As shown, the shape formed by the distribution areas of the first component pad area 31 and the second component pad area 32 within the same device area 5 is a "cleaver" shape. Therefore, the outer contour shape of the orthographic projection of the reflective pattern 2 onto the substrate 1 is also a "cleaver" shape. Of course, the shape formed by the distribution areas of the first component pad area 31 and the second component pad area 32 within the same device area 5 can also be other shapes. For example, such as... Figure 7B As shown, the shape formed by the distribution areas of the first element pad area 31 and the second element pad area 32 within the same device area 5 is rectangular, so the outer contour shape of the orthographic projection of the reflection pattern 2 onto the substrate 1 can also be rectangular.

[0117] In one possible implementation, combining Figure 3As shown, the outer contours of each reflective pattern 2 are identical.

[0118] In one possible implementation, at least two reflective patterns 2 have different shapes. Specifically, the shape difference may be due to the different number of elements distributed within their enclosed areas, or the same number of elements, but different element types and / or differences in element distribution density.

[0119] In one possible implementation, the material of the first reflective layer is a thermosetting white ink or a photosensitive white ink.

[0120] Specifically, white ink can reflect light onto the light-emitting side of the circuit board, increasing light utilization. However, in actual manufacturing processes, uneven thickness of the first reflective layer due to manufacturing processes can cause color differences at different locations, resulting in uneven reflection. In one possible implementation, see... Figures 12A-14 As shown, where, Figure 12A This is a cross-sectional view of a circuit board. Figure 13 This is a top view of the second reflective layer 6. Figure 15 This is a top view schematic diagram of a circuit board with a second reflective layer. Figure 14 This is a top view of another circuit board with a second reflective layer. The circuit board also includes a second reflective layer 6 located on the side of the first reflective layer 20 facing away from the substrate 1. The second reflective layer 6 can be disposed on the side of the first reflective layer 20 facing away from the substrate 1 by attachment or other means. The second reflective layer 6 can further improve light utilization and improve the uneven reflection effect between different device regions 5.

[0121] In one possible implementation, the second reflective layer 6 can be a reflective sheet, which can be attached to or stacked on the side of the first reflective layer 20 facing away from the substrate 1. Specifically, see... Figure 12B As shown, Figure 12B for Figure 3 Another cross-sectional view along the dashed line AA' shows that the second reflective layer 6 may include a substrate 601, a first film layer 602 located on the side of the substrate 601 away from the first reflective layer 20, and a second film layer 602 located on the side of the substrate 601 facing the first reflective layer 20. Specifically, the substrate 601 may contain dispersed scattering particles and / or microbubbles; specifically, the material of the scattering particles may be titanium dioxide; specifically, the material of the substrate 601 may be polyethylene terephthalate or polypropylene; specifically, the first film layer 602 may be a scattering layer, the material of the first film layer 602 may be titanium dioxide, and the second film layer 603 may be a reflective material layer, specifically, a white ink material may be used.

[0122] In one possible implementation, combining Figures 12A-14As shown, the second reflective layer 6 has a second cutout 60 in the area where the pad region 3 is located; the orthographic projection area of ​​the second cutout 60 on the substrate 1 is larger than the orthographic projection area of ​​the first cutout 30 on the substrate 1, and the orthographic projection of the first cutout 30 on the substrate 1 is located within the orthographic projection of the second cutout 60 on the substrate 1. In this embodiment of the present disclosure, the orthographic projection area of ​​the second cutout 60 on the substrate 1 is larger than the orthographic projection area of ​​the first cutout 30 on the substrate 1, and the orthographic projection of the first cutout 30 on the substrate 1 is located within the orthographic projection of the second cutout 60 on the substrate 1, which can ensure that the light-emitting element soldered to the pad region 3 can emit light sufficiently, and avoid the second cutout 60 affecting the light emission of the light-emitting element.

[0123] In one possible implementation, combining Figures 12A-14 As shown, within the circuit board, the minimum spacing between each of the second cutouts 60 and the pad area 3 located in the orthographic projection is approximately the same. Specifically, for example, combined with... Figure 15 or Figure 14 As shown, in the non-edge region of the circuit board parallel to the first direction X, the minimum distance between the second cutout 60 and the pad area 3 within its orthographic projection is f1. In the edge region of the circuit board, the minimum distance between the second cutout 60 and the pad area 3 within its orthographic projection is f2. f1 and f2 are approximately the same. In specific implementation, the second reflective layer 6 in this embodiment can be baked at high temperature before being formed on the circuit board. When the baking temperature T is greater than the initial temperature Tg, the free volume of the reflective sheet is released, and then it is naturally cooled to room temperature, causing it to shrink to the free volume corresponding to room temperature. When the subsequent process is under high temperature conditions again, the volume of the second reflective layer 6 does not shrink or only shrinks slightly, thereby reducing the warpage value of the circuit board. The second reflective layer 6 after high temperature baking and natural cooling can make the minimum distance between each second cutout 60 and the pad area 3 in the orthographic projection approximately the same in different areas of the circuit board. This can avoid the problem that when the second reflective layer 6 without high temperature baking is attached to the first reflective layer 2, the size of the second cutout 6 in the non-edge area and the edge area of ​​the second reflective layer 6 will be different due to the stretching of the second reflective layer 6 during the attachment process. After being attached to the first reflective layer 2, this will cause the distance between each pad area 3 and the second cutout 60 in the same direction to be different in different areas of the circuit board, resulting in uneven light output brightness in different areas of the circuit board.

[0124] In one possible implementation, the minimum distance between the second cutout 60 and the pad area 3 located in the orthographic projection is f1, which is less than the minimum distance e3 between two adjacent pad areas 3 in the first direction X. Specifically, the range of the minimum distance f1 between the second cutout 60 and the pad area 3 located in the orthographic projection can be 0.45mm < f1 < 1mm.

[0125] It should be noted that even after high-temperature treatment and natural cooling, the second reflective layer 6 may still not be able to ensure that the spacing between each pad area 3 and the second cutout 60 containing the pad area 3 is exactly the same in the same direction due to actual process errors (e.g., equipment alignment errors). Therefore, in this embodiment, the spacing between each pad area 3 and the second cutout 60 containing the pad area 3 in the same direction is approximately the same. This can be understood as the difference in spacing between the pad area 3 and the second cutout 60 containing the pad area 3 in the same direction in any two areas of the circuit board being less than 10% of the ratio of the spacing between the pad area 3 and the second cutout 60 containing the pad area 3 in the same direction in any one of the areas. Specifically, for example, as Figure 14 In the circuit board, the difference between f1 and f2 is a1 in the internal region and a2 in the edge region. Therefore, (a1-a1) / f1 < ±10% and (a1-a1) / f2 < ±10%.

[0126] In one possible implementation, combining Figure 12A , Figure 15 and Figure 14 As shown, the orthographic projection of the area of ​​the second reflective layer 6, excluding the second cutout 60, onto the substrate 1 at least covers the orthographic projection of the gap between two adjacent reflective patterns 2 onto the substrate 1. In this embodiment, the orthographic projection of the second reflective layer 6 onto the substrate 1 at least covers the orthographic projection of the gap between adjacent reflective patterns 2 onto the substrate 1, which can block the gap between adjacent reflective patterns 2. This allows the areas on the circuit board without reflective patterns 2 to be covered by the subsequently installed second reflective layer 6 without affecting the optical performance of the product.

[0127] In one possible implementation, combining Figure 12A , Figure 15 and Figure 14 As shown, the orthographic projection of the area of ​​the second reflective layer 6, excluding the second cutout 60, onto the substrate 1 overlaps with the portion of the orthographic projection of the reflective pattern 2 onto the substrate 1. For example, as... Figure 15 or Figure 14 In the second reflective layer 6, the area other than the second cutout 60, in the orthographic projection on the substrate 1 also covers the part around the first cutout 30 of the reflective pattern 2. That is, the orthographic projection size of the second cutout 60 on the substrate 1 is smaller than the orthographic projection size of the reflective pattern 2 on the substrate 1, so as to ensure that the area on the circuit board not covered by the reflective pattern 2 can be partially covered by the second reflective layer 6, thereby improving the optical performance of the product.

[0128] In specific implementation, such as Figure 14As shown, on the one hand, the minimum size L of the second cutout 60 in the second reflective layer 6 is determined by the processing technology. Taking the shape of the second cutout 60 as a circle as an example, the minimum size of the second cutout 60 refers to its diameter. The minimum diameter produced by the current processing method is approximately 1.5mm. On the other hand, the outer contour size L0 of the reflective pattern 2 is related to L. A reflective pattern 2 encloses at least one pad area 3, and adjacent reflective patterns 2 are spaced apart. Therefore, the maximum size L0 of the outer contour of the reflective pattern 2 is related to the spacing between adjacent components on the circuit board. It can be understood that when the outer contour shape of the reflective pattern 2 is polygonal, the maximum size refers to its diagonal length; if the outer contour shape of the reflective pattern 2 is circular, the maximum size refers to its diameter; and if the outer contour shape of the reflective pattern 2 is elliptical, the maximum size refers to its major axis length. In the design, L0 needs to be slightly larger than L, for example, satisfying L0 > L + reflective sheet mounting accuracy; where the mounting accuracy is determined by the equipment accuracy, for example, the value range of the mounting accuracy is 0-0.2mm. In addition, in order to further improve the light utilization rate of the circuit board, the size of the second cutout 60 should not be too large, for example, 3mm > L ≥ 1.5mm.

[0129] In some embodiments, a protective structure may be further provided on the component. Combined with Figure 18 As shown, the size L of the second cutout 60 needs to be slightly smaller than the outline size of the protective structure 73 projected onto the substrate 1, so that there is an overlapping area between the second reflective layer 6 and the protective structure 73, and the two can partially contact each other to achieve a more secure fixation.

[0130] Furthermore, such as Figure 14 As shown, whether a reflective pattern 2 on a circuit board encloses only one pad area 3 is determined by three factors: the spacing P between adjacent pad areas 3, the outer contour dimension L0 of the reflective pattern 2, and the precision of the patterning process. If the spacing P between any two components on the circuit board is greater than (L0 + process precision), that is, the minimum distance between two adjacent reflective patterns 2 (such as L1 and L1') is greater than 0, then each pad area 3 can be enclosed by one reflective pattern 2. It is understandable that if the spacing P between some pad areas 3 on the circuit board does not meet the above conditions, the minimum distance between two adjacent reflective patterns 2 (such as L1 and L1') will be less than or equal to 0, meaning that the two reflective patterns 2 have overlapping areas and are interconnected. In this case, it is possible to consider enclosing multiple closely spaced pad areas 3 with one reflective pattern 2.

[0131] It is understandable that the first element is used to implement the main function of the circuit board. Multiple first elements are arranged in a certain pattern and the arrangement density is relatively large. Therefore, the spacing between the first elements is relatively small. The second element (such as micro IC, sensor, etc.) is less numerous and is only placed in local positions on the circuit board. For example, it is usually placed in the gap between two adjacent first elements. Therefore, if a second element is placed between two adjacent first elements, for example, if at least one second element overlaps with the line connecting the geometric centers of two adjacent first elements, a reflective pattern 2 is used to surround the two first elements and at least one second element located between them.

[0132] Furthermore, a single circuit board can have a variety of reflective patterns with different outer contour shapes.

[0133] In the case where the first element is a light-emitting diode, in some embodiments, the purpose of setting the second reflective layer 6 is to further improve the utilization rate of light. Therefore, for non-optical functional elements on the circuit board, such as the second element, the second reflective layer 6 may not have a cutout in the area where the non-optical functional element is located. However, this will affect the flatness of the second reflective layer 6. To improve this problem, a cross or straight slit can be set in the position of the second reflective layer 6 corresponding to the area where the non-optical functional element is located.

[0134] In some embodiments, such as Figure 15 As shown, a device area 5 includes four first pad areas 31 (for soldering first components) and one second pad area 32 (for soldering second components). The four first components are connected in series, or in parallel and then in series, or in parallel; there is no limitation here. The second pad area 32 is located within a quadrilateral formed by the geometric centers of the four first pad areas 31 connected in sequence.

[0135] All components in a device area 5 are surrounded by a reflective pattern 2. That is, all components of a device area 5 are distributed within the area enclosed by the outer contour of the reflective pattern 2. The first cutouts 30 in the reflective pattern 2 expose each pad area 3. Because the first and second components have different sizes, the shapes and sizes of the first pad area 31 and the second pad area 32 differ. Correspondingly, the shapes and sizes of the first cutouts 30 corresponding to the pad areas 3 also differ. That is, the second cutouts 60 in the second reflective layer 6, such as the second cutout 60 corresponding to the first pad area 31 and the second cutout 60' corresponding to the second component, can also have different sizes. For example, the second cutouts 60 and 60' are both circular, with diameters L and L' respectively, where L' > L.

[0136] In some embodiments, a device region 5 may include more first elements, and the connection relationship between the multiple first elements can be designed as needed. At the same time, the arrangement of the first elements belonging to the same device region 5 is not limited to array arrangement along the X and Y directions, but can also be other ways, without limitation.

[0137] In one possible implementation, see Figure 16 As shown, where, Figure 16 for Figure 15 A cross-sectional schematic diagram along the dotted line AA' shows that an adhesive layer 63 is also present between the second reflective layer 6 and the first reflective layer 20. The second reflective layer 6 is attached to the first reflective layer 20. Specifically, the adhesive layer 63 may have a third perforation in the area corresponding to the second perforation 60 to facilitate the subsequent placement and connection of the first component to the first soldering area 31, or the placement and connection of the second component to the second soldering area 32.

[0138] In one possible implementation, the viscosity of the adhesive layer 63 is in the range of 800 Pa·s to 2000 Pa·s. Typically, to enhance the adhesion of the second reflective layer 6 (e.g., a reflective sheet) to the first reflective layer 20, the viscosity of the adhesive film on the second reflective layer 6 needs to be relatively high (>3000 Pa·s). Subsequent dispensing processes (e.g., forming a protective structure for the light-emitting element), and subsequent high-temperature baking (100°C to 150°C) after dispensing, further increase substrate stress, thereby increasing substrate warpage. To improve this problem, in this embodiment, the viscosity of the adhesive layer 63 is in the range of 800 Pa·s to 2000 Pa·s. By reducing the viscosity of the adhesive layer 63 on the second reflective layer 6 while maintaining adhesion, the warpage of the circuit board can be reduced.

[0139] In one possible implementation, combining Figure 13 , Figure 14 as well as Figure 18As shown, the outer contour of the reflective pattern 2 is a circle, rectangle, polygon, or ellipse, etc., and the pad area 3 is rectangular. In this embodiment, the shape of the pad area 3 is rectangular, and the shape of the pad area 3 is the same as or similar to the orthographic projection shape of the component to be connected to the pad in the pad area 3 on the substrate 1, which makes it easy to solder the component to the pad area 3. In this embodiment, multiple reflective patterns 2 of the first reflective layer need to be formed on the circuit board first; then, a second reflective layer 6 with a second cutout 60 is formed on the side of the first reflective layer 20 away from the substrate 1; subsequently, components (such as the first component 71) are soldered to the pads 33; then, a protective structure 73 is set on the side of the component (such as the first component 71) away from the substrate 1 by drop-casting or printing process to protect the component from external water and oxygen corrosion; since the protective structure 73 needs to cover the second cutout 60 of the second reflective layer 6, and since the protective structure 73 is prepared by drop-casting or printing, its orthogonal projection shape on the substrate 1 is circular or elliptical. In order to ensure product uniformity and reduce process errors and difficulties, the orthogonal projection shape of the second cutout 60 on the substrate 1 is similar to the orthogonal projection shape of the protective structure 73 on the substrate 1, that is, the orthogonal projection shape of the second cutout 60 on the substrate 1 is circular, regular polygonal, or elliptical. In some embodiments, in order to make it easier for the second reflective layer 6 to be aligned or attached to the first reflective layer, the orthographic projection shape of the outer contour of the reflective pattern 2 onto the substrate 1 is kept similar to the orthographic projection shape of the second cutout 60 onto the substrate 1. That is, the orthographic projection shape of the outer contour of the reflective pattern 2 onto the substrate 1 is a circle, rectangle, polygon, or ellipse.

[0140] Figure 17A The diagram illustrates the results of testing the warpage value of a substrate after a first reflective layer with different film patterns is applied to a quadrilateral substrate. Eight sites are selected at equal intervals in four regions near the four edges of the substrate. The first reflective layers on samples 1 and 2 are a single, interconnected film layer. The first reflective layers 20 on samples 3 and 4 include multiple spaced reflective patterns 2, each containing at least one device region 5, for example, having… Figure 3 Or such as Figure 9 The reflective pattern 2 shown; the first reflective layer 20 on samples 5 and 6 includes multiple mutually spaced reflective patterns 2, each reflective pattern 2 containing only one pad area 3, for example having Figure 6 The reflection pattern 2 shown. From Figure 17AAs can be seen, the maximum warpage value of the first reflective layer on samples 1 and 2 is 1.4 mm, while the maximum warpage values ​​of the first reflective layers on samples 3 and 4 and samples 5 and 6 are 0.65 mm and 0.45 mm, respectively. By designing the first reflective layer with multiple mutually spaced reflective patterns, the tensile stress generated by the near-high temperature conditions (such as curing) required during the fabrication of the first reflective layer can be reduced, thereby reducing the warpage value of the substrate.

[0141] Furthermore, taking an adhesive layer 63 with a viscosity of 3000 Pa·s on the second reflective layer 6 as an example, the second reflective layer 6 is pre-baked at a high temperature before the first reflective layer 20 is attached. The pre-baked second reflective layer 6 is then attached, and the circuit board warpage is measured as follows: Figure 17B As shown, where, Figure 17B The diagram illustrates the results of warpage tests conducted on a quadrilateral substrate with a second reflective layer. The tests compared conditions such as whether the second reflective layer was baked before application and the viscosity of the adhesive layer used. Eight points were selected at equal intervals in four regions near the four edges of the substrate for each region. Specifically, for samples 1 and 2, an adhesive layer with a viscosity of 3000 Pa·s was used, and the unbaked second reflective layer was applied to the substrate. For samples 3 and 4, an adhesive layer with a viscosity of 3000 Pa·s was used, and the baked second reflective layer was applied to the substrate. For samples 5 and 6, an adhesive layer with a viscosity of 800 Pa·s was used, and the unbaked second reflective layer was applied to the substrate. Figure 17B As can be seen, when using an adhesive layer of the same viscosity, the maximum warpage of the substrate is 4.75 mm when the unbaked second reflective layer 6 is placed on the substrate, while the maximum warpage is 3.5 mm when the second reflective layer 6 is baked before being attached to the substrate, significantly reducing the warpage. (See also...) Figure 17B As shown, when the viscosity of the adhesive layer 63 on the second reflective layer 6 is 3000 Pa·s, the maximum warpage of the substrate is 4.75 mm. However, when the viscosity of the adhesive layer is reduced to 800 Pa·s, the maximum warpage of the substrate is reduced to 3.85 mm. Therefore, reducing the viscosity of the adhesive layer 63 can reduce the warpage of the substrate.

[0142] Based on the same inventive concept, this disclosure also provides an electronic device, including a circuit board as provided in this disclosure, and a plurality of first elements 71 and / or a plurality of second elements 72, wherein each of the plurality of first elements 71 is connected to a first element pad area 31, and each of the plurality of second elements 72 is connected to a second element pad area 32.

[0143] For specific implementation, see Figure 18 As shown, Figure 18 It can be Figure 15 A cross-sectional view showing the component soldered onto the pad at the dashed line AA'. The first component 71 can be a light-emitting element, which can include a light-emitting part 711 and pins 712. The light-emitting element can be either a Mini Light Emitting Diode (Mini LED) or a Micro Light Emitting Diode (Micro LED); Mini LEDs have a size greater than or equal to 80μm and less than 500μm; Micro LEDs have a size less than 80μm. A protective structure 73 can also be provided on the side of the light-emitting element away from the substrate 1, and the surface of the protective structure 73 away from the substrate 1 can be curved. The second component can be a micro control chip used to control the light emission of the light-emitting elements within the same device area 5. In combination with... Figure 16 and Figure 18 As shown, the protective structure 73 can fill the area where the first cutout 30 of the first reflective layer 20 is located, the area where the second cutout 60 of the second reflective sheet 6 is located, and the area where the adhesive layer 63 is located corresponding to the second cutout 60. Specifically, in conjunction with Figure 15 and Figure 18As shown, the dimension h of substrate 1 in the Z direction is between 0.5 mm and 1.0 mm. Specifically, for example, h can be between 0.6 mm and 0.8 mm, and specifically, for example, h can be 0.7 mm. Substrate 1 may include organic resin materials such as epoxy resin, triazine, silicone resin, or polyimide. In some example embodiments, substrate 1 may be an FR4 type printed circuit board (PCB), or it may be a flexible PCB that is easily deformable. In some example embodiments, substrate 1 may include ceramic materials such as silicon nitride, AlN, or Al2O3, or metals or metal compounds. Substrate 1 may be such as a metal core printed circuit board (MCPCB) or a metal copper clad laminate (MCCL). The width d0 of each pad 33 in the pad area 3 parallel to the first direction X can be 150μm to 250μm. Specifically, for example, d0 can be 180μm to 220μm, or even 200μm, 202μm, 204μm, or 206μm. Specifically, the dimension h2 of the first reflective layer 20 in the Z direction can be 10μm to 50μm. Specifically, for example, h2 can be 20μm to 40μm, or even 25μm, 30μm, or 202μm. m, 35μm or 40μm; specifically, the width of the first reflective layer 20 in the first direction X can be designed according to the shape and size of the specific reflective pattern 2, and this embodiment does not limit it here; specifically, the dimension h3 of the second reflective layer 6 in the Z direction can be 80μm to 120μm, specifically, for example, h3 can be 90μm to 110μm, specifically, for example, h3 can be 95μm, 100μm, 105μm or 110μm; specifically, the dimension h of the first element 71 in the Z direction is... 4 can be 80μm to 120μm, h4 can be 90μm to 110μm, specifically, for example, h4 can be 95μm, 100μm, 105μm or 110μm; specifically, the width d3 of the first element 71 in the first direction X can be 300μm to 500μm, d3 can be 350μm to 450μm, specifically, for example, d3 can be 390μm, 400μm, 410μm or 420μm; specifically, when the protective structure 73 is hemispherical, the hemispherical protective structure 7 3. The dimension h5 in the Z direction can be 0.3mm to 0.8mm, specifically, for example, h5 can be 0.4mm to 0.7mm, specifically, for example, h5 can be 0.45mm, 0.5mm, 0.55mm or 0.6mm; specifically, the diameter d5 of the hemispherical protective structure 73 can be 2.0mm to 3.0mm, specifically, for example, d5 can be 2.3mm to 2.7mm, specifically, for example, d5 can be 2.3mm, 2.4mm, 2.5mm or 2.6mm.

[0144] Specifically, when the protective structure 73 is set using a drop-in or printing process, air bubbles may enter the area to be enclosed by the protective structure 73. Since the protective structure 73 needs to be cured and molded at high temperature afterward, air bubbles may remain in the aforementioned area. Therefore, the surfaces of the first reflective layer 20, adhesive layer 63, and / or the first reflective layer 6 facing the element can, for example, have an angle of 30°-80° with the plane of the substrate 1, thus facilitating gas expulsion during the drop-in or printing process.

[0145] In one possible implementation, combining Figure 19 As shown, Figure 19 It can be Figure 15 Another cross-sectional view along the dashed line AA' and after the component is soldered on the pad. The substrate 1 may include a substrate 10 and a first trace layer 11 disposed on the side of the substrate 10 facing the first reflective layer 20. Specifically, the first trace layer 11 may be a single trace layer, or the first trace layer 11 may be a composite layer including multiple sub-trace layers. An insulating layer may be disposed between adjacent sub-trace layers. For example, one sub-trace layer may be used to lay series lines connecting different first components in the same device area 5, and another sub-trace layer may be used to lay voltage traces or other signal traces for providing electrical signals to the device area.

[0146] In one possible implementation, combining Figure 20 As shown, Figure 20 It can be Figure 15 Another cross-sectional view along the dashed line AA' and after components are soldered onto the pads. The substrate 1 may include a substrate 10 and a first trace layer 11 disposed on the side of the substrate 10 facing the first reflective layer 20. It may also include a second trace layer located on the substrate 10 away from the first trace layer 11. Specifically, the first trace layer 11 may be a single-layer trace layer used to lay series lines connecting different first components in the same device area 5. The second trace layer 12 may be a single-layer trace layer used to lay voltage traces or other signal traces for providing electrical signals to the device area.

[0147] In one possible implementation, see Figure 21 As shown, the first elements 71 in the same device area 5 are connected in series.

[0148] In one possible implementation, each of the first elements 71 in the same device region 5 is electrically connected to the second element 72.

[0149] Based on the same inventive concept, this disclosure also provides a method for manufacturing the circuit board provided in this disclosure, such as... Figure 22 As shown, it includes:

[0150] Step S100: Provide a substrate; specifically, in conjunction with... Figure 19 As shown, substrate 1 may include substrate 10 and a first wiring layer 11 disposed on one side of substrate 10. Specifically, the first wiring layer 11 may be a single wiring layer, or the first wiring layer 11 may be a composite layer including multiple sub-wiring layers. An insulating layer may be disposed between adjacent sub-wiring layers. Specifically, for example, one sub-wiring layer may be used to lay series lines connecting different first components in the same device region 5, and another sub-wiring layer may be used to lay voltage lines or other signal lines for providing electrical signals to the device region. Alternatively, in combination with... Figure 20 As shown, substrate 1 may include a substrate 10 and a first wiring layer 11 disposed on one side of substrate 10, and may also include a second wiring layer 12 located on substrate 10 away from the first wiring layer 11. Specifically, the first wiring layer 11 may be a single-layer wiring layer used to lay series lines connecting different first components within the same device region 5, and the second wiring layer 12 may be a single-layer wiring layer used to lay voltage lines or other signal lines for providing electrical signals to the device region. Specifically, substrate 1 may also include a plurality of pads 33 located on the first wiring layer 11.

[0151] Step S200: A first reflective layer having multiple mutually spaced reflective patterns is formed on one side of the substrate.

[0152] In one possible implementation, regarding step S200, forming a first reflective layer having a plurality of mutually spaced reflective patterns on one side of the substrate includes:

[0153] Step S211: Coat a first reflective film on one side of the substrate;

[0154] Step S212: A first reflective layer is formed by a partitioned exposure process, which has multiple mutually spaced reflective patterns and exposes each pad area, wherein at least one device area is distributed in each reflective pattern.

[0155] In one possible implementation, regarding step S200, forming a first reflective layer having a plurality of mutually spaced reflective patterns on one side of the substrate includes:

[0156] Step S221: Coat a first reflective film on one side of the substrate;

[0157] Step S222: A first reflective layer is formed by a regional exposure process, which has multiple mutually spaced reflective patterns and exposes each pad area, wherein each reflective pattern contains a pad area.

[0158] In one possible implementation, see Figure 23As shown, after step S200, that is, after forming a first reflective layer having multiple mutually spaced reflective patterns on one side of the substrate, the fabrication method further includes:

[0159] Step S300: Provide a reflective structure, wherein, see Figure 24 As shown, the reflective structure includes a second reflective layer 6, an adhesive layer 63 located on one side of the second reflective layer 6, a first protective layer 61 located on the side of the adhesive layer 63 opposite to the second reflective layer 6, and a second protective layer 62 located on the side of the second reflective layer 6 opposite to the adhesive layer 63.

[0160] Step S400: Bake the reflective structure and make the baking temperature higher than the initial temperature Tg. The initial temperature Tg is the temperature at which the cooling rate and the volume discharge rate do not match.

[0161] Step S500: Remove the first protective layer of the cooled reflective structure, and attach the second reflective layer to the side of the first reflective layer away from the substrate using an adhesive layer.

[0162] Step S600: Remove the second protective layer.

[0163] Specifically, after removing the second protective layer, components (first component 71 and / or second component 72) can be placed on the pad 33 through a die bonding process. After that, an electrical test can be performed to check the soldering condition between the component and the pad 33. If a defect is found, the problem can be identified in time and a rework process can be carried out. If the electrical test passes, a protective structure 73 can be further formed on the component through a drop-in or printing process.

[0164] In this embodiment of the present disclosure, before the second reflective layer 6 is formed on the circuit board, the reflective structure including the second reflective layer 6 can be baked at a high temperature (T>Tg) to release the free volume of the reflective sheet. Then, it can be cooled naturally to shrink to the free volume corresponding to room temperature. When it is baked at a high temperature again in subsequent processes, the volume of the second reflective layer 6 does not shrink or only shrinks slightly, thereby reducing the warpage of the circuit board.

[0165] The beneficial effects of the embodiments of this disclosure are as follows: In the embodiments of this disclosure, the first reflective layer includes a plurality of mutually spaced reflective patterns 2, and there is a gap between adjacent reflective patterns 2. The first reflective layer is formed as a film layer with a plurality of mutually spaced reflective patterns 2. Compared with a first reflective layer that is interconnected everywhere, the first film layer with a plurality of mutually spaced reflective patterns 2 can release stress and avoid the problem of circuit board warping when forming a first reflective layer that is interconnected everywhere.

[0166] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0167] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A circuit board, wherein, include: Substrate; Multiple pad areas are located on the substrate; A first reflective layer is located on the same side of the substrate as the plurality of pad areas. The first reflective layer has a first cutout, through which each of the plurality of pad areas can be exposed. The first reflective layer includes a plurality of mutually spaced reflective patterns with gaps between adjacent reflective patterns. The circuit board further includes a second reflective layer located on the side of the first reflective layer opposite to the substrate.

2. The circuit board as described in claim 1, wherein, At least one of the plurality of pad areas is distributed within the area enclosed by the outer contour of at least one of the reflective patterns.

3. The circuit board as described in claim 2, wherein, The minimum size of any of the reflective patterns is greater than the maximum size of the pad area within the area enclosed by the reflective pattern, and only one of the plurality of pad areas is distributed within the area enclosed by the outer contour of at least one of the reflective patterns.

4. The circuit board as described in claim 3, wherein, At least one of the outer contour shapes of the reflective pattern is different from the shape of the pad area within the area enclosed by the reflective pattern.

5. The circuit board as described in claim 4, wherein, At least one of the outer contour shapes of the reflective pattern is any one of the shapes such as circle, rectangle, polygon or ellipse, and the pad area within the area enclosed by the reflective pattern is rectangular.

6. The circuit board as described in claim 2, wherein, The plurality of pad areas include a first component pad area and / or a second component pad area, wherein the number of pads or the size of pads included in the first component pad area and the second component pad area are different.

7. The circuit board as described in claim 6, wherein, The circuit board includes multiple device areas; each device area includes at least one first element pad area and / or at least one second element pad area; at least one of the device areas is distributed within the area enclosed by at least one of the outer contours of the reflective pattern.

8. The circuit board as described in claim 6, wherein, At least one of the reflection patterns includes a first sub-reflection pattern and a second sub-reflection pattern; The at least two first element pad areas of the same device region are distributed in an array within the area enclosed by the outer contour of the first sub-reflective pattern. The second element pad area of ​​the same device area is distributed in the second sub-reflection pattern.

9. The circuit board as described in claim 8, wherein, In at least one of the reflected patterns, the first sub-reflective pattern and the second sub-reflective pattern are interconnected and form an integral structure.

10. The circuit board as claimed in claim 9, wherein, At least one of the reflected patterns has an outer contour shape in the orthographic projection on the substrate that is similar to the shape formed by the distribution areas of the first element pad area and the second element pad area within the same device region.

11. The circuit board according to any one of claims 1-10, wherein, All of the described reflective patterns have the same shape.

12. The circuit board according to any one of claims 1-10, wherein, At least two of the reflected patterns have different shapes.

13. The circuit board as claimed in claim 12, wherein, The reflective patterns are arranged in an array; along the first direction, the minimum spacing between two adjacent reflective patterns is the same, and along the second direction, the minimum spacing between two adjacent reflective patterns is the same.

14. The circuit board as claimed in claim 13, wherein, Along the first direction, the ratio of the minimum spacing between two adjacent pad areas in the plurality of pad areas to the minimum spacing between two adjacent reflection patterns along the first direction ranges from 3 to 10. Along the second direction, the ratio of the minimum spacing between two adjacent pad areas in the plurality of pad areas to the minimum spacing between two adjacent reflection patterns along the second direction ranges from 3 to 10.

15. The circuit board as claimed in claim 13, wherein, Along the first direction, the minimum spacing between two adjacent reflective patterns is greater than 2 mm; Along the second direction, the minimum spacing between two adjacent reflective patterns is greater than 2 mm.

16. The circuit board as claimed in claim 15, wherein, The material of the first reflective layer is white ink.

17. The circuit board as claimed in claim 16, wherein, The second reflective layer has a second cutout in the area where the pad area is located; The projected area of ​​the second cutout on the substrate is larger than the projected area of ​​the first cutout on the substrate, and the projected area of ​​the first cutout on the substrate is located within the projected area of ​​the second cutout on the substrate.

18. The circuit board as claimed in claim 17, wherein, The area of ​​the second reflective layer, excluding the second cutout, in its orthogonal projection onto the substrate, at least covers the orthogonal projection of the gap between two adjacent reflective patterns onto the substrate.

19. The circuit board as claimed in claim 18, wherein, The orthographic projection of the area of ​​the second reflective layer, excluding the second cutout, onto the substrate overlaps with a portion of the orthographic projection of at least one of the reflective patterns onto the substrate.

20. The circuit board according to any one of claims 17-19, wherein, Within the circuit board, the minimum spacing between each of the second cutouts and the pad area located in the orthographic projection is approximately the same.

21. The circuit board as claimed in claim 20, wherein, Along the first direction, the minimum distance between the second cutout and the pad area located within the orthographic projection is less than the minimum distance between two adjacent pad areas among the plurality of pad areas.

22. The circuit board as claimed in claim 21, wherein, An adhesive layer is also provided between the second reflective layer and the first reflective layer.

23. The circuit board as claimed in claim 22, wherein, The viscosity range of the adhesive layer is 800 Pa. s ~ 2000 Pa s.

24. The circuit board as claimed in claim 23, wherein, The second reflective layer includes a substrate, a first film layer located on the side of the substrate away from the first reflective layer, and a second film layer located on the side of the substrate facing the first reflective layer.

25. The circuit board as claimed in claim 24, wherein, The substrate contains scattering particles and / or microbubbles.

26. The circuit board as claimed in claim 25, wherein, The substrate material includes polyethylene terephthalate or polypropylene; the first film layer material includes titanium dioxide; and the second film layer material includes a white oil coating.

27. An electronic device, wherein, The circuit board includes any one of claims 1-26, and a plurality of first elements and / or a plurality of second elements, wherein each of the plurality of first elements is connected to a pad area of ​​a first element, and each of the plurality of second elements is connected to a pad area of ​​a second element.

28. The electronic device of claim 27, wherein, The first elements in the same device region are interconnected.

29. A method for manufacturing a circuit board as described in any one of claims 1-26, wherein, include: Provide a substrate; A first reflective layer having multiple mutually spaced reflective patterns is formed on one side of the substrate.

30. The manufacturing method as described in claim 29, wherein, The formation of a first reflective layer having multiple mutually spaced reflective patterns on one side of the substrate includes: A first reflective film is coated on one side of the substrate; A first reflective layer is formed by a partitioned exposure process, having multiple mutually spaced reflective patterns and exposing at least a portion of the multiple pad areas, wherein at least one device area is distributed within at least one of the reflective patterns.

31. The manufacturing method as described in claim 30, wherein, The formation of a first reflective layer having multiple mutually spaced reflective patterns on one side of the substrate includes: A first reflective film is coated on one side of the substrate; A first reflective layer is formed by a regional exposure process, having multiple mutually spaced reflective patterns and exposing at least a portion of the multiple pad areas, wherein at least one of the multiple pad areas is distributed within at least one of the reflective patterns.

32. The manufacturing method according to any one of claims 29-31, wherein, After forming a first reflective layer having multiple mutually spaced reflective patterns on one side of the substrate, the fabrication method further includes: A reflective structure is provided, wherein the reflective structure includes a second reflective layer, an adhesive layer located on one side of the second reflective layer, a first protective layer located on the side of the adhesive layer opposite to the second reflective layer, and a second protective layer located on the side of the second reflective layer opposite to the adhesive layer. The reflective structure is baked at a temperature higher than the initial temperature Tg, where the initial temperature Tg is the temperature at which the cooling rate and the volume discharge rate are mismatched. Remove the first protective layer of the cooled reflective structure, and attach the second reflective layer to the side of the first reflective layer away from the substrate using the adhesive layer; Remove the second protective layer.

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