Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area (A1), and a frame area arranged at a first side edge of the display area (A1); the display area (A1) comprises a center display area (A2), a first display area (A11) and a second display area (A12); the display substrate comprises a plurality of first data signal leads and a plurality of second data signal leads; the first data signal leads comprise first lead portions extending along a first direction, and the second data signal leads comprise second lead portions extending along a second direction; the line width of the first lead portions is smaller than the line width of the second lead portions; and the extension direction of the first data lines and the extension direction of the second data lines are a third direction. The difference between the line resistance values of the data signal leads is reduced, and the display uniformity is improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0002] With the continuous development of flexible screen technology, foldable screen phones are increasingly entering the market. Compared to conventional phones, foldable screen phones have stricter requirements for screen display quality, especially in terms of improving the uniformity of screen display at low grayscale levels. The line resistance of the signal lines used to transmit data voltage is a crucial factor affecting the uniformity of low grayscale levels, and the driving current Ioled is equal to K(VDD-Vdata). 2 In this context, K is the current coefficient of the driving transistor, the first voltage VDD is a fixed voltage, and the data voltage Vdata decreases as the line resistance of the signal lines increases. The smaller the difference in line resistance between the signal lines, the better the uniformity of low grayscale. Therefore, to improve display uniformity, resistance compensation is required for the signal lines. Summary of the Invention

[0003] The main objective of this disclosure is to provide a display substrate and a display device that solves the problems of color deviation and poor display uniformity caused by large differences in the line resistance of various data signal leads in the related art.

[0004] In one aspect, embodiments of the present disclosure provide a display substrate including a display area and a border area disposed on a first side of the display area;

[0005] The display area includes a central display area, a first display area disposed on a second side of the central display area, and a second display area disposed on a third side of the central display area; the second side and the third side are opposite sides.

[0006] The display substrate includes multiple first data lines disposed in the central display area, multiple second data lines disposed in the first display area and the second display area, and multiple first data signal leads and multiple second data signal leads disposed in the border area; the first data signal leads are coupled to the first data lines, and the second data signal leads are coupled to the second data lines.

[0007] The first data signal lead includes a first lead portion extending along a first direction, and the second data signal lead includes a second lead portion extending along a second direction;

[0008] The line width of the first lead portion is smaller than the line width of the second lead portion;

[0009] The extension direction of the first data line and the extension direction of the second data line are in a third direction, the first direction intersects the third direction, and the second direction intersects the third direction;

[0010] The first direction and the third direction have a first angle, and the second direction and the third direction have a second angle.

[0011] Optionally, the line width of the first lead portion is greater than or equal to 1.0 μm and less than or equal to 2.0 μm, and the line width of the second lead portion is greater than or equal to 1.5 μm and less than or equal to 3.0 μm;

[0012] The second data signal lead also includes a third lead portion extending in a fourth direction;

[0013] The line width of the third lead is greater than that of the second lead.

[0014] Optionally, the linewidth of the third lead portion is greater than or equal to 1.8 μm and less than or equal to 4.0 μm;

[0015] The second data signal lead includes a fourth lead portion extending in a third direction;

[0016] The line width of the fourth lead is greater than the line width of the second lead.

[0017] Optionally, the linewidth of the fourth lead portion is greater than or equal to 3µm and less than or equal to 13µm;

[0018] The border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area;

[0019] The line width of the second lead portion in the first fan-out region is smaller than the line width of the second lead portion in the second fan-out region.

[0020] Optionally, the border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; the first data signal lead includes a serpentine lead portion;

[0021] The serpentine lead portion includes a plurality of first lead portions extending along a third direction, and a plurality of second lead portions extending along a fifth direction; the first lead portions and the second lead portions are alternately arranged, and adjacent first lead portions and second lead portions are coupled to each other.

[0022] Optionally, the shortest distance between two adjacent second lead portions included in the same serpentine lead portion is greater than or equal to 2.4 μm and less than or equal to 3 μm; the shortest distance between two adjacent serpentine lead portions is greater than or equal to 1.0 μm and less than or equal to 2 μm, and the line width of the first lead portion and the line width of the second lead portion are both greater than or equal to 1.8 μm and less than or equal to 2.4 μm.

[0023] Optionally, the border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; in the first fan-out area, the sum of the line width of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the line width of the second lead portion and the shortest distance between two adjacent second lead portions.

[0024] In the second fan-out region, the sum of the linewidth of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the linewidth of the second lead portion and the shortest distance between two adjacent second lead portions.

[0025] Optionally, the shortest distance between two adjacent first lead portions is greater than or equal to 1.0 μm and less than or equal to 2.0 μm;

[0026] The shortest distance between two adjacent second lead portions is greater than or equal to 0.5um and less than or equal to 1.0um.

[0027] Optionally, the first included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees, and the second included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0028] Optionally, the border area includes a fan-out area, which includes a first fan-out area and a second fan-out area arranged along a direction away from the display area;

[0029] The display substrate includes a substrate, and a first metal layer and a second metal layer stacked along a direction away from the substrate.

[0030] The first data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer;

[0031] The second data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer;

[0032] The adjacent data signal leads, including the lead portions disposed in the fan-out region, are contained in different layers.

[0033] Optionally, the border area further includes a bent area disposed between the first fan-out area and the second fan-out area, and the display substrate further includes a source / drain metal layer;

[0034] The data signal lead further includes a fifth lead portion disposed in the bending region; the fifth lead portion is contained in the source / drain metal layer.

[0035] Optionally, the display substrate includes a first source / drain metal layer and a second source / drain metal layer. On the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are stacked sequentially in a direction away from the substrate. The fifth lead portion is included in at least one of the first source / drain metal layer and the second source / drain metal layer.

[0036] Optionally, the display substrate includes a first source / drain metal layer, a second source / drain metal layer, and an additional source / drain metal layer; the fifth lead portion is included in at least one of the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer;

[0037] On the side of the second metal layer facing away from the substrate, the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer are sequentially stacked in a direction away from the substrate; or, on the side of the second metal layer facing away from the substrate, the additional source / drain metal layer, the first source / drain metal layer, and the second source / drain metal layer are sequentially stacked in a direction away from the substrate; or, the substrate includes a first substrate and a second substrate stacked together, the additional source / drain metal layer is disposed between the first substrate and the second substrate, and on the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are sequentially stacked.

[0038] Optionally, the fan-out area further includes a third fan-out area, and the frame area further includes an electrostatic protection area and a box-in testing area;

[0039] The second fan-out area, the electrostatic protection area, the cell assembly test area, and the third fan-out area are arranged sequentially along a direction away from the display area;

[0040] The lead portion of the first data signal lead located in the electrostatic protection area and the box test area is disposed in the same layer as the lead portion of the first data signal lead located in the fan-out area.

[0041] The second data signal lead includes a lead portion disposed in the electrostatic protection area and the box test area, which is disposed in the same layer as the lead portion disposed in the fan-out area.

[0042] In a second aspect, embodiments of this disclosure provide a display device including the display substrate described above.

[0043] The display substrate and display device described in this embodiment improve the poor display uniformity caused by excessive differences in line resistance between the data signal leads by setting the line width of the first lead portion coupled to the first data line located in the central display area to be smaller than the line width of the second lead portion coupled to the second data lines located in the display areas on both sides. This makes the line width of the second lead portion larger, which reduces the resistance value of the second data signal lead, and the line width of the first lead portion smaller, which increases the resistance value of the first data signal lead. As a result, the differences in line resistance between the data signal leads are reduced, color shift is improved, and display uniformity is enhanced. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the region division of the display substrate according to at least one embodiment of the present disclosure;

[0045] Figure 2 Is Figure 1 A schematic diagram showing the addition of multiple data lines to the existing structure;

[0046] Figure 3 This is a schematic diagram of the region division of the display substrate according to at least one embodiment of the present disclosure;

[0047] Figure 4 This is eleven figures showing the data signal leads included in at least one embodiment of the display substrate described in this disclosure;

[0048] Figure 5 Is Figure 4 Based on this, a schematic diagram illustrating the identification of each data signal lead is added;

[0049] Figure 6 It shows Figure 5 L2n-2 includes the portion disposed in the first fan-out region F1, L2n-1 includes the portion disposed in the first fan-out region F1, and L2n includes the portion disposed in the first fan-out region F1.

[0050] Figure 7 It shows Figure 5 L11 includes the portion disposed in the first fan-out region F1, L12 includes the portion disposed in the first fan-out region F1, and L13 includes the portion disposed in the first fan-out region F1.

[0051] Figure 8 It shows Figure 5L2n-2 includes the portion disposed in the second fan-out region F2, L2n-1 includes the portion disposed in the second fan-out region F2, and L2n includes the portion disposed in the second fan-out region F2.

[0052] Figure 9 It shows Figure 5 L11 includes the portion disposed in the second fan-out region F2, L12 includes the portion disposed in the second fan-out region F2, and L13 includes the portion disposed in the second fan-out region F1.

[0053] Figure 10 It shows Figure 5 L21 includes the portion disposed in the second fan-out region F2, L22 includes the portion disposed in the second fan-out region F2, and L23 includes the portion disposed in the second fan-out region F2.

[0054] Figure 11 It shows Figure 5 L21 includes the portion disposed in the second fan-out region F2, L22 includes the portion disposed in the second fan-out region F2, and L23 includes the portion disposed in the second fan-out region F2.

[0055] Figure 12 It shows Figure 5 L11 includes the portion located in the first fan-out region F1. Figure 5 L12 includes the portion located in the first fan-out region F1. Figure 5 L13 in the text includes a portion of the first fan-out region F1;

[0056] Figure 13 yes Figure 12 A schematic diagram of the structure of the third serpentine lead section L73;

[0057] Figure 14 It shows Figure 5 The data signal leads in the diagram include the portion located in the bending area B1;

[0058] Figure 15 It shows Figure 5 The data signal leads in the package include the portions located in the electrostatic discharge protection area E1 and the box test area C1;

[0059] Figure 16 It shows Figure 5 L11 includes the portion located in the third fan-out region F3. Figure 5 L12 includes the portion located in the third fan-out region F3. Figure 5 L13 includes the portion located in the third fan-out region F3;

[0060] Figure 17 yes Figure 5 The diagram shows the portion of L21 located in the first fan-out region F1 coupled to the first adapter Z1 through a corresponding first via H1.

[0061] Figure 18 yes Figure 5 The diagram shows that L21, including the portion located in the second fan-out region F1, is coupled to the second adapter Z2 through the corresponding second via H2.

[0062] Figure 19 yes Figure 5 The diagram shows that L22, which includes the portion located in the chip mounting area S1, is coupled to the third adapter Z3 through a corresponding third via H3. Detailed Implementation

[0063] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0064] The display substrate described in this embodiment includes a display area and a border area disposed on a first side of the display area;

[0065] The display area includes a central display area, a first display area disposed on a second side of the central display area, and a second display area disposed on a third side of the central display area; the second side and the third side are opposite sides.

[0066] The display substrate includes multiple first data lines disposed in the central display area, multiple second data lines disposed in the first display area and the second display area, and multiple first data signal leads and multiple second data signal leads disposed in the border area; the first data signal leads are coupled to the first data lines, and the second data signal leads are coupled to the second data lines.

[0067] The first data signal lead includes a first lead portion extending along a first direction, and the second data signal lead includes a second lead portion extending along a second direction;

[0068] The line width of the first lead portion is smaller than the line width of the second lead portion;

[0069] The extension direction of the first data line and the extension direction of the second data line are in a third direction, the first direction intersects the third direction, and the second direction intersects the third direction;

[0070] The first direction and the third direction have a first angle, and the second direction and the third direction have a second angle.

[0071] In at least one embodiment of this disclosure, the first included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees, and the second included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0072] Optionally, the third direction can be a vertical direction, but is not limited thereto.

[0073] In at least one embodiment of this disclosure, the linewidth of each signal line may refer to the width of the signal line along the linewidth direction; the linewidth direction is a direction perpendicular to the extension direction of the signal line.

[0074] In at least one embodiment of this disclosure, the first direction is not perpendicular to the third direction, the first direction is not substantially perpendicular to the third direction, the second direction is not perpendicular to the third direction, and the second direction is not substantially perpendicular to the third direction.

[0075] In at least one embodiment of this disclosure, the first direction being substantially perpendicular to the third direction means that the first included angle is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees, and that the first included angle is not equal to 90 degrees;

[0076] The first direction intersects with the third direction, and the first direction is not perpendicular to the third direction. The first direction not being approximately perpendicular to the third direction can mean that the first included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0077] The second direction being approximately perpendicular to the third direction means that the second included angle is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees, and that the second included angle is not equal to 90 degrees;

[0078] The second direction intersects with the third direction. The second direction is not perpendicular to the third direction. The second direction not being approximately perpendicular to the third direction can mean that the second included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0079] However, this is not the limit.

[0080] In specific implementation, the first data line and the second data line can be vertically extending data lines, and the first lead portion and the second lead portion can be oblique lead portions. At least one embodiment of this disclosure sets the line width of the first lead portion coupled to the first data line located in the central display area to be smaller than the line width of the second lead portion coupled to the second data lines located in the display areas on both sides, so as to improve the poor display uniformity caused by the large difference in line resistance between the data signal leads. This makes the line width of the second lead portion larger, which makes the resistance value of the second data signal lead smaller, and makes the line width of the first lead portion smaller, which makes the resistance value of the first data signal lead larger. This reduces the difference in line resistance between the data signal leads, improves the color shift phenomenon, enhances display uniformity, and ensures low grayscale display uniformity.

[0081] In related technologies, the line resistance of signal lines used to transmit data voltages is a crucial factor affecting the uniformity of low grayscale. The smaller the difference in line resistance between signal lines transmitting data voltages, the closer the written data voltages are, and consequently, the closer the luminous current of the light-emitting elements are, resulting in better low grayscale uniformity. In this embodiment, by setting the line width of each obliquely positioned lead portion, the difference in line resistance between each data signal lead can be reduced. By using the display substrate described in this embodiment, Rmax / Rmin can be reduced to below 2.0, where Rmax is the maximum resistance value among all data signal leads, and Rmin is the minimum resistance value among all data signal leads.

[0082] In at least one embodiment of this disclosure, the first side can be the bottom side, the second side can be the left side, and the third side can be the right side, but is not limited thereto.

[0083] like Figure 1 As shown, the display substrate of at least one embodiment of the present disclosure includes a display area A1 and a border area A0 disposed on the lower side of the display area A1;

[0084] The display area A1 includes a central display area A2, a first display area A11 disposed to the left of the central display area A2, and a second display area A12 disposed to the right of the central display area A2;

[0085] like Figure 2 As shown, the display substrate includes multiple first data lines disposed in the central display area A2, multiple second data lines disposed in the first display area A11 and the second display area A12, and multiple first data signal leads and multiple second data signal leads disposed in the border area A0;

[0086] exist Figure 2In the diagram, the second data line in the first column of the first display area A11 is labeled D21, the second data line in the second column of the first display area A11 is labeled D22, and the second data line in the third column of the first display area A11 is labeled D23.

[0087] The second data line labeled D2n-2 is located in the (n-2)th column of the first display area A11; the second data line labeled D2n-1 is located in the (n-1)th column of the first display area A11; and the second data line labeled D2n is located in the nth column of the first display area A11; n is a positive integer and is greater than 5.

[0088] The first data line in the first column of the central display area A2 is labeled D11; the first data line in the second column of the central display area A2 is labeled D12; and the first data line in the third column of the central display area A2 is labeled D13.

[0089] The first data line in the mth column of the central display area A2 is labeled D1m, and the first data line in the (m+1)th column of the central display area A2 is labeled D1m+1, where m is a positive integer and m is greater than 3.

[0090] The data line labeled D1a-2 is the first data line in the (a-2)th column of the central display area A2; the data line labeled D1a-1 is the first data line in the (a-1)th column of the central display area A2; and the data line labeled D1a is the first data line in the (a)th column of the central display area A2; where 'a' is a positive integer and a-2 is greater than m+1. The data line labeled D2b-2 is the second data line in the (b-2)th column of the second display area A12; the data line labeled D2b-1 is the second data line in the (b-1)th column of the second display area A12; and the data line labeled D2b is the second data line in the (b)th column of the second display area A12; where 'b' is a positive integer and b-2 equals n+1.

[0091] The second data line in column c-2 of the second display area A12 is labeled D2c-2; the second data line in column c-1 of the second display area A12 is labeled D2c; and the second data line in column c of the second display area A12 is labeled D2c. c is a positive integer and is greater than b+2.

[0092] exist Figure 2 In the first display area A11 and the second display area A12, there are multiple columns of second data lines, and each column of second data lines is numbered from left to right;

[0093] The second data line D2n in column n is the rightmost second data line in the first display area A11, the second data line D2b-2 in column b-2 is the leftmost second data line in the second display area A12, and the second data line D2b-2 in column b-2 is the second data line in column n+1. That is, b-2 equals n+1.

[0094] The second data line D2c-2 in column c-2 is located to the right of the second data line D2b in column b. Therefore, c-2 is greater than b, and c is greater than b+2.

[0095] like Figure 2 As shown, in at least one embodiment of this disclosure, the third direction can be the vertical direction, but is not limited thereto.

[0096] exist Figure 3 In the diagram, F1 is the first fan-out area, B1 is the bending area, F2 is the second fan-out area, E1 is the electrostatic protection area, C1 is the cell assembly testing area, F3 is the third fan-out area, S1 is the chip mounting area for setting source drivers, and F0 is the area for setting FPC (flexible printed circuit board).

[0097] Figure 4 This diagram illustrates a structure of multiple data signal leads disposed in a border region, according to at least one embodiment of this disclosure. Figure 4 In at least one embodiment shown, the source driver is disposed in the chip mounting area S1.

[0098] like Figure 5 As shown, in Figure 4 Based on this, each data signal lead was labeled.

[0099] exist Figure 5 In the diagram, L11 is the first first data signal lead, L12 is the second first data signal lead, and L13 is the third first data signal lead.

[0100] The line labeled L1m is the m-th first data signal lead, and the line labeled L1m+1 is the (m+1)-th first data signal lead.

[0101] The lead labeled L1a-2 is the (a-2)th first data signal lead, the lead labeled L1a-1 is the (a-1)th first data signal lead, and the lead labeled L1a is the ath first data signal lead.

[0102] The lead labeled L2b-2 is the (b-2)th second data signal lead, the lead labeled L2b-1 is the (b-1)th second data signal lead, and the lead labeled L2b is the bth second data signal lead.

[0103] The lead labeled L2c-2 is the (c-2)th second data signal lead, the lead labeled L2c-1 is the (c-1)th second data signal lead, and the lead labeled L2c is the cth second data signal lead.

[0104] like Figure 5 As shown, each data signal lead includes a lead portion disposed in the first fan-out area F1, a lead portion disposed in the bending area B1, a lead portion disposed in the second fan-out area F2, a lead portion disposed in the electrostatic protection area E1, a lead portion disposed in the package testing area C1, and a lead portion disposed in the third fan-out area F3.

[0105] In at least one embodiment of this disclosure, L21 is coupled to D21, L22 is coupled to D22, L23 is coupled to D23, L2n-2 is coupled to D2n-2, L2n-1 is coupled to D2n-1, L2n is coupled to D2n, L11 is coupled to D11, L12 is coupled to D12, L13 is coupled to D13, L1m is coupled to D1m, L1m+1 is coupled to D1m+1, L1a-2 is coupled to D1a-2, L1a-1 is coupled to D1a-1, L1a is coupled to D1a, L2b-2 is coupled to D2b-2, L2b-1 is coupled to D2b-1, L2b is coupled to D2b, L2c-2 is coupled to D2c-2, L2c-1 is coupled to D2c-1, and L2c is coupled to D2c.

[0106] In at least one embodiment of this disclosure, the display substrate may include a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer. The first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer may be stacked along a direction away from the substrate. Each data line may be disposed in at least one of the first source / drain metal layer and the second source / drain metal layer. In the first fan-out region, each data signal lead may be disposed in the first gate metal layer or the second gate metal layer. Each data signal lead may be coupled to the corresponding data line through a transition portion disposed in the first source / drain metal layer or the second source / drain metal layer.

[0107] In at least one embodiment of this disclosure, the display substrate may include a first gate metal layer, a second gate metal layer, a first source / drain metal layer, a second source / drain metal layer, and an additional source / drain metal layer;

[0108] Each of the data lines can be disposed in at least one of the first source-drain metal layer, the second source-drain metal layer, and the additional source-drain metal layer. In the first fan-out region, each data signal lead can be disposed in the first gate metal layer or the second gate metal layer. Each data signal lead can be coupled to the corresponding data line through the adapter disposed in the first source-drain metal layer, the second source-drain metal layer, or the additional source-drain metal layer.

[0109] Optionally, on the side of the second gate metal layer facing away from the substrate, the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer are sequentially stacked in a direction away from the substrate; or, on the side of the second gate metal layer facing away from the substrate, the additional source / drain metal layer, the first source / drain metal layer, and the second source / drain metal layer are sequentially stacked in a direction away from the substrate; or, the substrate includes a first substrate and a second substrate stacked together, the additional source / drain metal layer is disposed between the first substrate and the second substrate, and on the side of the second gate metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are sequentially stacked.

[0110] In at least one embodiment of this disclosure, a three-layer source-drain metal layer can be used for wiring, which can achieve a higher PPI (Pixels Per Inch) and narrower bezels.

[0111] Optionally, the first substrate and the second substrate can be flexible substrates, and the first substrate and the second substrate can be made of PI (Polyimide), but are not limited thereto.

[0112] Figure 6 It shows Figure 5 L2n-2 includes the portion disposed in the first fan-out region F1, L2n-1 includes the portion disposed in the first fan-out region F1, and L2n includes the portion disposed in the first fan-out region F1.

[0113] exist Figure 6 In the diagram, L41 is the first second lead section, L42 is the second second lead section, and L43 is the third second lead section.

[0114] L41, L42 and L43 extend along the first second direction X12;

[0115] exist Figure 6 In the diagram, K41 represents the line width of L41, K42 represents the line width of L42, K43 represents the line width of L43, J1 represents the spacing between L41 and L42, and J2 represents the spacing between L42 and L43.

[0116] exist Figure 6 In the middle, the first second direction X12 intersects the vertical direction, the first second direction X12 is not perpendicular to the vertical direction, and the first second direction X12 is not approximately perpendicular to the vertical direction.

[0117] exist Figure 6In at least one embodiment shown, the angle between the first second direction X12 and the vertical direction is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0118] In at least one embodiment of this disclosure, the spacing between L41 and L42 can be the shortest distance between L41 and L42, and the spacing between L42 and L43 can be the shortest distance between L42 and L43.

[0119] In at least one embodiment of this disclosure, K41, K42 and K43 may all be 2.2um, and J1 and J2 may all be 0.5um, but are not limited thereto.

[0120] exist Figure 6 In the diagram, the first sixth lead is labeled L91, the second sixth lead is labeled L92, and the third sixth lead is labeled L93. L91 is coupled to L41, L92 is coupled to L42, and L93 is coupled to L43.

[0121] L91, L92 and L93 can all extend along a third direction.

[0122] exist Figure 6 In at least one embodiment shown, the third direction is the vertical direction, the line width of L91, the line width of L92, and the line width of L93 can be greater than or equal to 2.6 μm and less than or equal to 3.2 μm, the shortest distance between L91 and L92, and the shortest distance between L92 and L93 can be greater than or equal to 9 μm and less than or equal to 30 μm, but are not limited thereto.

[0123] Figure 7 It shows Figure 5 L11 includes the portion disposed in the first fan-out region F1, L12 includes the portion disposed in the first fan-out region F1, and L13 includes the portion disposed in the first fan-out region F1.

[0124] exist Figure 7 In the diagram, L31 is the first lead section, L32 is the second lead section, and L33 is the third lead section.

[0125] L31, L32 and L33 extend along the first first direction X11;

[0126] exist Figure 7 In the diagram, K31 represents the line width of L31, K32 represents the line width of L32, K33 represents the line width of L33, J3 represents the spacing between L31 and L32, and J4 represents the spacing between L32 and L33.

[0127] exist Figure 7 In the first direction X11, the first direction X11 intersects the vertical direction; the first direction X11 is not perpendicular to the vertical direction; the first direction X11 is not approximately perpendicular to the vertical direction.

[0128] exist Figure 7 In at least one embodiment shown, the angle between the first first direction X11 and the vertical direction is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0129] In at least one embodiment of this disclosure, the distance between L31 and L32 can be the shortest distance between L31 and L32, and the distance between L32 and L33 can be the shortest distance between L42 and L43.

[0130] In at least one embodiment of this disclosure, K31, K32 and K33 can all be 1.8 μm, and J3 and J4 can all be 0.9 μm.

[0131] like Figure 6 and Figure 7 As shown, the line width of each first lead is smaller than the line width of each second lead to increase the resistance value of the first data signal lead and decrease the resistance value of the second data signal lead, thereby reducing the difference in line resistance between the data signal leads and improving display uniformity.

[0132] Figure 8 It shows Figure 5 L2n-2 includes the portion disposed in the second fan-out region F2, L2n-1 includes the portion disposed in the second fan-out region F2, and L2n includes the portion disposed in the second fan-out region F2.

[0133] exist Figure 8 In the diagram, L44 is the fourth second lead section, L45 is the fifth second lead section, and L46 is the sixth second lead section.

[0134] L44, L45 and L46 extend along the second second direction X22;

[0135] exist Figure 8 In the diagram, K44 represents the line width of L44, K45 represents the line width of L45, K46 represents the line width of L46, J5 represents the spacing between L44 and L45, and J6 represents the spacing between L45 and L46.

[0136] exist Figure 8 In the middle, the second second direction X22 intersects the vertical direction, the second second direction X22 is not perpendicular to the vertical direction, and the second second direction X22 is not approximately perpendicular to the vertical direction.

[0137] exist Figure 8 In at least one embodiment shown, the angle between the second direction X22 and the vertical direction is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees. In at least one embodiment of this disclosure, the distance between L44 and L45 can be the shortest distance between L44 and L45, and the distance between L45 and L46 can be the shortest distance between L45 and L46.

[0138] In at least one embodiment of this disclosure, K44, K45 and K46 may all be 2.3 μm, and J5 and J6 may all be 0.5 μm, but are not limited thereto.

[0139] Figure 9 It shows Figure 5 L11 includes the portion disposed in the second fan-out region F2, L12 includes the portion disposed in the second fan-out region F2, and L13 includes the portion disposed in the second fan-out region F1.

[0140] exist Figure 9 In the diagram, L34 is the fourth first lead section, L35 is the fifth first lead section, and L36 is the sixth first lead section.

[0141] L34, L35 and L36 extend along the second first direction X21;

[0142] exist Figure 9 In the diagram, K34 represents the line width of L34, K35 represents the line width of L35, K36 represents the line width of L36, J7 represents the spacing between L34 and L35, and J8 represents the spacing between L35 and L36.

[0143] exist Figure 9 In the middle, the second first direction X21 intersects the vertical direction, the second first direction X21 is not perpendicular to the vertical direction, and the second first direction X21 is not approximately perpendicular to the vertical direction.

[0144] exist Figure 9 In at least one embodiment shown, the angle between the second first direction X21 and the vertical direction is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

[0145] In at least one embodiment of this disclosure, the spacing between L34 and L35 can be the shortest distance between L34 and L35, and the spacing between L35 and L36 can be the shortest distance between L45 and L46.

[0146] In at least one embodiment of this disclosure, K34, K35 and K36 may all be 1.8 μm, and J7 and J8 may all be 1.0 μm.

[0147] like Figure 8 and Figure 9 As shown, the line width of each first lead is smaller than the line width of each second lead to increase the resistance value of the first data signal lead and decrease the resistance value of the second data signal lead, thereby reducing the difference in line resistance between the data signal leads and improving display uniformity.

[0148] Optionally, the line width of the first lead portion can be greater than or equal to 1.0 μm and less than or equal to 2.0 μm, and the line width of the second lead portion can be greater than or equal to 1.5 μm and less than or equal to 3.0 μm.

[0149] In at least one embodiment of this disclosure, the second data signal lead further includes a third lead portion extending along a fourth direction, wherein the fourth direction and the third direction have a third included angle; the third included angle is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees.

[0150] The line width of the third lead is greater than that of the second lead.

[0151] In at least one embodiment of this disclosure, the fourth direction is perpendicular or substantially perpendicular to the third direction;

[0152] The statement that the fourth direction is approximately perpendicular to the third direction can mean that the angle between the fourth direction and the third direction is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees, and that the angle between the fourth direction and the third direction is not equal to 90 degrees; however, it is not limited to this.

[0153] In a specific implementation, the second data signal lead may include a third lead portion extending along a fourth direction. The line width of the third lead portion may be greater than the line width of the second lead portion, so as to further reduce the resistance value of the second data signal lead.

[0154] Figure 10 It shows Figure 5 L21 includes the portion disposed in the second fan-out region F2, L22 includes the portion disposed in the second fan-out region F2, and L23 includes the portion disposed in the second fan-out region F2.

[0155] exist Figure 10 In the diagram, L51 is the first third lead section, L52 is the second third lead section, and L53 is the third third lead section.

[0156] The extension directions of L51, L52, and L53 are the fourth direction X4.

[0157] exist Figure 10In at least one embodiment shown, the fourth direction X4 is a horizontal direction and is perpendicular to the third direction.

[0158] like Figure 10 As shown, K51 represents the line width of L51, K52 represents the line width of L52, K53 represents the line width of L53, J9 represents the spacing between L51 and L52, and J10 represents the spacing between L52 and L53.

[0159] In at least one embodiment of this disclosure, the spacing between L51 and L52 can be the shortest distance between L51 and L52, and the spacing between L52 and L53 can be the shortest distance between L52 and L53.

[0160] exist Figure 10 In at least one embodiment shown, K51, K52 and K53 may be equal to 2.7 μm, and J9 and J10 may be equal to 2 μm, but are not limited thereto.

[0161] In at least one embodiment of this disclosure, the linewidth of the third lead portion is greater than or equal to 1.8 μm and less than or equal to 4.0 μm, but is not limited thereto.

[0162] In at least one embodiment of this disclosure, the second data signal lead includes a fourth lead portion extending in a third direction;

[0163] The line width of the fourth lead is greater than the line width of the second lead.

[0164] In practical implementation, the resistance value of the second data signal lead can be further compensated by setting the line width of the portion of the lead extending in the third direction, which is included in the second data signal lead, to further reduce the resistance value of the second data signal lead.

[0165] Figure 11 It shows Figure 5 L21 includes the portion disposed in the second fan-out region F2, L22 includes the portion disposed in the second fan-out region F2, and L23 includes the portion disposed in the second fan-out region F2.

[0166] exist Figure 11 In the diagram, L61 is the first fourth lead section, L62 is the second fourth lead section, L63 is the third fourth lead section; L64 is the fourth fourth lead section, L65 is the fifth fourth lead section, and L66 is the sixth fourth lead section.

[0167] The first fourth lead section L61, the second fourth lead section L62, the third fourth lead section L63, the fourth fourth lead section L64, the fifth fourth lead section L65, and the sixth fourth lead section L66 all extend in a vertical direction.

[0168] like Figure 11 As shown, the closer to the sides, the longer the fourth lead portion of each second data signal lead is, in order to reduce the resistance value of the second data signal lead.

[0169] exist Figure 11 In at least one corresponding embodiment, the line widths K61 of L61, K62 of L62, K63 of L63, K64 of L64, K65 of L65, and K66 of L66 can be greater than or equal to 3 μm and less than or equal to 13 μm, and the shortest distance between each fourth lead portion can be greater than or equal to 0.8 μm and less than or equal to 1.5 μm, but are not limited thereto.

[0170] In at least one embodiment of this disclosure, the border region includes a first fan-out region and a second fan-out region arranged along a direction away from the display region;

[0171] The line width of the second lead portion in the first fan-out region is smaller than the line width of the second lead portion in the second fan-out region.

[0172] like Figure 6 and Figure 8 As shown, when the longitudinal length of the second fan-out region is greater than the longitudinal length of the first fan-out region, the line width of the second lead in the first fan-out region can be less than the line width of the second lead in the second fan-out region.

[0173] In at least one embodiment of this disclosure, the border region includes a first fan-out region and a second fan-out region arranged along a direction away from the display region; the first data signal lead includes a serpentine lead portion;

[0174] The serpentine lead portion includes a plurality of first lead portions extending along a third direction, and a plurality of second lead portions extending along a fifth direction; the first lead portions and the second lead portions are alternately arranged, and adjacent first lead portions and second lead portions are coupled to each other.

[0175] The fifth direction and the third direction have a fourth included angle, which is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees.

[0176] In at least one embodiment of this disclosure, the fifth direction is perpendicular or substantially perpendicular to the third direction;

[0177] The statement that the fifth direction is approximately perpendicular to the third direction can mean that the angle between the fifth direction and the third direction is greater than or equal to 89.5 degrees and less than or equal to 90.5 degrees, and that the angle between the fifth direction and the third direction is not equal to 90 degrees; however, it is not limited to this.

[0178] In a specific implementation, the length of the first data signal lead can be increased by including a serpentine lead portion, thereby further increasing the resistance value of the first data signal lead for resistance compensation.

[0179] Figure 12 It shows Figure 5 L11 includes the portion located in the first fan-out region F1. Figure 5 L12 includes the portion located in the first fan-out region F1. Figure 5 L13 in the text includes a portion of the first fan-out region F1;

[0180] like Figure 5 and Figure 12 As shown, L11 includes a first serpentine lead portion L71, L12 includes a second serpentine lead portion L72, and L13 includes a third serpentine lead portion L73.

[0181] like Figure 12 As shown, the shortest distance J11 between L71 and L72, and the shortest distance J12 between L72 and L73 can be greater than or equal to 1.2um and less than or equal to 2um. For example, J11 and J12 can be equal to 1.5um, but are not limited to this.

[0182] Figure 13 yes Figure 12 The diagram shows the structure of the third serpentine lead section L73, where L81 is the first first lead section, L82 is the first second lead section, L83 is the second first lead section, and L84 is the second second lead section.

[0183] L81 extends vertically, and L82 extends along the fifth direction X5. L81 and L82 are coupled together.

[0184] exist Figure 13 In at least one embodiment shown, the fifth direction X5 can be a horizontal direction, the third direction can be a vertical direction, and the fifth direction is perpendicular to the third direction.

[0185] like Figure 13 As shown, the third serpentine lead portion L73 includes a plurality of first lead portions extending in the vertical direction and a plurality of second lead portions extending in the direction, with adjacent first lead portions and second lead portions coupled to each other.

[0186] like Figure 13 As shown, the shortest distance between the first second lead portion L82 and the second second lead portion L84 included in L73 can be 2.7um, but is not limited to this.

[0187] like Figure 5 As shown, in both the first and second fan-out regions, the first data signal lead can include a serpentine lead portion, and the closer to the center, the longer the serpentine lead portion becomes, in order to increase the resistance value of the first data signal lead.

[0188] In at least one embodiment of this disclosure, the line width of the first lead portion and the line width of the second lead portion included in the same serpentine lead portion may be equal, but are not limited thereto;

[0189] The linewidth of the first lead portion and the linewidth of the second lead portion can both be greater than or equal to 1.8um and less than or equal to 2.4um, but are not limited thereto.

[0190] Optionally, the shortest distance between two adjacent second lead portions included in the same serpentine lead portion can be greater than or equal to 2.4 μm and less than or equal to 3 μm; the shortest distance between two adjacent serpentine lead portions can be greater than or equal to 1.0 μm and less than or equal to 2 μm.

[0191] In at least one embodiment of this disclosure, the border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; in the first fan-out area, the sum of the line width of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the line width of the second lead portion and the shortest distance between two adjacent second lead portions.

[0192] In the second fan-out region, the sum of the linewidth of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the linewidth of the second lead portion and the shortest distance between two adjacent second lead portions.

[0193] In practical implementation, for ease of layout, in the first fan-out area, the sum of the line width of the first lead portion and the shortest distance between two adjacent first lead portions is set to be equal to the sum of the line width of the second lead portion and the shortest distance between two adjacent second lead portions. Similarly, in the second fan-out area, the sum of the line width of the first lead portion and the shortest distance between two adjacent first lead portions is set to be equal to the sum of the line width of the second lead portion and the shortest distance between two adjacent second lead portions.

[0194] like Figure 6As shown, in the first fan-out region, the linewidth of each second lead portion can be 2.2 μm, and the shortest distance between any two adjacent second lead portions can be 0.5 μm; Figure 7 As shown, in the first fan-out region, the linewidth of each first lead portion can be 1.8 μm, and the shortest distance between two adjacent first lead portions can be 0.9 μm; that is, in the first fan-out region, the sum of the linewidth of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the linewidth of the second lead portion and the shortest distance between two adjacent second lead portions.

[0195] like Figure 8 As shown, in the second fan-out region, the linewidth of each second lead portion can be 2.3 μm, and the shortest distance between two adjacent second lead portions can be 0.5 μm; Figure 9 As shown, in the second fan-out region, the linewidth of each first lead portion can be 1.8 μm, and the shortest distance between two adjacent first lead portions can be 1 μm; that is, in the second fan-out region, the sum of the linewidth of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the linewidth of the second lead portion and the shortest distance between two adjacent second lead portions.

[0196] Optionally, the shortest distance between two adjacent first lead portions is greater than or equal to 1.0 μm and less than or equal to 2.0 μm;

[0197] The shortest distance between two adjacent second lead portions is greater than or equal to 0.5 μm and less than or equal to 1.0 μm;

[0198] However, this is not the limit.

[0199] By setting the data signal leads in the border area as follows Figure 5 As shown, Rmax can be set to 9.3 kΩ, Rmin to 7.1 kΩ, Rmax / Rmin to 1.3, and the current value I1 of the outermost data signal lead can be set to 2.26kΩ. -11 Naan, set the current value I2 of the center-side data signal lead to 2.325e. -11 The current difference between the outermost and center data signal leads is reduced to 2.75%, significantly reducing the line resistance difference between the data signal leads and meeting the low grayscale uniformity requirement as much as possible.

[0200] In at least one embodiment of this disclosure, the border region includes a fan-out region, the fan-out region including a first fan-out region and a second fan-out region arranged along a direction away from the display region;

[0201] The display substrate includes a substrate, and a first metal layer and a second metal layer stacked along a direction away from the substrate.

[0202] The first data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer;

[0203] The second data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer;

[0204] The adjacent data signal leads, including the lead portions disposed in the fan-out region, are contained in different layers.

[0205] In specific implementation, in the first fan-out area and the second fan-out area, each data signal lead can be set on the first metal layer or the second metal layer, and two adjacent data signal leads can be set on different layers to increase the distance between two adjacent data signal leads on the same layer and reduce signal interference between two adjacent data signal leads on the same layer.

[0206] In at least one embodiment of this disclosure, portions of the same data signal lead located in the first fan-out region and the second fan-out region are disposed on the same layer.

[0207] In at least one embodiment of this disclosure, the first metal layer may be a first gate metal layer and the second metal layer may be a second gate metal layer, but is not limited thereto.

[0208] In at least one embodiment of this disclosure, since the high voltage line and the low voltage line inevitably overlap with the data signal lead in the fan-out region, the data signal lead cannot be located on the same layer as the high voltage line and the low voltage line. Since the high voltage line and the low voltage line are disposed on the source and drain metal layers, the data signal lead is disposed on the first gate metal layer or the second gate metal layer in the fan-out region.

[0209] like Figure 5As shown, L21 includes the portion disposed in the first fan-out area, L21 includes the portion disposed in the second fan-out area, L23 includes the portion disposed in the first fan-out area, L21 includes the portion disposed in the second fan-out area, L2n-2 includes the portion disposed in the first fan-out area, L2n-2 includes the portion disposed in the second fan-out area, L2n includes the portion disposed in the first fan-out area, L2n includes the portion disposed in the second fan-out area, L12 includes the portion disposed in the first fan-out area, L12 includes the portion disposed in the second fan-out area, L1m includes the portion disposed in the first fan-out area, and L1m includes the portion disposed in the second fan-out area. The portion of the second fan-out region, the portion of L1a-1 included in the first fan-out region, the portion of L1a-1 included in the second fan-out region, the portion of L2b-2 included in the first fan-out region, the portion of L2b-2 included in the second fan-out region, the portion of L2b included in the first fan-out region, the portion of L2b included in the second fan-out region, the portion of L2c-2 included in the first fan-out region, the portion of L2c-2 included in the second fan-out region, the portion of L2c included in the first fan-out region, and the portion of L2c included in the second fan-out region are all disposed in the first gate metal layer.

[0210] L22 includes the portion disposed in the first fan-out region, L22 includes the portion disposed in the second fan-out region, L2n-1 includes the portion disposed in the first fan-out region, L2n-1 includes the portion disposed in the second fan-out region, L11 includes the portion disposed in the first fan-out region, L11 includes the portion disposed in the second fan-out region, L13 includes the portion disposed in the first fan-out region, L13 includes the portion disposed in the second fan-out region, L1m+1 includes the portion disposed in the first fan-out region, and L1m+1 includes the portion disposed in the second fan-out region. The portion of the second fan-out region, the portion of L1a-2 included in the first fan-out region, the portion of L1a-2 included in the second fan-out region, the portion of L1a included in the first fan-out region, the portion of L1a included in the second fan-out region, the portion of L2b-1 included in the first fan-out region, the portion of L2b-1 included in the second fan-out region, the portion of L2c-1 included in the first fan-out region, and the portion of L2c-1 included in the second fan-out region can all be disposed in the second gate metal layer.

[0211] In at least one embodiment of this disclosure, the border region further includes a bent region disposed between the first fan-out region and the second fan-out region, and the display substrate further includes a source / drain metal layer disposed on the side of the second gate metal layer away from the first gate metal layer;

[0212] The data signal lead further includes a fifth lead portion disposed in the bending region; the fifth lead portion is contained in the source / drain metal layer.

[0213] Optionally, the source / drain metal layer includes a first source / drain metal layer and a second source / drain metal layer; on the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are sequentially stacked in a direction away from the substrate.

[0214] The fifth lead portion is included in at least one of the first source / drain metal layer and the second source / drain metal layer.

[0215] In at least one embodiment of this disclosure, the fifth lead portion may extend in a third direction, but is not limited thereto.

[0216] In at least one embodiment of this disclosure, an active layer, a first gate metal layer, a second gate metal layer, an interlayer dielectric layer, a first source / drain metal layer, a first planarization layer, a second source / drain metal layer, and a second planarization layer may be sequentially disposed on a substrate. In the bending region, the interlayer dielectric layer (which may be an inorganic layer) needs to be removed. If the data signal lead is disposed on the first gate metal layer or the second gate metal layer in the bending region, it will affect the flatness of the gate metal layer and may even cause the gate metal layer to break in severe cases. Therefore, in at least one embodiment of this disclosure, the data signal lead is disposed on at least one of the first source / drain metal layer and the second source / drain metal layer in the bending region.

[0217] like Figure 5 As shown, the fifth lead portion of each data signal lead, which is located in the bending region, is located in the second source / drain metal layer.

[0218] In at least one embodiment of this disclosure, the display substrate may include a first source / drain metal layer, a second source / drain metal layer, and an additional source / drain metal layer; the fifth lead portion may be included in at least one of the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer;

[0219] On the side of the second metal layer facing away from the substrate, the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer are sequentially stacked in a direction away from the substrate; or, on the side of the second metal layer facing away from the substrate, the additional source / drain metal layer, the first source / drain metal layer, and the second source / drain metal layer are sequentially stacked in a direction away from the substrate; or, the substrate includes a first substrate and a second substrate stacked together, the additional source / drain metal layer is disposed between the first substrate and the second substrate, and on the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are sequentially stacked.

[0220] In specific implementations, when the display substrate includes only one source / drain metal layer, the data signal lead may be contained within the source / drain metal layer in the bending region; when the display substrate includes two source / drain metal layers, the data signal lead may be contained within at least one of the first source / drain metal layer and the second source / drain metal layer in the bending region; when the display substrate includes a first source / drain metal layer, a second source / drain metal layer, and an additional source / drain metal layer, the data signal lead may be contained within at least one of the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer in the bending region.

[0221] Figure 14 It shows Figure 5 The data signal leads in the diagram include the portion located in the bending area B1;

[0222] exist Figure 14 In the diagram, L81 is the first fifth lead section, L82 is the second fifth lead section, and L83 is the third fifth lead section.

[0223] The first fifth lead portion L81 is the portion of L11 that is disposed in the bending area B1; the second fifth lead portion L82 is the portion of L12 that is disposed in the bending area B1; and the third fifth lead portion L83 is the portion of L13 that is disposed in the bending area B1.

[0224] L81, L82 and L83 are all located in the second source / drain metal layer, and L81, L82 and L83 all extend in the vertical direction.

[0225] In at least one embodiment of this disclosure, the linewidth of each fifth lead portion can be greater than or equal to 7 μm and less than or equal to 10 μm, and the shortest distance between two adjacent fifth lead portions can be greater than or equal to 8 μm and less than or equal to 13 μm.

[0226] In at least one embodiment of this disclosure, the fan-out region further includes a third fan-out region, and the border region further includes an electrostatic protection region and a box-in testing region;

[0227] The second fan-out area, the electrostatic protection area, the cell assembly test area, and the third fan-out area are arranged sequentially along a direction away from the display area;

[0228] The lead portion of the first data signal lead located in the electrostatic protection area and the box test area is disposed in the same layer as the lead portion of the first data signal lead located in the fan-out area.

[0229] The second data signal lead includes a lead portion disposed in the electrostatic protection area and the box test area, which is disposed in the same layer as the lead portion disposed in the fan-out area.

[0230] In specific implementation, the portions of the first data signal lead located in the first fan-out area, the second fan-out area, the third fan-out area, the electrostatic protection area, and the box test area can be located on the same layer, and the portions of the second data signal lead located in the first fan-out area, the second fan-out area, the third fan-out area, the electrostatic protection area, and the box test area can be located on the same layer to facilitate wiring.

[0231] exist Figure 5 In at least one embodiment shown, in the test cell area C1, the linewidth of each data signal lead can be greater than or equal to 3 μm and less than or equal to 4 μm, the horizontal distance between two adjacent data signal leads can be greater than or equal to 3 μm and less than or equal to 4 μm, or the horizontal distance between two adjacent data signal leads can be greater than or equal to 18 μm and less than or equal to 27 μm, but is not limited thereto.

[0232] Figure 15 It shows Figure 5 The data signal leads in the package include the portions located in the electrostatic discharge protection area E1 and the box test area C1;

[0233] exist Figure 15 In the diagram, L101 is the first seventh lead section, L102 is the second seventh lead section, and L103 is the third seventh lead section.

[0234] L101 is the portion of L11 that is disposed in the box-forming test area C1, L102 is the portion of L12 that is disposed in the box-forming test area C1, and L103 is the portion of L13 that is disposed in the box-forming test area C1.

[0235] L101, L102 and L103 can all extend in the vertical direction.

[0236] like Figure 15 As shown, the distance between L101 and L102 along the horizontal direction is labeled J01. J01 can be greater than or equal to 3um and less than or equal to 4um.

[0237] The distance between L102 and L103 in the horizontal direction is designated as J02. J02 can be greater than or equal to 18 μm and less than or equal to 27 μm.

[0238] However, this is not the limit.

[0239] exist Figure 5In at least one of the embodiments shown, in the third fan-out region F3, the linewidth of each of the data signal leads can be greater than or equal to 3 μm and less than or equal to 5 μm.

[0240] In at least one embodiment of this disclosure, in the third fan-out region, each data signal lead may include an eighth lead portion extending along a third direction, and the horizontal distance between two adjacent eighth lead portions may be greater than or equal to 10 μm and less than or equal to 20 μm, but is not limited thereto.

[0241] Figure 16 It shows Figure 5 L11 includes the portion located in the third fan-out region F3. Figure 5 L12 includes the portion located in the third fan-out region F3. Figure 5 L13 includes the portion located in the third fan-out region F3;

[0242] like Figure 16 As shown, in the third fan-out region, L11 includes a first eighth lead portion L111 extending in the vertical direction, L12 includes a second eighth lead portion L112 extending in the vertical direction, and L13 includes a third eighth lead portion L113 extending in the vertical direction.

[0243] In at least one embodiment of this disclosure, since the portion of each data signal lead located in the first fan-out region F1 is disposed in the first gate metal layer or the second gate metal layer, and the portion of each data signal lead located in the bending region B1 is disposed in the second source-drain metal layer, the portion of each data signal lead located in the first fan-out region F1 is coupled to the portion of the data signal lead located in the bending region through a corresponding first adapter; the first adapter is contained in the second source-drain metal layer.

[0244] like Figure 17 As shown, the portion of L21 located in the first fan-out region F1 is coupled to the first adapter Z1 through a corresponding first through hole H1, and the first adapter Z1 is coupled to the portion of L21 located in the bending region B1.

[0245] As in at least one embodiment of this disclosure, since the portion of each data signal lead located in the bending region B1 is disposed in the second source-drain metal layer, and the portion of each data signal lead located in the second fan-out region F2 is disposed in the first gate metal layer or the second gate metal layer, the portion of each data signal lead located in the second fan-out region F2 is coupled to the portion of the data signal lead located in the bending region through the second adapter; the second adapter is contained in the second source-drain metal layer.

[0246] like Figure 18As shown, the portion of L21 located in the second fan-out region F1 is coupled to the second adapter Z2 through a corresponding second via H2, and the second adapter Z2 is coupled to the portion of L21 located in the bending region B1.

[0247] In at least one embodiment of this disclosure, since no second gate metal layer is provided in the chip mounting area S1, in the third fan-out area F1, the portion of the data signal lead disposed in the second gate metal layer is coupled to the third adapter portion. The third adapter portion may be included in the first gate metal layer. The portion of the data signal lead disposed in the second gate metal layer is coupled to the pin of the source driver disposed in the chip mounting area S1 through the third adapter portion.

[0248] like Figure 19 As shown, the portion of L22 located in the chip mounting area S1 is coupled to the third adapter Z3 through a corresponding third via H3, and the third adapter Z3 is contained in the first gate metal layer.

[0249] The display device described in this disclosure includes the display substrate described above.

[0250] In at least one embodiment of this disclosure, the border area of ​​the display substrate may include a first fan-out area, a bent area, a second fan-out area, a third fan-out area, and a chip mounting area arranged in a direction away from the display area, and the display device includes a source driver mounted in the chip mounting area;

[0251] The source driver is used to provide data voltage and to provide the data voltage to the data line through the data signal lead.

[0252] In at least one embodiment of this disclosure, the display device may be a foldable display screen, but is not limited thereto.

[0253] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0254] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display substrate, wherein, It includes a display area and a border area disposed on a first side of the display area; The display area includes a central display area, a first display area disposed on a second side of the central display area, and a second display area disposed on a third side of the central display area; the second side and the third side are opposite sides. The display substrate includes multiple first data lines disposed in the central display area, multiple second data lines disposed in the first display area and the second display area, and multiple first data signal leads and multiple second data signal leads disposed in the border area; the first data signal leads are coupled to the first data lines, and the second data signal leads are coupled to the second data lines. The first data signal lead includes a first lead portion extending along a first direction, and the second data signal lead includes a second lead portion extending along a second direction; The line width of the first lead portion is smaller than the line width of the second lead portion; The extension direction of the first data line and the extension direction of the second data line are in a third direction, the first direction intersects the third direction, and the second direction intersects the third direction; The first direction and the third direction have a first angle, and the second direction and the third direction have a second angle; The second data signal lead also includes a third lead portion extending in a fourth direction; the line width of the third lead portion is greater than the line width of the second lead portion; The second data signal lead includes a fourth lead portion extending in a third direction; the line width of the fourth lead portion is greater than the line width of the second lead portion; The border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; the line width of the second lead portion in the first fan-out area is smaller than the line width of the second lead portion in the second fan-out area; The longitudinal length of the second fan-out region is greater than the longitudinal length of the first fan-out region; The border area also includes a bent area disposed between the first fan-out area and the second fan-out area, and the display substrate also includes a source / drain metal layer; The data signal lead further includes a fifth lead portion disposed in the bending region; the fifth lead portion is contained in the source / drain metal layer; The fourth direction is perpendicular or substantially perpendicular to the third direction; In the bending area, the interlayer dielectric layer is removed.

2. The display substrate as claimed in claim 1, wherein, The line width of the first lead portion is greater than or equal to 1.0 μm and less than or equal to 2.0 μm, and the line width of the second lead portion is greater than or equal to 1.5 μm and less than or equal to 3.0 μm.

3. The display substrate as described in claim 2, wherein, The linewidth of the third lead portion is greater than or equal to 1.8 μm and less than or equal to 4.0 μm.

4. The display substrate as described in claim 3, wherein, The linewidth of the fourth lead is greater than or equal to 3µm and less than or equal to 13µm.

5. The display substrate as claimed in claim 1, wherein, The border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; the first data signal lead includes a serpentine lead portion; The serpentine lead portion includes a plurality of first lead portions extending along a third direction, and a plurality of second lead portions extending along a fifth direction; the first lead portions and the second lead portions are alternately arranged, and adjacent first lead portions and second lead portions are coupled to each other.

6. The display substrate as claimed in claim 5, wherein, The shortest distance between two adjacent second lead portions included in the same serpentine lead portion is greater than or equal to 2.4 μm and less than or equal to 3 μm; the shortest distance between two adjacent serpentine lead portions is greater than or equal to 1.0 μm and less than or equal to 2 μm, and the line width of the first lead portion and the line width of the second lead portion are both greater than or equal to 1.8 μm and less than or equal to 2.4 μm.

7. The display substrate as claimed in claim 1, wherein, The border area includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; in the first fan-out area, the sum of the line width of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the line width of the second lead portion and the shortest distance between two adjacent second lead portions. In the second fan-out region, the sum of the linewidth of the first lead portion and the shortest distance between two adjacent first lead portions is equal to the sum of the linewidth of the second lead portion and the shortest distance between two adjacent second lead portions.

8. The display substrate as claimed in claim 7, wherein, The shortest distance between two adjacent first lead portions is greater than or equal to 1.0 μm and less than or equal to 2.0 μm; The shortest distance between two adjacent second lead portions is greater than or equal to 0.5um and less than or equal to 1.0um.

9. The display substrate according to any one of claims 1 to 8, wherein, The first included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees, and the second included angle is greater than 0 degrees and less than 89.5 degrees or greater than 90.5 degrees and less than 180 degrees.

10. The display substrate as claimed in claim 1, wherein, The border area includes a fan-out area, which includes a first fan-out area and a second fan-out area arranged along a direction away from the display area; The display substrate includes a substrate, and a first metal layer and a second metal layer stacked along a direction away from the substrate. The first data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer; The second data signal lead includes a lead portion disposed in the fan-out region that is contained in the first metal layer or the second metal layer; The adjacent data signal leads, including the lead portions disposed in the fan-out region, are contained in different layers.

11. The display substrate as claimed in claim 10, wherein, The display substrate includes a first source / drain metal layer and a second source / drain metal layer. On the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are stacked sequentially in a direction away from the substrate. The fifth lead portion is included in at least one of the first source / drain metal layer and the second source / drain metal layer.

12. The display substrate as claimed in claim 10, wherein, The display substrate includes a first source / drain metal layer, a second source / drain metal layer, and an additional source / drain metal layer; the fifth lead portion is included in at least one of the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer. On the side of the second metal layer facing away from the substrate, the first source / drain metal layer, the second source / drain metal layer, and the additional source / drain metal layer are sequentially stacked in a direction away from the substrate; or, on the side of the second metal layer facing away from the substrate, the additional source / drain metal layer, the first source / drain metal layer, and the second source / drain metal layer are sequentially stacked in a direction away from the substrate; or, the substrate includes a first substrate and a second substrate stacked together, the additional source / drain metal layer is disposed between the first substrate and the second substrate, and on the side of the second metal layer facing away from the substrate, the first source / drain metal layer and the second source / drain metal layer are sequentially stacked.

13. The display substrate as claimed in claim 10, wherein, The fan-out area also includes a third fan-out area, and the frame area also includes an electrostatic protection area and a box-in testing area; The second fan-out area, the electrostatic protection area, the cell assembly test area, and the third fan-out area are arranged sequentially along a direction away from the display area; The lead portion of the first data signal lead located in the electrostatic protection area and the box test area is disposed in the same layer as the lead portion of the first data signal lead located in the fan-out area. The second data signal lead includes a lead portion disposed in the electrostatic protection area and the box test area, which is disposed in the same layer as the lead portion disposed in the fan-out area.

14. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 13.

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