Driving device and display device

Abstract

The driving device and the display device provided by the embodiments of the present disclosure comprise: a first controller configured to generate and output a data control synchronization signal after power-on; wherein the data control synchronization signal is configured to control whether to load data voltage on a data line in a to-be-connected touch display panel; a second controller connected with the first controller; and the second controller is configured to directly output a first setting level signal and a second setting level signal when not powered on; wherein the first setting level signal is configured to control selection of a display driving mode from a plurality of driving modes supported by the to-be-connected touch display panel; and the second setting level signal is configured to control output of a driving signal of the corresponding display driving mode to the to-be-connected touch display panel.

Description

Technical Field

[0001] This disclosure relates to the field of drive technology, and in particular to drive devices and display devices. Background Technology

[0002] Typically, a display device includes a display panel and a controller. The display panel generally comprises multiple pixel units. Each pixel unit may include a red subpixel, a green subpixel, and a blue subpixel. The controller can input corresponding controls to the display panel, controlling the brightness of each subpixel, thereby mixing the desired colors to display a color image. Summary of the Invention

[0003] The driving device provided in this disclosure includes:

[0004] The first controller is configured to generate and output a data control synchronization signal after power-on; wherein the data control synchronization signal is configured to control whether to apply a data voltage to the data line in the touch display panel to be connected.

[0005] A second controller is connected to the first controller; and the second controller is configured to directly output a first set level signal and a second set level signal when not powered on.

[0006] Wherein, the first set level signal is configured to control the selection of a display driving mode from multiple driving modes supported by the touch display panel to be connected;

[0007] The second set level signal is configured to control the touch display panel to be connected to output a drive signal corresponding to the display drive mode.

[0008] In some examples, when the level of the data control synchronization signal is at a first level, the data line in the touch display panel to be connected is controlled to be loaded with a data voltage;

[0009] When the level of the data control synchronization signal is the second level, the control stops applying data voltage to the data lines in the touch display panel to be connected.

[0010] In some examples, the data control synchronization signal is a clock signal.

[0011] In some examples, the first controller is also configured to generate and output a clock control synchronization signal after power-on;

[0012] The second controller is also configured to receive the clock control synchronization signal after power-on, and generate and output a mode enable signal and a drive control synchronization signal according to the clock control synchronization signal;

[0013] The mode enable signal is configured to control the selection of a target drive mode from the plurality of drive modes;

[0014] The drive control synchronization signal is configured to control the touch display panel to be connected to output a drive signal corresponding to the target drive mode.

[0015] In some examples, the first controller is further configured to generate the data control synchronization signal based on the clock control synchronization signal.

[0016] In some examples, the first controller is further configured to generate the clock control synchronization signal and the data control synchronization signal simultaneously.

[0017] In some examples, the data control synchronization signal has the same timing as the clock control synchronization signal.

[0018] In some examples, the drive control synchronization signal is a clock signal;

[0019] The duration of the first level of the clock control synchronization signal within one clock cycle is within the duration of the first level of the drive control synchronization signal within one clock cycle.

[0020] The duration of the second level of the drive control synchronization signal within one clock cycle is within the duration of the second level of the clock control synchronization signal within one clock cycle.

[0021] In some examples, the first controller includes: a timing controller and a first switching resistor;

[0022] The first timing pin of the timing controller is coupled to the first end of the first conversion resistor, and the second end of the first conversion resistor is configured to output the data control synchronization signal.

[0023] The timing controller is configured to generate the data control synchronization signal after power-on and output the data control synchronization signal through the second terminal of the first conversion resistor.

[0024] In some examples, the timing controller is also configured to generate the clock control synchronization signal after power-on and output the clock control synchronization signal through the first timing pin.

[0025] In some examples, the second controller includes a microprocessor;

[0026] The microprocessor is configured to output the first set level signal directly through the first processing pin and the second set level signal through the second processing pin when not powered on.

[0027] In some examples, the microprocessor is also configured to receive the clock control synchronization signal via a third processing pin after power-on, and generate a mode enable signal and a drive control synchronization signal based on the clock control synchronization signal; and output the mode enable signal via the first processing pin, and output the drive control synchronization signal via the second processing pin.

[0028] In some examples, the driving device further includes: a touch display driving circuit; and the first driving pin of the touch display driving circuit is connected to a first processing pin of the microprocessor in the second controller, and the second driving pin of the touch display driving circuit is connected to a second processing pin of the microprocessor in the second controller.

[0029] The touch display driving circuit is configured to store multiple driving modes supported by the touch display panel, receive a first set level signal through the first driving pin and a second set level signal through the second driving pin, select the display driving mode from the multiple driving modes stored according to the first set level signal, and output a driving signal corresponding to the display driving mode to the touch display panel to be connected through the third driving pin according to the second set level signal.

[0030] In some examples, the touch display driving circuit is further configured to receive the mode enable signal via the first driving pin and the drive control synchronization signal via the second driving pin, select the target driving mode from the stored plurality of driving modes according to the mode enable signal, and output a driving signal corresponding to the target driving mode to the touch display panel to be connected via the third driving pin according to the drive control synchronization signal.

[0031] In some examples, the driving device further includes a level conversion circuit; and the level conversion circuit is connected to the first controller;

[0032] The first controller is also configured to output a scan control enable signal after power-on;

[0033] The level conversion circuit is configured to receive the scan control enable signal and output a scan clock signal according to the scan control enable signal;

[0034] The scanning clock signal is configured to load a gate scan signal onto the gate lines in the touch display panel to be connected.

[0035] The display device provided in this disclosure includes:

[0036] A touch display panel, including touch electrodes, a data cable, and a source drive circuit connected to the data cable;

[0037] The drive device is the drive device described above;

[0038] The first controller is connected to the source drive circuit, which is configured to receive the data control synchronization signal and control whether to apply data voltage to the connected data line according to the data control synchronization signal.

[0039] The second controller is connected to the touch electrode via the touch display driving circuit, and the touch electrode is configured to receive the driving signal.

[0040] In some examples, the touch display panel further includes gate lines and gate driving circuitry connected to the gate lines;

[0041] The gate drive circuit is connected to the level conversion circuit and is configured to receive a scan control enable signal and apply a gate scan signal to the connected gate line according to the scan control enable signal. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the display transpose structure in related technologies;

[0043] Figure 2 These are timing diagrams of some signals in related technologies;

[0044] Figure 3 For other signal timing diagrams in related technologies;

[0045] Figure 4 Some structural schematic diagrams of the driving device provided in the embodiments of this disclosure;

[0046] Figure 5 Some signal timing diagrams provided for embodiments of this disclosure;

[0047] Figure 6 Other structural schematic diagrams of the driving device provided in the embodiments of this disclosure;

[0048] Figure 7 Other signal timing diagrams provided for embodiments of this disclosure;

[0049] Figure 8 Further structural schematic diagrams of the driving device provided in the embodiments of this disclosure;

[0050] Figure 9 These are some structural schematic diagrams of the display transpose provided in the embodiments of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0053] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0054] See Figure 1 As shown, the display device may include a touch display panel 100 and a driving device. The touch display panel 100 may include multiple pixel units arranged in an array, touch electrodes, multiple gate lines GA, multiple data lines DA, a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is coupled to each gate line GA, and the source driving circuit 120 is coupled to each data line DA. The driving device may include a timing controller 200, a microprocessor 300, a touch display driving circuit 400, and a system controller 500. The system controller 500 may input a first power supply voltage VINP to the timing controller 200 to power the timing controller 200, thereby enabling the timing controller 200 to perform its functions after power-on. The system controller 500 may also input a second power supply voltage VTSP to the microprocessor 300 to power the microprocessor 300, thereby enabling the microprocessor 300 to perform its functions after power-on.

[0055] For example, when the touch display panel 100 uses self-capacitance technology to implement the touch function, the touch electrodes can be set as self-capacitance electrodes. When the touch display panel 100 uses mutual capacitance technology to implement the touch function, the touch electrodes can be set as mutual capacitance electrodes. When the touch display panel 100 uses pressure-sensitive capacitance technology to implement the touch function, the touch electrodes can be set as pressure-sensitive capacitance electrodes. Of course, in practical applications, the implementation method of the touch electrodes can be determined according to the actual application requirements, and is not limited here.

[0056] Exemplarily, the touch display panel 100 can be configured as at least one of a liquid crystal display (LCD) panel and an organic light-emitting diode (OLED) display panel. Exemplarily, when the touch display panel 100 is configured as a liquid crystal display panel, the touch electrodes can be reused as common electrodes. When the touch display panel 100 is configured as an OLED display panel, the touch electrodes can be reused as the cathode of the OLED.

[0057] For example, combined Figure 1 and Figure 2 As shown, after power-on, the timing controller 200 can send display data Vda to the source driver circuit 120 (this display data includes a digital voltage form carrying the corresponding grayscale value for each sub-pixel in the touch display panel 100), and can generate a control synchronization signal Tsync for display and touch timing, and send the generated signal Tsync to the microprocessor 300. Upon receiving the signal Tsync, the microprocessor 300 generates signals Tsync_SRIC, Tsync_TMIC, and MUX_EN according to the signal Tsync. The signal Tsync_SRIC is input to the source driver circuit 120 to control its operating state. For example, when the signal Tsync_SRIC is high, the source driver circuit 120 can load a data voltage onto the data line according to the received display data to achieve normal output data voltage for display. When the signal Tsync_SRIC is low, the source driver circuit 120 does not operate and pauses output.

[0058] Furthermore, the signal Tsync_TMIC is input to the touch display driver circuit 400 to control the signals output by the touch display driver circuit 400. For example, when the signal Tsync_TMIC is high, the touch display driver circuit 400 outputs a common voltage signal Vcom to the touch electrodes for display. When the signal Tsync_TMIC is low, the touch display driver circuit 400 outputs a touch detection signal Tsig to the touch electrodes for touch control.

[0059] Furthermore, the signal MUX_EN is input to the touch display driver circuit 400 to control which driving mode the touch display driver circuit 400 adopts. For example, when the signal MUX_EN is high, the touch display driver circuit 400 can select a display-touch switching driving mode, enabling the touch display driver circuit 400 to switch between display and touch operation. When the signal MUX_EN is low, the touch display driver circuit 400 can select a display driving mode, enabling the touch display driver circuit 400 to operate in a display-only mode.

[0060] Combination Figure 1 and Figure 2When the touch display panel 100 is in the display-touch switching drive mode, the system controller 500 sends a first power supply voltage VINP to the timing controller 200 to power it on. After the timing controller 200 is powered on, it generates and outputs a control synchronization signal Tsync, acquires the display data Vda of the screen to be displayed, and sends the display data Vda to the source driver circuit 120. Furthermore, the system controller 500 also inputs a second power supply voltage VTSP to the microprocessor 300 to power it on. After the microprocessor 300 is powered on, it can receive the control synchronization signal Tsync output by the timing controller 200 and generate clock signal Tsync_SRIC, clock signal Tsync_TMIC, and a high-level signal MUX_EN based on the received control synchronization signal Tsync. The microprocessor 300 then sends the generated signal Tsync_SRIC to the source driver circuit 120. When the signal Tsync_SRIC is high, the source drive circuit 120 applies a data voltage to the data line based on the display data Vda. The microprocessor 300 sends the generated signal Tsync_TMIC and the high-level signal MUX_EN to the touch display drive circuit 400. This allows the touch display drive circuit 400 to select the touch switching drive mode based on the high-level signal MUX_EN, and to output a common voltage signal Vcom to the touch electrodes based on the high level in the signal Tsync_TMIC. This allows the touch display drive circuit 400 to display an image through the interaction of the applied data voltage and the common voltage signal Vcom. Conversely, when both the signals Tsync_TMIC and Tsync_SRIC are low, the source drive circuit 120 stops applying the data voltage to the data line when the signal Tsync_SRIC is low. Furthermore, when the signal Tsync_TMIC is low, the touch display drive circuit 400 outputs a touch detection signal Tsig to the touch electrodes. This allows the touch display drive circuit 400 to perform touch control and maintain the display image.

[0061] Combination Figure 1 and Figure 3As shown, when controlling the touch display panel 100 to achieve a display-only driving mode, the system controller 510 can apply a first power supply voltage VINP to the timing controller 200 but not apply a second power supply voltage VTSP to the microprocessor 300, thereby not controlling the touch display panel 100 to achieve touch functionality. Since the first power supply voltage VINP is applied to the timing controller 200, the timing controller 200 is powered on. Therefore, the timing controller 200 can generate and output a control synchronization signal Tsync, and acquire the display data Vda of the screen to be displayed, sending the display data Vda to the source driver circuit 120. However, since the second power supply voltage VTSP is not applied to the microprocessor 300, the microprocessor 300 is not powered on and therefore does not work. Consequently, the voltage corresponding to the signal Tsync_SRIC input by the microprocessor 300 to the source driver circuit 120 is 0V, meaning the signal Tsync_SRIC will remain at a low level. This also causes the voltage corresponding to the signal Tsync_TMIC input to the touch display driver circuit 400 to be 0V, meaning the signal Tsync_TMIC will remain at a low level. However, due to the presence of the pull-up resistor, the signal MUX_EN input to the touch display driver circuit 400 will remain at a high level. Since the signal Tsync_SRIC will remain at a low level, the source driver circuit 120 will have no data voltage output, resulting in a black screen on the touch display panel 100, where no image is displayed, and the display driver mode cannot be achieved.

[0062] To address the aforementioned problems, some driving devices provided in the embodiments of this disclosure, combined with Figure 4 and Figure 5 As shown, the driving device may include a first controller 210 and a second controller 220. The second controller 220 is connected to the first controller 210. The first controller 210 can generate and output a data control synchronization signal Ts_SRIC after power-on. The second controller 220 can directly output a first set level signal Ms1_EN and a second set level signal Ts1_TMIC when not powered on. The data control synchronization signal Ts_SRIC can control whether to apply data voltage to the data lines in the touch display panel 100 to be connected. The first set level signal Ms1_EN can control the selection of a display driving mode from multiple driving modes supported by the touch display panel 100 to be connected, and the second set level signal Ts1_TMIC can control the output of a driving signal corresponding to the display driving mode to the touch display panel 100 to be connected.

[0063] The driving device provided in this embodiment can directly output a first setting level signal Ms1_EN to control the selection of the display driving mode, and a second setting level signal Ts1_TMIC to directly control the output of the driving signal corresponding to the display driving mode, when the second controller 220 is not powered on. Furthermore, after the first controller 210 is powered on, it can output a data control synchronization signal Ts_SRIC to control whether to apply data voltage to the data lines in the touch display panel 100 to be connected. This allows the touch display panel 100 to perform a display function without implementing a touch function when the first controller 210 is powered on and the second controller 220 is not powered on.

[0064] In some embodiments of this disclosure, when the level of the data control synchronization signal Ts_SRIC is a first level, data voltage can be applied to the data lines in the touch display panel 100 to be connected. And when the level of the data control synchronization signal Ts_SRIC is a second level, the application of data voltage to the data lines in the touch display panel 100 to be connected can be stopped. Exemplarily, the first level of the data control synchronization signal Ts_SRIC can be high, and the second level can be low. Alternatively, the first level of the data control synchronization signal Ts_SRIC can be low, and the second level can be high.

[0065] In some embodiments of this disclosure, the data control synchronization signal Ts_SRIC can be set as a square wave signal that switches between high and low levels. Exemplarily, the data control synchronization signal Ts_SRIC can be set as a clock signal. For example, the frequency of the data control synchronization signal Ts_SRIC set as a clock signal can be set to 960Hz, the duty cycle to 56.7%, the voltage corresponding to the high level to 2.5V, and the voltage corresponding to the low level to 0V. Of course, in practical applications, the specific implementation of the data control synchronization signal Ts_SRIC can be determined according to the needs of the actual application, and is not limited here.

[0066] In some embodiments of this disclosure, the first controller 210 may also generate and output a clock control synchronization signal Ts after power-on. The second controller 220 may also receive the clock control synchronization signal Ts after power-on, and generate and output a mode enable signal Ms2_EN and a drive control synchronization signal Ts2_TMIC based on the clock control synchronization signal Ts. The mode enable signal Ms2_EN can control the selection of a target drive mode from multiple drive modes. The drive control synchronization signal Ts2_TMIC can control the output of a drive signal corresponding to the target drive mode to the touch display panel 100 to be connected.

[0067] In some embodiments of this disclosure, the clock control synchronization signal Ts can be set as a square wave signal that switches between high and low levels. Exemplarily, the clock control synchronization signal Ts can be set as a clock signal. For example, the frequency of the clock control synchronization signal Ts set as a clock signal can be set to 960Hz, the duty cycle to 56.7%, the voltage corresponding to the high level to 2.5V, and the voltage corresponding to the low level to 0V. Of course, in practical applications, the specific implementation of the clock control synchronization signal Ts can be determined according to the needs of the actual application, and is not limited here.

[0068] In some embodiments of this disclosure, the first controller 210 may further generate a data control synchronization signal Ts_SRIC based on a clock control synchronization signal Ts. For example, as shown... Figure 5 As shown, the data control synchronization signal Ts_SRIC can be designed using a bypass approach to ensure that its waveform is identical to that of the clock control synchronization signal Ts, thus making their timing identical. For example, the first controller 210 can be further configured to simultaneously generate both the clock control synchronization signal Ts and the data control synchronization signal Ts_SRIC. This allows the first controller 210 to output clock control synchronization signals Ts and Ts_SRIC with identical waveforms, reducing signal design complexity.

[0069] In some embodiments of this disclosure, the drive control synchronization signal Ts2_TMIC can also be set as a clock signal. The duration of the first level within one clock cycle of the clock control synchronization signal Ts is within the duration of the first level within one clock cycle of the drive control synchronization signal Ts2_TMIC. The duration of the second level within one clock cycle of the drive control synchronization signal Ts2_TMIC is within the duration of the second level within one clock cycle of the clock control synchronization signal Ts. For example, as... Figure 5As shown, the first level can be high and the second level can be low. Then, the duration of the high level in one clock cycle of the clock control synchronization signal Ts is within the duration of the high level in one clock cycle of the drive control synchronization signal Ts2_TMIC. The duration of the low level in one clock cycle of the drive control synchronization signal Ts2_TMIC is within the duration of the low level in one clock cycle of the clock control synchronization signal Ts. Alternatively, the first level can also be high and the second level can be low. Then, the duration of the low level in one clock cycle of the clock control synchronization signal Ts is within the duration of the low level in one clock cycle of the drive control synchronization signal Ts2_TMIC. The duration of the high level in one clock cycle of the drive control synchronization signal Ts2_TMIC is within the duration of the high level in one clock cycle of the clock control synchronization signal Ts.

[0070] For example, the frequency of the drive control synchronization signal Ts2_TMIC, which can be set as a clock signal, can be set to 960Hz, the duty cycle to 68.4%, the voltage corresponding to the high level to 2.5V, and the voltage corresponding to the low level to 0V. Of course, in practical applications, the specific implementation of the drive control synchronization signal Ts2_TMIC can be determined according to the actual application requirements, and is not limited here.

[0071] In some embodiments of this disclosure, such as Figure 6 and Figure 8 As shown, the first controller 210 may include a timing controller 211 and a first conversion resistor Rz1. The timing controller 211 has a first timing pin SX1 coupled to a first terminal of the first conversion resistor Rz1, and the second terminal of the first conversion resistor Rz1 is configured to output a data control synchronization signal Ts_SRIC. Exemplarily, the timing controller 211 can generate the data control synchronization signal Ts_SRIC after power-on and output it through the second terminal of the first conversion resistor Rz1. Furthermore, the timing controller 211 can also generate a clock control synchronization signal Ts after power-on and output it through the first timing pin SX1. This allows the data control synchronization signal Ts_SRIC to be designed using a bypass, ensuring that the waveform of the data control synchronization signal Ts_SRIC is identical to that of the clock control synchronization signal Ts, thereby ensuring that the timing of the data control synchronization signal Ts_SRIC and the clock control synchronization signal Ts is the same. Furthermore, it is only necessary to add a first conversion resistor Rz1 to the original design of the timing controller 211 to realize the output of the data control synchronization signal Ts_SRIC, thus reducing the design difficulty.

[0072] For example, the first timing pin SX1 can be configured as a pin in a general purpose input / output (GPIO) interface. For instance, the first timing pin SX1 can be configured as pin GPIO22 in the GPIO interface of the timing controller 211. Of course, in practical applications, it can be determined according to the specific application requirements, and this is not limited here. It should be noted that the functions and connection methods of other pins in the timing controller 211 are basically the same as those in related technologies, and will not be elaborated upon here.

[0073] In some embodiments of this disclosure, such as Figure 6 and Figure 8 As shown, the second controller 220 may include a microprocessor 221. The microprocessor 221 can, when not powered on, directly output a first set level signal Ms1_EN through a first processing pin CL1 and a second set level signal Ts1_TMIC through a second processing pin CL2. For example, the first set level signal Ms1_EN is output directly through the first processing pin CL1 without a pull-up resistor. Furthermore, since the microprocessor 221 is not powered on, it can be inactive and therefore does not control the pull-up action of the first processing pin CL1 and the second processing pin CL2. Therefore, when the microprocessor 221 is not powered on, both the first set level signal Ms1_EN output from the first processing pin CL1 and the second set level signal Ts1_TMIC output from the second processing pin CL2 can be low-level signals.

[0074] In some embodiments of this disclosure, such as Figure 6 and Figure 8 As shown, after power-on, the microprocessor 221 can also receive the clock control synchronization signal Ts output from the first timing pin SX1 of the timing controller 211 via the third processing pin CL3, and generate a mode enable signal Ms2_EN and a drive control synchronization signal Ts2_TMIC according to the clock control synchronization signal Ts. It then outputs the mode enable signal Ms2_EN via the first processing pin CL1 and the drive control synchronization signal Ts2_TMIC via the second processing pin CL2. In other words, after power-on, the microprocessor 221 can perform corresponding processing tasks and generate the mode enable signal Ms2_EN and the drive control synchronization signal Ts2_TMIC according to the clock control synchronization signal Ts.

[0075] For example, the first processing pin CL1, the second processing pin CL2, and the third processing pin CL3 can be configured as pins in the GPIO interface. For instance, the first processing pin CL1 can be configured as pin GPIOA26 in the GPIO interface of the microprocessor 221. The second processing pin CL2 can be configured as pin GPIOA40 in the GPIO interface of the microprocessor 221. The third processing pin CL3 can be configured as pin GPIOA35 in the GPIO interface of the microprocessor 221. Of course, in practical applications, these configurations can be determined according to the specific application requirements, and are not limited here. It should be noted that the functions and connection methods of other pins in the microprocessor 221 are basically the same as those in related technologies, and will not be elaborated upon here.

[0076] In some embodiments of this disclosure, such as Figure 6 and Figure 8 As shown, the driving device may further include a touch display driving circuit 410; and the first driving pin QD1 of the touch display driving circuit 410 is connected to the first processing pin CL1 of the microprocessor 221 in the second controller 220, and the second driving pin QD2 of the touch display driving circuit 410 is connected to the second processing pin CL2 of the microprocessor 221 in the second controller 220. Furthermore, the touch display driving circuit 410 may store multiple driving modes supported by the touch display panel 100, and when the microprocessor 221 is not powered on, it receives a first setting level signal Ms1_EN through the first driving pin QD1 and a second setting level signal Ts1_TMIC through the second driving pin QD2, selects a display driving mode from the stored multiple driving modes according to the first setting level signal Ms1_EN, and outputs a driving signal corresponding to the display driving mode to the touch display panel 100 to be connected through the third driving pin according to the second setting level signal Ts1_TMIC. Furthermore, after the microprocessor 221 is powered on, the touch display driving circuit 410 can receive the mode enable signal Ms2_EN through the first driving pin QD1 and the drive control synchronization signal Ts2_TMIC through the second driving pin QD2, and select the target driving mode from multiple stored driving modes according to the mode enable signal Ms2_EN, and output the corresponding target driving mode driving signal to the touch display panel 100 to be connected through the third driving pin according to the drive control synchronization signal Ts2_TMIC.

[0077] For example, the first driving pin QD1 and the second driving pin QD2 can be configured as pins in the GPIO interface. For instance, the first driving pin QD1 and the second driving pin QD2 can be configured as pins in the GPIO interface of the touch display driver circuit. Of course, in practical applications, these can be determined according to the specific application requirements, and are not limited here. It should be noted that the functions and connection methods of other pins in the touch display driver circuit are basically the same as those in related technologies, and will not be elaborated upon here.

[0078] For example, the multiple driving modes supported by the touch display panel 100 stored in the touch display driving circuit 410 may include a display-touch switching driving mode that controls the touch display panel 100 to both display and touch, a display driving mode that controls only the touch display panel 100 to display, and a touch driving mode that controls only the touch display panel 100 to touch. For example, the target driving mode may be a display-touch switching driving mode that controls the touch display panel 100 to both display and touch. Alternatively, the target driving mode may also be a display driving mode that controls only the touch display panel 100 to display. Alternatively, the target driving mode may also be a touch driving mode that controls only the touch display panel 100 to touch. Of course, in practical applications, the specific manner in which the driving modes and target driving modes stored in the touch display driving circuit are determined according to the needs of the actual application, and is not limited here.

[0079] In some embodiments of this disclosure, such as Figure 6 As shown, the driving device may further include a level conversion circuit 600; and the level conversion circuit 600 is connected to the timing controller 211 in the first controller 210. The first controller 210 may also output scan control enable signals CLK_ON and CLK_OFF after power-on. The level conversion circuit 600 may receive the scan control enable signals CLK_ON and CLK_OFF, and output a scan clock signal GOA_CLK according to the scan control enable signals CLK_ON and CLK_OFF. The scan clock signal GOA_CLK may be configured to load gate scan signals onto the gate lines of the touch display panel 100 to be connected.

[0080] In some embodiments of this disclosure, such as Figure 4 and Figure 6As shown, the drive device may further include a system controller 510. The system controller 510 can provide a voltage V1 to the timing controller 211 in the first controller 210 to power on the timing controller 211. The system controller 510 can also provide a voltage V2 to the microprocessor 221 in the second controller 220 to power on the microprocessor 221. Exemplarily, the system controller 510 can provide voltage V1 to the timing controller 211 in the first controller 210 while simultaneously providing voltage V2 to the microprocessor 221 in the second controller 220. Alternatively, the system controller 510 can provide voltage V1 to the timing controller 211 in the first controller 210 without providing voltage V2 to the microprocessor 221 in the second controller 220.

[0081] In some embodiments of this disclosure, the system controller 510 may include a system-on-chip (SOC). The touch display driving circuitry may include a display driver integrated circuit (e.g., an integrated circuit, IC) chip.

[0082] In some embodiments of this disclosure, at least two of the system controller 510, first controller 210, second controller 220, touch display driver circuit 410, and level conversion circuit 600 can be disposed on the same circuit board. This improves integration. Exemplarily, the system controller 510, first controller 210, second controller 220, touch display driver circuit 410, and level conversion circuit 600 can be disposed on the same circuit board. This maximizes integration. Of course, the system controller 510, first controller 210, second controller 220, touch display driver circuit 410, and level conversion circuit 600 can also be disposed on different circuit boards. In practical applications, the specific configuration can be determined according to the requirements of the application, and no limitation is made here.

[0083] This disclosure also provides some display devices, such as... Figure 9 As shown, the display device may include a touch display panel 100 and a driving device. The touch display panel 100 can be coupled with... Figure 1 The basic structure is the same as that in the previous one, and the structure of the drive device can be as follows: Figures 4 to 8 The structure is basically the same as that in other languages, so I will not go into details here.

[0084] For example, combined Figure 9As shown, the timing controller 211 in the first controller 210 can be connected to the source drive circuit 120. The source drive circuit 120 can receive a data control synchronization signal Ts_SRIC and control whether to apply a data voltage to the connected data line according to the data control synchronization signal Ts_SRIC. For example, when the level of the data control synchronization signal Ts_SRIC is a first level, the source drive circuit 120 can be controlled to operate to apply a data voltage to the data line DA in the touch display panel 100 to be connected. And, when the level of the data control synchronization signal Ts_SRIC is a second level, the source drive circuit 120 can be controlled to stop operating to stop applying a data voltage to the data line DA in the touch display panel 100 to be connected.

[0085] For example, combined Figure 9 As shown, the second controller 220 is connected to the touch electrode via the touch display driving circuit 410, and the touch electrode can receive driving signals. For example, when a display driving mode is selected, the driving signal received by the touch electrode can be a common voltage signal Vcom, so that the touch display panel 100 only performs the display function. When a display touch switching driving mode is selected, the driving signal received by the touch electrode can alternate between the common voltage signal Vcom and the touch detection signal Tsig, so that the touch display panel 100 performs both display and touch functions.

[0086] For example, combined Figure 9 As shown, the gate driving circuit 110 can be connected to the level conversion circuit 600. Furthermore, the gate driving circuit 110 can receive scan control enable signals CLK_ON and CLK_OFF, and load gate scan signals onto the connected gate lines GA according to the scan control enable signals CLK_ON and CLK_OFF. For example, the gate driving circuit 110 can load gate scan signals onto the connected gate lines row by row to drive the gate lines row by row, thereby allowing sub-pixels to input data voltage row by row. Alternatively, the gate driving circuit 110 can also load gate scan signals onto the connected gate lines every other row to drive the gate lines every other row, thereby allowing sub-pixels to input data voltage every other row.

[0087] The following is combined Figure 5 , Figure 7 as well as Figure 9 The operation of the display device provided in the embodiments of this disclosure will be described.

[0088] When controlling the touch display panel 100 to achieve a display-only driving mode, the system controller 510 can provide voltage V1 to the timing controller 211 in the first controller 210 to power on the timing controller 211. Furthermore, if voltage V2 is not provided to the microprocessor 221 in the second controller 220, the microprocessor 221 will not be powered on. After the timing controller 211 in the first controller 210 is powered on, it can acquire the display data of the screen to be displayed and generate a clock control synchronization signal Ts. The clock control synchronization signal Ts generated through the first timing cathode output, and the clock control synchronization signal Ts output from the first timing pin SX1, are then converted into a data control synchronization signal Ts_SRIC through the first conversion resistor Rz1. The clock control synchronization signal Ts can be input to the microprocessor 221 in the unpowered second controller 220. However, since the microprocessor 221 in the second controller 220 is not powered on and does not operate, its first processing pin CL1 directly outputs a low-level first setting level signal Ms1_EN, and its second processing pin CL2 outputs a low-level second setting level signal Ts1_TMIC. The timing controller 211 in the first controller 210 can send the display data of the screen to be displayed to the source drive circuit 120, and it can also send the data control synchronization signal Ts_SRIC output through the first conversion resistor Rz1 to the source drive circuit 120. Thus, when the data control synchronization signal Ts_SRIC is high, the source drive circuit 120 can be controlled to operate, applying data voltage to the connected data lines according to the received display data. When the data control synchronization signal Ts_SRIC is low, the source drive circuit can be controlled to stop operating and not output data voltage. The low-level first setting level signal Ms1_EN and the low-level second setting level signal Ts1_TMIC can be input to the touch display driver circuit respectively. The low-level first setting level signal Ms1_EN can select the display driving mode, and the low-level second setting level signal Ts1_TMIC can control the touch display driver circuit 410 to output a common voltage signal Vcom to the touch electrodes. In this way, the sub-pixels can realize the display function under the joint control of the data voltage and the common voltage signal Vcom.

[0089] When controlling the touch display panel 100 to switch between display and touch operation in the display touch switching drive mode, the system controller 510 can provide voltage V1 to the timing controller 211 in the first controller 210 to power on the timing controller 211, and provide voltage V2 to the microprocessor 221 in the second controller 220 to power on the microprocessor 221. After the timing controller 211 in the first controller 210 is powered on, it can acquire the display data of the screen to be displayed and generate a clock control synchronization signal Ts. The clock control synchronization signal Ts generated through the first timing cathode output and the clock control synchronization signal Ts output by the first timing pin SX1 are then converted into a data control synchronization signal Ts_SRIC through the first conversion resistor Rz1. The clock control synchronization signal Ts can be input to the microprocessor 221 in the powered-on second controller 220. Therefore, the microprocessor 221 in the second controller 220 can pull the first processing pin CL1 high according to the clock control synchronization signal Ts, so that the first processing pin CL1 outputs a high-level mode enable signal Ms2_EN. Furthermore, the microprocessor 221 in the second controller 220 can generate a clock signal mode drive control synchronization signal Ts2_TMIC based on the clock control synchronization signal Ts, and output the drive control synchronization signal Ts2_TMIC through the second processing pin CL2. The mode enable signal Ms2_EN and the drive control synchronization signal Ts2_TMIC are respectively input to the touch display drive circuit 410. Under the control of the high-level mode enable signal Ms2_EN, the display touch switching drive mode can be selected.

[0090] Furthermore, the timing controller 211 in the first controller 210 can send the display data of the image to be displayed to the source drive circuit 120, and the timing controller 211 in the first controller 210 can also send the data control synchronization signal Ts_SRIC output through the first conversion resistor Rz1 to the source drive circuit 120. Thus, when the data control synchronization signal Ts_SRIC is high, the source drive circuit 120 can be controlled to operate, applying a data voltage to the connected data lines according to the received display data. At this time, the drive control synchronization signal Ts2_TMIC is high, controlling the touch display drive circuit 410 to output a common voltage signal Vcom to the touch electrodes. This allows the sub-pixels to achieve the image display function under the joint control of the data voltage and the common voltage signal Vcom.

[0091] Furthermore, when the data control synchronization signal Ts_SRIC is low, the source drive circuit 120 can be controlled to stop working and not output data voltage. At this time, the drive control synchronization signal Ts2_TMIC is low, controlling the touch display drive circuit 410 to output a touch detection signal Tsig to the touch electrode. This enables the touch display drive circuit 410 to achieve touch control and maintain the display screen.

[0092] It should be noted that the process of the touch display panel 100 operating in display driving mode can be either a display test conducted after the touch display panel 100 and the driving device have been assembled but before leaving the factory, or a process after leaving the factory where, in order to reduce power consumption, only the touch display panel 100 is controlled to perform the display function, without performing the touch function.

[0093] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0097] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0098] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A driving device, comprising: The first controller is configured to generate and output a data control synchronization signal after power-on, and to generate and output a clock control synchronization signal after power-on; wherein the data control synchronization signal is configured to control whether to apply a data voltage to the data line in the touch display panel to be connected. A second controller is connected to the first controller; and the second controller is configured to directly output a first set level signal and a second set level signal when not powered on, and to receive the clock control synchronization signal after power-on, and to generate and output a mode enable signal and a drive control synchronization signal according to the clock control synchronization signal. Wherein, the first set level signal is configured to control the selection of a display driving mode from multiple driving modes supported by the touch display panel to be connected; The second set level signal is configured to control the touch display panel to be connected to output a drive signal corresponding to the display drive mode; The mode enable signal is configured to control the selection of a target drive mode from the plurality of drive modes; The drive control synchronization signal is configured to control the touch display panel to be connected to output a drive signal corresponding to the target drive mode.

2. The driving device as claimed in claim 1, wherein, When the level of the data control synchronization signal is the first level, the data voltage is applied to the data line in the touch display panel to be connected. When the level of the data control synchronization signal is the second level, the control stops applying data voltage to the data lines in the touch display panel to be connected.

3. The driving device as claimed in claim 2, wherein, The data control synchronization signal is a clock signal.

4. The driving device as claimed in claim 1, wherein, The first controller is further configured to generate the data control synchronization signal based on the clock control synchronization signal.

5. The driving device as claimed in claim 4, wherein, The first controller is further configured to simultaneously generate the clock control synchronization signal and the data control synchronization signal.

6. The driving device as claimed in claim 1, wherein, The data control synchronization signal has the same timing as the clock control synchronization signal.

7. The driving device as claimed in claim 1, wherein, The drive control synchronization signal is a clock signal; The duration of the first level of the clock control synchronization signal within one clock cycle is within the duration of the first level of the drive control synchronization signal within one clock cycle. The duration of the second level of the drive control synchronization signal within one clock cycle is within the duration of the second level of the clock control synchronization signal within one clock cycle.

8. The driving device as claimed in claim 1, wherein, The first controller includes: a timing controller and a first switching resistor; The first timing pin of the timing controller is coupled to the first end of the first conversion resistor, and the second end of the first conversion resistor is configured to output the data control synchronization signal. The timing controller is configured to generate the data control synchronization signal after power-on and output the data control synchronization signal through the second terminal of the first conversion resistor.

9. The driving device as claimed in claim 8, wherein, The timing controller is also configured to generate the clock control synchronization signal after power-on and output the clock control synchronization signal through the first timing pin.

10. The driving device as claimed in claim 1, wherein, The second controller includes: a microprocessor; The microprocessor is configured to output the first set level signal directly through the first processing pin and the second set level signal through the second processing pin when not powered on.

11. The driving device as claimed in claim 10, wherein, The microprocessor is also configured to receive the clock control synchronization signal via a third processing pin after power-on, and generate a mode enable signal and a drive control synchronization signal according to the clock control synchronization signal; and output the mode enable signal via the first processing pin, and output the drive control synchronization signal via the second processing pin.

12. The driving device as claimed in claim 1, wherein, The driving device further includes: a touch display driving circuit; and the first driving pin of the touch display driving circuit is connected to the first processing pin of the microprocessor in the second controller, and the second driving pin of the touch display driving circuit is connected to the second processing pin of the microprocessor in the second controller. The touch display driving circuit is configured to store multiple driving modes supported by the touch display panel, receive a first set level signal through the first driving pin and a second set level signal through the second driving pin, select the display driving mode from the multiple driving modes stored according to the first set level signal, and output a driving signal corresponding to the display driving mode to the touch display panel to be connected through the third driving pin according to the second set level signal.

13. The driving device as claimed in claim 12, wherein, The touch display driving circuit is further configured to receive the mode enable signal through the first driving pin and the drive control synchronization signal through the second driving pin, select the target driving mode from the stored plurality of driving modes according to the mode enable signal, and output a driving signal corresponding to the target driving mode to the touch display panel to be connected through the third driving pin according to the drive control synchronization signal.

14. The driving device as claimed in claim 1, wherein, The driving device further includes a level conversion circuit; and the level conversion circuit is connected to the first controller. The first controller is also configured to output a scan control enable signal after power-on; The level conversion circuit is configured to receive the scan control enable signal and output a scan clock signal according to the scan control enable signal; The scanning clock signal is configured to load a gate scan signal onto the gate lines in the touch display panel to be connected.

15. A display device, comprising: The touch display panel includes touch electrodes, a data cable, and a source drive circuit connected to the data cable; The driving device is the driving device as described in any one of claims 1-14; The first controller is connected to the source drive circuit, which is configured to receive the data control synchronization signal and control whether to apply data voltage to the connected data line according to the data control synchronization signal. The second controller is connected to the touch electrode via a touch display driving circuit, and the touch electrode is configured to receive the driving signal.

16. The display device as claimed in claim 15, wherein, The touch display panel also includes gate lines and a gate driving circuit connected to the gate lines; The gate drive circuit is connected to the level conversion circuit and is configured to receive a scan control enable signal and apply a gate scan signal to the connected gate line according to the scan control enable signal.

Images