Display substrate, driving method thereof, and display device

Abstract

A display substrate, its driving method, and a display device are disclosed, belonging to the field of display technology. The display substrate includes multiple light-emitting elements (L1) and multiple pixel circuit groups (Z1) located in a display area (AA). At least one pixel circuit group (Z1) may include multiple pixel circuit subgroups (Z11) arranged along a first direction (X1), and each pixel circuit subgroup (Z11) may include multiple pixel circuits (02) arranged along a second direction (X2). The first direction (X1) and the second direction (X2) may intersect. Each pixel circuit (02) includes a data writing circuit (021) that is coupled to a first scan line (Scan1), a switch control line (MUX1), a data signal line (Data), and a driving circuit (022), respectively. Under the control of the first scan line (Scan1) and the switch control line (MUX1), it can transmit data signals provided by the data signal line (Data) to the driving circuit (022), causing the driving circuit (022) to drive the coupled light-emitting elements (L1) to emit light. Within the same pixel circuit group (Z1), each pixel circuit subgroup (Z11) is coupled to a different switch control line (MUX1), and multiple coupled data signal lines (Data) are coupled to the same data line (S1) to receive data signals from the data line (S1). Each pixel circuit (02) can receive data signals provided by the data line (S1) to its coupled data signal line (Data) under the control of its coupled switch control line (MUX1). Consequently, the data signals received by each pixel circuit (02) from the shared data line (S1) have better uniformity, resulting in better display uniformity of the display substrate.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and its driving method, and a display device. Background Technology

[0002] A display substrate typically includes multiple pixel circuits and multiple light-emitting elements. Each pixel circuit is coupled to a scan signal line, a data signal line, a power supply terminal, and a light-emitting element, and is configured to provide a light-emitting driving signal to the light-emitting element based on the scan signal provided by the scan signal line, the data signal provided by the data signal line, and the power supply signal provided by the power supply terminal, so as to drive the light-emitting element to emit light. Summary of the Invention

[0003] This disclosure provides a display substrate and its driving method, as well as a display device, which can solve the problem of uneven display on display substrates in related technologies. The technical solution is as follows:

[0004] On one hand, a display substrate is provided, comprising:

[0005] A substrate having a display area and a non-display area at least partially surrounding the display area;

[0006] Multiple light-emitting elements are located in the display area;

[0007] Multiple pixel circuit groups are located in the display area, and at least one of the pixel circuit groups includes multiple pixel circuit subgroups arranged along a first direction, and each pixel circuit subgroup includes multiple pixel circuits arranged along a second direction, wherein the first direction and the second direction intersect.

[0008] Multiple first scan lines and multiple data signal lines are located in the display area and the non-display area, and are coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups;

[0009] Multiple switch control lines and multiple data lines are located in the non-display area and are coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups;

[0010] At least one of the pixel circuits includes a data writing circuit and a driving circuit. The data writing circuit is coupled to the first scan line, the switch control line, the data signal line, and the driving circuit, respectively. The data writing circuit is configured to control the on / off state of the data signal line and the driving circuit in response to a first scan signal provided by the first scan line and a switch control signal provided by the switch control line. The driving circuit is also coupled to the light-emitting element and is configured to drive the light-emitting element to emit light based on the data signal provided by the data writing circuit.

[0011] Furthermore, the same pixel circuit subgroup is coupled to the same switch control line and the same data signal line; multiple pixel circuit subgroups in the same pixel circuit group are coupled to different switch control lines, and multiple data signal lines coupled to multiple pixel circuit subgroups in the same pixel circuit group are coupled to the same data line and receive data signals from the data line.

[0012] Optionally, in different pixel circuit groups, at least two pixel circuit subgroups share one of the multiple switch control lines.

[0013] Optionally, in the plurality of pixel circuit groups, each pixel circuit group includes a plurality of pixel circuit subgroups that share the plurality of switch control lines.

[0014] Optionally, each pixel circuit group includes a number of pixel circuit subgroups that are greater than or equal to 2 and less than or equal to 5.

[0015] Optionally, the plurality of switch control lines and the plurality of first scan lines extend along the first direction;

[0016] The plurality of data signal lines and the plurality of data lines extend along the second direction.

[0017] Optionally, the first direction is perpendicular to the second direction.

[0018] Optionally, the multiple switch control lines are configured to provide switch control signals to the data writing circuits of different pixel circuit subgroups at different time periods.

[0019] Optionally, the data writing circuit includes: a data writing sub-circuit and a switching sub-circuit;

[0020] The data writing sub-circuit is coupled to the first scan line, the data signal line and the switch sub-circuit respectively. The data writing sub-circuit is configured to control the on / off state of the data signal line and the switch sub-circuit in response to the first scan signal.

[0021] The switch sub-circuit is also coupled to the switch control line and the drive circuit respectively. The switch sub-circuit is configured to control the on / off state of the data writing sub-circuit and the drive circuit in response to the switch control signal.

[0022] Optionally, the data writing sub-circuit includes: a data writing transistor;

[0023] The gate of the data writing transistor is coupled to the first scan line, the first electrode of the data writing transistor is coupled to the data signal line, and the second electrode of the data writing transistor is coupled to the switch sub-circuit.

[0024] Optionally, the switching sub-circuit includes: a switching transistor;

[0025] The gate of the switching transistor is coupled to the switching control line, the first terminal of the switching transistor is coupled to the data writing sub-circuit, and the second terminal of the switching transistor is coupled to the driving circuit.

[0026] Optionally, the display substrate further includes: multiple first light-emitting control lines, multiple second light-emitting control lines, multiple second scan lines, multiple initialization signal lines, and multiple first power lines, located in the display area and the non-display area, and coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups; the driving circuit includes: an initialization circuit and a light-emitting driving circuit;

[0027] The initialization circuit is coupled to the second scan line, the initialization signal line, the light-emitting driving circuit, and the first electrode of the light-emitting element, respectively. The initialization circuit is configured to control the on / off state of the initialization signal line with the light-emitting driving circuit and the first electrode of the light-emitting element in response to the second scan signal provided by the second scan line.

[0028] The light-emitting driving circuit is also coupled to the data writing circuit, the first power line, the first light-emitting control line, the second light-emitting control line, and the first electrode of the light-emitting element. The light-emitting driving circuit is configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element in response to the data signal provided by the data writing circuit, the first light-emitting control signal provided by the first light-emitting control line, the second light-emitting control signal provided by the second light-emitting control line, and the first power signal provided by the first power line.

[0029] The second electrode of the light-emitting element is configured to be coupled to the second power line, and the light-emitting element is configured to emit light based on the light-emitting drive signal and the second power signal provided by the second power line.

[0030] Optionally, the light-emitting driving circuit includes: a storage sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit;

[0031] The storage sub-circuit is coupled to the data writing circuit and the light emission control sub-circuit respectively, and the storage sub-circuit is configured to adjust the potential at the coupling point;

[0032] The light emission control sub-circuit is also coupled to the first light emission control line, the second light emission control line, the first power supply line, the data writing circuit and the driving sub-circuit respectively. The light emission control sub-circuit is configured to control the on / off state of the first power supply line and the driving sub-circuit in response to the first light emission control signal and the second light emission control signal.

[0033] The driving sub-circuit is also coupled to the first electrode of the light-emitting element, and the driving sub-circuit is configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element in response to a signal provided by the light-emitting control sub-circuit.

[0034] Optionally, the light-emitting control sub-circuit includes: a first light-emitting control transistor, a second light-emitting control transistor, and a third light-emitting control transistor;

[0035] The gate of the first light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the first power supply line, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the third light-emitting control transistor.

[0036] The gate of the second light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the data writing circuit, and the second electrode of the second light-emitting control transistor is coupled to the driving sub-circuit and the initialization circuit.

[0037] The gate of the third light-emitting control transistor is coupled to the second light-emitting control line, and the second electrode of the third light-emitting control transistor is coupled to the driving sub-circuit.

[0038] Optionally, the driving sub-circuit includes: a driving transistor;

[0039] The gate of the driving transistor is coupled to the light-emitting control sub-circuit and the initialization circuit, respectively. The first electrode of the driving transistor is coupled to the light-emitting control sub-circuit, and the second electrode of the driving transistor is coupled to the first electrode of the light-emitting element.

[0040] Optionally, the storage sub-circuit includes: a storage capacitor;

[0041] The first end of the storage capacitor is coupled to the data writing circuit, and the second end of the storage capacitor is coupled to the light-emitting control sub-circuit.

[0042] Optionally, the initialization circuit includes: a first initialization transistor and a second initialization transistor;

[0043] The gates of the first initialization transistor and the second initialization transistor are both coupled to the second scan line. The first terminals of the first initialization transistor and the second initialization transistor are both coupled to the initialization signal line. The second terminal of the first initialization transistor is coupled to the light-emitting driving circuit, and the second terminal of the second initialization transistor is coupled to the first terminal of the light-emitting element.

[0044] On the other hand, a driving method for a display substrate is provided, configured to drive the display substrate as described above, the method comprising:

[0045] Multiple switch control lines provide switch control signals at different times, and multiple first scan lines provide first scan signals at different times. The data writing circuits in the multiple pixel circuits of different pixel circuit subgroups respond in a time-division manner to the first scan signal and the switch control signal, controlling the data signal line to be connected to the driving circuit so that the data signal line transmits the data signal from the data line to the driving circuit.

[0046] In another aspect, a display device is provided, the display device comprising: a first driving circuit, a second driving circuit, and a display substrate as described above;

[0047] The first driving circuit is coupled to multiple switch control lines in the display substrate, and the first driving circuit is configured to provide switch control signals to the multiple switch control lines;

[0048] The second driving circuit is coupled to multiple data lines in the display substrate, and the second driving circuit is configured to provide data signals to the multiple data lines.

[0049] Optionally, the first driving circuit and the second driving circuit are integrated.

[0050] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can include at least the following:

[0051] A display substrate and its driving method, as well as a display device, are provided, belonging to the field of display technology. Each pixel circuit includes a data writing circuit that is coupled to a first scan line, a switch control line, a data signal line, and a driving circuit, respectively. Under the control of the first scan line and the switch control line, the data writing circuit transmits data signals provided by the data signal line to the driving circuit, causing the driving circuit to drive the coupled light-emitting element to emit light. In the same pixel circuit group, each pixel circuit subgroup is coupled to different switch control lines, and multiple coupled data signal lines are coupled to the same data line to receive data signals from the data line. Thus, each pixel circuit can receive data signals provided by the data line to its coupled data signal line under the control of its coupled switch control line. Furthermore, the data signal received by each pixel circuit from the shared data line has good uniformity, resulting in better display uniformity of the display substrate. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0054] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present disclosure;

[0055] Figure 3 This is a schematic diagram of another display substrate structure provided in an embodiment of this disclosure;

[0056] Figure 4 This is a schematic diagram of the structure of another display substrate provided in this embodiment;

[0057] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure;

[0058] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0059] Figure 7 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0060] Figure 8 This is a schematic diagram of another pixel circuit provided in an embodiment of the present disclosure;

[0061] Figure 9 This is a schematic diagram of the structure of another display substrate provided in this embodiment;

[0062] Figure 10 This is a timing diagram of the signal terminals coupled to a pixel circuit according to an embodiment of the present disclosure;

[0063] Figure 11 This is a schematic diagram of a current display substrate structure provided in an embodiment of this disclosure;

[0064] Figure 12 This is a flowchart of a driving method for a display substrate provided in an embodiment of this disclosure;

[0065] Figure 13 This is a flowchart of a pixel circuit driving method provided in an embodiment of this disclosure;

[0066] Figure 14This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0068] All transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of this disclosure are mainly switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their sources and drains are interchangeable. In the embodiments of this disclosure, the source is referred to as the first terminal and the drain as the second terminal, or vice versa. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the switching transistors used in the embodiments of this disclosure can include any one or a combination of P-type and N-type transistors. The P-type transistor conducts when the gate is low and is cut off when the gate is high, while the N-type transistor conducts when the gate is high and is cut off when the gate is low. In addition, multiple signals in the various embodiments of this disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent that the potential of the signal has two different states and do not represent that the first potential or the second potential has a specific value throughout the text. Furthermore, the term "coupled" as used in the embodiments of this disclosure can refer to an electrical connection.

[0069] Organic light-emitting diode (OLED) displays, compared to liquid crystal displays (LCDs), offer advantages such as wider color gamut, higher contrast, energy efficiency, and foldability, making them highly competitive in the 21st-century display market. Based on this, active-matrix organic light-emitting diode (AMOLED) displays, derived from OLED devices, are gradually becoming a key development direction for flexible displays. OLED and AMOLED displays can be collectively referred to as OLED-type display devices.

[0070] Currently, in OLED display devices, each pixel comprises multiple sub-pixels of different colors, and each sub-pixel includes a pixel circuit and a light-emitting element. The pixel circuit typically includes a switching transistor, a driving transistor, and a storage capacitor, i.e., a 2T1C structure (comprising two transistors and one capacitor). The pixel circuit is configured to transmit a driving current to the light-emitting element based on a data signal provided by a coupled data signal line, thereby driving the light-emitting element to emit light. Wherein, the driving current I0 = (Vgs - Vth) 2 Vgs refers to the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. However, because the threshold voltage Vth of the driving transistor is prone to drift, and the signal lines coupled to the pixel circuit have voltage drop (IR) problems, it can be seen from the driving current formula that the driving current transmitted from the pixel circuit to the light-emitting element is currently unstable, which can easily lead to poor display uniformity of the display substrate and affect the display quality.

[0071] Furthermore, for display products with higher resolutions, if each column of pixel circuits is coupled to a data signal line, the source driver circuit (Driver IC), configured to be coupled to the data signal line and provide the data signal, needs to have a larger number of channels. For example, taking an 8K display product as an example, its resolution is generally 4320*7680 pixels, that is, 4320 rows and 7680 columns of pixels. If each pixel includes 3 sub-pixels, then the display product includes a total of 7680*3=23040 columns of sub-pixels. Correspondingly, the Driver IC needs to have 23040 channels. Considering the limitations of module bonding process (e.g., small cof pitch) and cost requirements, it is desirable to reduce the number of channels required by the Driver IC, which can also be considered as reducing the number of Driver ICs.

[0072] Therefore, currently, a multiplexer (MUX) circuit is typically placed in the non-display area of ​​the display substrate, and multiple data signal lines are coupled to the same data line through this MUX circuit. This data line is then coupled to the Driver IC, so that the data signal provided by the Driver IC is transmitted to multiple data signal lines via the MUX circuit. In this way, the number of data lines that need to be coupled to the Driver IC is reduced, and correspondingly, the number of channels that need to be set on the Driver IC is reduced. However, tests have shown that due to the presence of parasitic capacitance on the data signal lines, the data signals transmitted to the pixel circuit by the multiple data signal lines sharing the same data line are different, which in turn causes different brightness of the light-emitting elements in each column, affecting the display uniformity of the display substrate.

[0073] This disclosure provides a new display substrate that can solve the problem of poor display uniformity caused by threshold voltage drift, IR voltage drop and parasitic capacitance in current display substrates while reducing the number of channels required for the Driver IC. The display substrate has better display quality.

[0074] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure. For example... Figure 1 As shown, the display substrate includes: a substrate 01 having a display area AA and a non-display area BB at least partially surrounding the display area AA. For example, Figure 1 The non-display area BB shown is located below the display area AA and is adjacent to it, that is, partially surrounding the display area AA. Of course, the non-display area BB is not limited to being located below the display area AA. For example, the non-display area BB can also be located above the display area AA, or the non-display area BB can surround the display area AA.

[0075] It should be noted that the area of ​​the display area AA is generally much larger than the area of ​​the non-display area BB. The attached diagram is for illustrative purposes only and does not limit the area of ​​the display area AA or the non-display area BB. (Continue to refer to...) Figure 1 As can be seen, the display substrate described in this embodiment further includes:

[0076] The display area AA contains multiple light-emitting elements L1 and multiple pixel circuit groups Z1. At least one pixel circuit group Z1 may include multiple pixel circuit subgroups Z11 arranged along a first direction X1, and each pixel circuit subgroup Z11 may include multiple pixel circuits O2 arranged along a second direction X2, wherein the first direction X1 and the second direction X2 may intersect. For example, Figure 1 Each pixel circuit group Z1 shown includes multiple pixel circuit subgroups Z11, and the first direction X1 and the second direction X2 are perpendicular to each other. Based on this, it can be considered that the multiple pixel circuits 02 in the display substrate are arranged in a row and column array, that is, including multiple rows and multiple columns of pixel circuits 02. The first direction X1 can refer to the row direction, and the second direction X2 can refer to the column direction.

[0077] Multiple first scan lines Scan1 and multiple data signal lines Data are located in the display area AA and the non-display area BB, and the multiple first scan lines Scan1 and multiple data signal lines Data can be coupled to multiple pixel circuit subgroups Z11 in multiple pixel circuit groups Z1.

[0078] In addition, multiple switch control lines MUX1 and multiple data lines S1 are located in the non-display area BB, and the multiple switch control lines MUX1 and multiple data lines S1 can be coupled to multiple pixel circuit subgroups Z11 in multiple pixel circuit groups Z1.

[0079] Among them, combined Figure 2 As shown in the diagram, at least one pixel circuit 02 described in this embodiment may include a data writing circuit 021 and a driving circuit 022. The data writing circuit 021 is coupled to a first scan line Scan1, a switch control line MUX1, a data signal line Data, and the driving circuit 022. The data writing circuit 021 is configured to control the switching of the data signal line Data and the driving circuit 022 in response to a first scan signal provided by the first scan line Scan1 and a switch control signal provided by the switch control line MUX1. The driving circuit 022 is also coupled to a light-emitting element L1 and is configured to drive the light-emitting element L1 to emit light based on the data signal provided by the data signal line Data. Figure 2 The coupling node between the data writing circuit 021 and the driving circuit 022 is identified as the first node P1.

[0080] For example, when the potential of the first scan signal provided by the first scan line Scan1 and the potential of the switch control signal provided by the switch control line MUX1 are both at the first potential, the data writing circuit 021 can control the data signal line Data to be connected to the driving circuit 022 (i.e., the first node P1). At this time, the data signal line Data can transmit data signals to the first node P1. The driving circuit 022 can then transmit a light-emitting driving signal (e.g., driving current) to the light-emitting element L1 based on the data signal written to the first node P1 to drive the light-emitting element L1 to emit light. Conversely, when the potential of the first scan signal and / or the potential of the switch control signal are at the second potential, the data writing circuit 021 can control the data signal line Data to be disconnected from the driving circuit 022. At this time, the data signal line Data cannot transmit data signals to the first node P1.

[0081] Optionally, in this embodiment of the disclosure, the first potential can be an effective potential, the second potential can be an ineffective potential, and the first potential can be a low potential relative to the ineffective potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential.

[0082] and combination Figure 1 and Figure 2As can be seen, in the embodiments of this disclosure, the same pixel circuit subgroup Z11 (i.e., each pixel circuit 02 located in the same column) is coupled to the same switch control line MUX1 and the same data signal line Data. Multiple pixel circuit subgroups Z11 within the same pixel circuit group Z1 (i.e., each column of pixel circuits 02 belonging to the same pixel circuit group Z1) are coupled to different switch control lines MUX1, and multiple data signal lines Data coupled to multiple pixel circuit subgroups Z11 within the same pixel circuit group Z1 are coupled to the same data line S1 and receive data signals from the data line S1. Furthermore, each pixel circuit 02 located in the same row shares a first scan line Scan1. Optionally, the data line S1 can be coupled to a Driver IC to receive data signals provided by the Driver IC.

[0083] That is, in the embodiments of this disclosure, different pixel circuits 02 can share the same data line S1 through their included data writing circuits 021, which can be considered as integrating the MUX circuit into each pixel circuit 02. Furthermore, a pixel circuit group Z1, which includes multiple columns of pixel circuits 02 (i.e., multiple pixel circuit subgroups Z11), is coupled to a data line S1. The number of data lines S1 in the display substrate can be equal to the number of pixel circuit groups Z1, and less than the number of data signal lines Data. This not only ensures that the number of channels required for the Driver IC can be reduced, but also avoids differences in data signals transmitted to each column of pixel circuits 02 via the same data line S1 due to parasitic capacitance on the data signal lines Data. Therefore, the display uniformity of the display substrate provided in the embodiments of this disclosure can be better.

[0084] In summary, the present disclosure provides a display substrate. In this display substrate, each pixel circuit includes a data writing circuit that is coupled to a first scan line, a switch control line, a data signal line, and a driving circuit, respectively. Based on a first scan signal provided by the first scan line and a switch control signal provided by the switch control line, the data signal provided by the data signal line is transmitted to the driving circuit, causing the driving circuit to drive the coupled light-emitting element to emit light. Within the same pixel circuit group, each pixel circuit subgroup is coupled to different switch control lines, and multiple data signal lines coupled to each pixel circuit subgroup are coupled to the same data line to receive data signals from that data line. Thus, each pixel circuit can receive data signals from the data line to its coupled data signal line under the control of its coupled switch control line. Consequently, the data signal received by each pixel circuit from the shared data line has good uniformity, the brightness of each light-emitting element is relatively uniform, and the display uniformity of the display substrate is good.

[0085] Optionally, in this embodiment of the disclosure, multiple switch control lines MUX1 can be configured to provide switch control signals to the data writing circuit 021 of different pixel circuit subgroups Z1 at different time periods. Providing switch control signals here can refer to switch control signals that provide effective potentials.

[0086] In other words, during the same time period, when one switch control line MUX1 provides a valid switch control signal, all other switch control lines MUX1 provide invalid switch control signals. Thus, for each pixel circuit group Z1, within each pixel circuit subgroup Z11 (i.e., each column of pixel circuits 02), the data writing circuit 021 can sequentially transmit the data signal provided by the shared data line S1 to the coupled driving circuit 022 in a time-division manner. That is, each column of light-emitting elements L1 can emit light sequentially, ensuring a better display effect on the display substrate.

[0087] Optional, Figure 3 This is a schematic diagram of another display substrate provided in an embodiment of this disclosure. (Combined with...) Figure 1 and Figure 3 As can be seen, in the embodiments of this disclosure, each pixel circuit group Z1 includes individual pixel circuit subgroups Z11 that can be adjacent, meaning that multiple columns of pixel circuits 02 belonging to the same pixel circuit group Z1 can be adjacent. Thus, it can be considered that each adjacent column of pixel circuits 02 (e.g., the first column of pixel circuits 02, the second column of pixel circuits 02, and the third column of pixel circuits 02) shares a single data line S1. This arrangement facilitates wiring, simplifies the structure, and saves costs.

[0088] Of course, in some other embodiments, reference Figure 4 As can be seen from another type of display substrate, multiple non-adjacent pixel circuits 02 (e.g., the first, third, and fifth pixel circuits 02) belong to a pixel circuit group Z1 and share the same data line S1.

[0089] Optionally, in this embodiment of the disclosure, the number of pixel circuit subgroups Z11 included in each pixel circuit group Z1 can be greater than or equal to 2 and less than or equal to 5. That is, each pixel circuit group Z1 can include two to five columns of pixel circuits O2.

[0090] For example, refer to Figure 3 and Figure 4As can be seen, each pixel circuit group Z1 shown may include three pixel circuit subgroups Z11, i.e., three columns of pixel circuits 02. Based on this, it can be considered that every three columns of pixel circuits 02 share a single data line S1, and that every three adjacent columns of pixel circuits 02 share a single data line S1. That is, a 1:3 MUX circuit architecture is adopted (which can be understood as: every three columns of pixel circuits 02 are coupled to one data line S1 via three data signal lines Data). Of course, in some other embodiments, each pixel circuit group Z1 may also include more columns of pixel circuits 02, such as six columns.

[0091] Optionally, in the different pixel circuit groups Z1 described in the embodiments of this disclosure, at least two pixel circuit subgroups Z11 can share one of the multiple switch control lines MUX1.

[0092] For example, still refer to Figure 3 and Figure 4 It can be seen that in the multiple pixel circuit groups Z1 included in the display substrate, the multiple pixel circuit subgroups Z11 included in each pixel circuit group Z1 can share the multiple switch control lines MUX1 included in the display substrate. For example, based on the fact that the three pixel circuit subgroups Z11 included in each pixel circuit group Z1 (i.e., every three columns of pixel circuits 02) share one data line S1, the display substrate can include a total of three switch control lines MUX1. Figure 3 and Figure 4 To distinguish the three switch control lines MUX1, they are labeled MUX11, MUX12, and MUX13 respectively. These three switch control lines MUX11, MUX12, and MUX13 can provide switch control signals at different times. This further simplifies wiring, saves costs, and facilitates the narrow bezel design of the display device.

[0093] Optional, combined Figure 1 , Figure 3 and Figure 4 As can be seen, in the display substrate described in the embodiments of this disclosure, the display area AA and the non-display area BB of the substrate 01 can be arranged along the first direction X1.

[0094] Multiple switch control lines MUX1 and multiple first scan lines Scan1 can extend along the first direction X1.

[0095] Multiple data signal lines Data and multiple data lines S1 can extend along the second direction X2.

[0096] Furthermore, each data signal line Data may include a first segment D11 located in the non-display area BB and a second segment D12 located in the display area AA. The first segment D11 is coupled to both data line S1 and the second segment D12, and the second segment D12 is also coupled to pixel circuit O2. That is, the second segment D12 coupled to pixel circuit O2 can be indirectly coupled to data line S1 through the first segment D11 located in the non-display area BB. Therefore, the first segment D11 can also be referred to as a data line lead.

[0097] In addition, from Figure 3 and Figure 4 As can be seen, due to the different extension directions of the signal lines, the first segment D11 and the switch control line MUX1 of the data signal line Data will inevitably overlap. Therefore, to avoid signal crosstalk between them, the first segment D11 and the switch control line MUX1 can be located on different layers, that is, they can be made of metals located on different layers.

[0098] Figure 5 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. (See reference) Figure 5 As can be seen, the data writing circuit 021 may include: a data writing sub-circuit 0211 and a switching sub-circuit 0212.

[0099] The data writing sub-circuit 0211 can be coupled to the first scan line Scan1, the data signal line Data, and the switch sub-circuit 0212 respectively. The data writing sub-circuit 0211 can be configured to control the on / off state of the data signal line Data and the switch sub-circuit 0212 in response to the first scan signal.

[0100] For example, the data writing sub-circuit 0211 can control the data signal line Data to be connected to the switch sub-circuit 0212 when the potential of the first scan signal is at the first potential. At this time, the data signal received by the data signal line Data from the data line S1 can be transmitted to the switch sub-circuit 0212. Conversely, the data writing sub-circuit 0211 can control the data signal line Data to be disconnected from the switch sub-circuit 0212 when the potential of the first scan signal is at the second potential. At this time, the data signal cannot be transmitted to the switch sub-circuit 0212.

[0101] The switch sub-circuit 0212 can also be connected to the switch control line MUX1 and the drive circuit 022 (i.e., Figure 5 The first node P1 shown is coupled to the switch sub-circuit 0212, which can be configured to control data writing to the on / off state of the sub-circuit 0211 and the drive circuit 022 in response to a switch control signal.

[0102] For example, when the switch control signal is at a first potential, the switch sub-circuit 0212 can control the data writing sub-circuit 0211 and the drive circuit 022 to conduct. At this time, the data signal transmitted from the data writing sub-circuit 0211 to the switch sub-circuit 0212 can be further transmitted to the drive circuit 022. Conversely, when the switch control signal is at a second potential, the switch sub-circuit 0212 can control the data writing sub-circuit 0211 and the drive circuit 022 to disconnect. At this time, the data signal cannot be further transmitted to the drive circuit 022.

[0103] Of course, in some embodiments, the data writing sub-circuit 0211 and the switching sub-circuit 0212 can also satisfy other coupling methods. For example, the switching sub-circuit 0212 is coupled to the first scan line Scan1, the data signal line Data, and the data writing sub-circuit 0211, respectively. The data writing sub-circuit 0211 is then coupled to the switch control line MUX1 and the drive circuit 022, respectively. Alternatively, the switching sub-circuit 0212 is coupled to the first scan line Scan1, the switch control line MUX1, and the data writing sub-circuit 0211, respectively, and transmits a first scan signal to the data writing sub-circuit 0211 in response to the switch control signal. The data writing sub-circuit 0211 is then coupled to the data signal line Data and the drive circuit 022, and transmits a data signal to the drive circuit 022 in response to the first scan signal. The embodiments of this disclosure do not limit the coupling method and control principle of the data writing sub-circuit 0211 and the switching sub-circuit 0212.

[0104] Figure 6 This is a schematic diagram of another pixel circuit provided in an embodiment of this disclosure. (Combined with...) Figure 1 and Figure 6 It is understood that the display substrate may further include: multiple first light-emitting control lines EM1, multiple second light-emitting control lines EM2, multiple second scan lines Scan2, multiple initialization signal lines Vinit, and multiple first power supply lines ELVDD located in the display area AA and the non-display area BB. The multiple first light-emitting control lines EM1, multiple second light-emitting control lines EM2, multiple second scan lines Scan2, multiple initialization signal lines Vinit, and multiple first power supply lines ELVDD can be coupled to multiple pixel circuit subgroups Z11 in multiple pixel circuit groups Z1. Furthermore, the driving circuit 022 may include: an initialization circuit 0221 and a light-emitting driving circuit 0222.

[0105] The initialization circuit 0221 can be coupled to the second scan line Scan2, the initialization signal line Vinit, the light-emitting driving circuit 0222, and the first pole of the light-emitting element L1, respectively. The initialization circuit 0221 can be configured to control the on / off state of the initialization signal line Vinit with the light-emitting driving circuit 0222 and the first pole of the light-emitting element L1 in response to the second scan signal provided by the second scan line Scan2. Figure 6 The coupling node between the initialization circuit 0221 and the light-emitting driving circuit 0222 is designated as the third node P3, and the coupling node between the initialization circuit 0221 and the first pole of the light-emitting element L1 is designated as the fifth node P5.

[0106] For example, initialization circuit 0221 can control the initialization signal line Vinit to be connected to both the third node P3 and the fifth node P5 when the potential of the second scan signal provided by the second scan line Scan2 is at the first potential. At this time, the initialization signal line Vinit can transmit initialization signals to the third node P3 and the fifth node P5 respectively to reset the third node P3 and the fifth node P5. Alternatively, initialization circuit 0221 can control the initialization signal line Vinit to be disconnected from both the third node P3 and the fifth node P5 when the potential of the second scan signal is at the second potential. At this time, the initialization signal line Vinit cannot transmit initialization signals to the third node P3 and the fifth node P5.

[0107] The light-emitting driving circuit 0222 is also coupled to the data writing circuit 021 (i.e., the first node P1), the first power line ELVDD, the first light-emitting control line EM1, the second light-emitting control line EM2, and the first electrode of the light-emitting element L1 (i.e., the fifth node P5). The light-emitting driving circuit 0222 can be configured to transmit a light-emitting driving signal (e.g., driving current) to the first electrode of the light-emitting element L1 in response to the data signal provided by the data writing circuit 021, the first light-emitting control signal provided by the first light-emitting control line EM1, the second light-emitting control signal provided by the second light-emitting control line EM2, and the first power signal provided by the first power line ELVDD.

[0108] The second electrode of the light-emitting element L1 can be configured to be coupled to the second power line ELVSS. The light-emitting element L1 can be configured to emit light based on the light-emitting driving signal transmitted by the light-emitting driving circuit 0222 and the second power signal provided by the second power line ELVSS. For example, the light-emitting element L1 can emit light under the voltage difference between the light-emitting driving signal and the second power signal. Based on this, it can also be determined that, in addition to the above-mentioned signal lines, the display substrate may also include a second power line ELVSS for the second electrode of the light-emitting element L1 to be connected.

[0109] Optional, combined Figure 6The first electrode of the light-emitting element L1 can be an anode, and correspondingly, the second electrode of the light-emitting element L1 can be a cathode. Alternatively, in some other embodiments, the first electrode of the light-emitting element L1 can also be a cathode, and correspondingly, the second electrode of the light-emitting element L1 can be an anode.

[0110] Optionally, in this embodiment of the disclosure, the potential of the first power signal can be greater than the potential of the second power signal. For example, the potential of the first power signal can be a positive potential (i.e., greater than 0), the potential of the second power signal can be a negative potential (i.e., less than 0), and the potential of the initialization signal can be a negative potential.

[0111] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 7 As shown, the light-emitting driving circuit 0222 may include: a storage sub-circuit 02221, a light-emitting control sub-circuit 02222, and a driving sub-circuit 02223.

[0112] Among them, the storage sub-circuit 02221 is coupled to the data writing circuit 021 and the light emission control sub-circuit 02222 respectively, and the storage sub-circuit 02221 can be configured to adjust the potential at the coupling point. Figure 7 The coupling node between the storage sub-circuit 02221 and the data writing circuit 021 is designated as the first node P1, and the coupling node between the storage sub-circuit 02221 and the light-emitting control sub-circuit 02222 is designated as the second node P2. That is, in this embodiment of the present disclosure, the storage sub-circuit 02221 can be configured to adjust the potential of the first node P1 and the potential of the second node P2.

[0113] The light-emitting control sub-circuit 02222 can also be coupled to the first light-emitting control line EM1, the second light-emitting control line EM2, the first power line ELVDD, the data writing circuit 021 and the driver sub-circuit 02223 respectively. The light-emitting control sub-circuit 02222 can be configured to control the on / off state of the first power line ELVDD and the driver sub-circuit 02223 in response to the first light-emitting control signal and the second light-emitting control signal. Figure 7 The coupling node between the light-emitting control sub-circuit 02222 and the data writing circuit 021 is designated as the first node P1, and the coupling nodes between the light-emitting control sub-circuit 02222 and the driving sub-circuit 02223 are designated as the third node P3 and the fourth node P4, respectively. Considering the coupling method of the initialization circuit 0221 in the above embodiment, it can be seen that the light-emitting control sub-circuit 02222 can also be coupled to the initialization circuit 0221 through the third node P3.

[0114] For example, the light-emitting control sub-circuit 02222 can control the first power line ELVDD to conduct with the second node P2, and control the first node P1 and the third node P3 to conduct when the potential of the first light-emitting control signal is at the first potential. At this time, the first power line ELVDD can transmit the first power signal to the second node P2, and the potentials of the first node P1 and the third node P3 can influence each other; for example, the potential of the first node P1 can be transmitted to the third node P3. Conversely, when the potential of the first light-emitting control signal is at the second potential, the light-emitting control sub-circuit 02222 can control the first power line ELVDD to decouple from the second node P2, and control the first node P1 and the third node P3 to decouple. At this time, the first power line ELVDD cannot transmit the first power signal to the second node P2, and the potentials of the first node P1 and the third node P3 are independent of each other; for example, the potential of the first node P1 cannot be transmitted to the third node P3.

[0115] Similarly, the light-emitting control sub-circuit 02222 can control the second node P2 and the fourth node P4 to conduct when the potential of the second light-emitting control signal is the first potential. At this time, the potentials of the second node P2 and the fourth node P4 can influence each other. For example, the potential of the second node P2 can be transmitted to the fourth node P4. Conversely, the light-emitting control sub-circuit 02222 can also control the second node P2 and the fourth node P4 to disconnect when the potential of the second light-emitting control signal is the second potential. At this time, the potentials of the second node P2 and the fourth node P4 are independent of each other. For example, the potential of the second node P2 cannot be transmitted to the fourth node P4.

[0116] The driving sub-circuit 02223 can also be coupled to the first electrode (i.e., the fifth node P5) of the light-emitting element L1. The driving sub-circuit 02223 can be configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element L1 in response to a signal provided by the light-emitting control sub-circuit 02222. That is, refer to... Figure 7 The driver sub-circuit 02223 can transmit the light-emitting driving signal to the fifth node P5 based on the potential of the third node P3 and the potential of the fourth node P4.

[0117] Figure 8 This is a schematic diagram of another pixel circuit structure provided in an embodiment of this disclosure. For example... Figure 8As shown, the data writing sub-circuit 0211 may include: a data writing transistor T1. The switching sub-circuit 0212 may include: a switching transistor T2. The light emission control sub-circuit 02222 may include: a first light emission control transistor T3, a second light emission control transistor T4, and a third light emission control transistor T5. The initialization circuit 0221 may include: a first initialization transistor T6 and a second initialization transistor T7. The driving sub-circuit 02223 may include: a driving transistor T8. The storage sub-circuit 02221 may include: a storage capacitor C1.

[0118] Specifically, the gate of the data writing transistor T1 can be coupled to the first scan line Scan1, the first terminal of the data writing transistor T1 can be coupled to the data signal line Data, and the second terminal of the data writing transistor T1 can be coupled to the switch sub-circuit 0212.

[0119] The gate of switching transistor T2 can be coupled to the switching control line MUX1, the first terminal of switching transistor T2 can be coupled to the data writing circuit 0211, and the second terminal of switching transistor T2 can be coupled to the driving circuit 022 (i.e., Figure 8 The first node P1 shown is coupled.

[0120] In other words, reference Figure 8 The coupling of the second terminal of the data writing transistor T1 to the switching sub-circuit 0212 and the coupling of the first terminal of the switching transistor T2 to the data writing circuit 0211 can mean that the first terminal of the switching transistor T2 is coupled to the second terminal of the data writing transistor T1.

[0121] The gate of the first light-emitting control transistor T3 can be coupled to the first light-emitting control line EM1, the first terminal of the first light-emitting control transistor T3 can be coupled to the first power supply line ELVDD, and the second terminal of the first light-emitting control transistor T3 can be coupled to the first terminal of the third light-emitting control transistor T3 (i.e., Figure 8 The second node P2 shown is coupled.

[0122] The gate of the second light-emitting control transistor T4 can be coupled to the first light-emitting control line EM1, and the first terminal of the second light-emitting control transistor T4 can be coupled to the data writing circuit 021 (i.e., Figure 8 The first node P1 shown is coupled to the second terminal of the second light-emitting control transistor T4, which can be connected to the driving sub-circuit 02223 and the initialization circuit 0221 (i.e., Figure 8 The third node P3 shown is coupled.

[0123] The gate of the third light-emitting control transistor T5 can be coupled to the second light-emitting control line EM2, and the second terminal of the third light-emitting control transistor T5 can be coupled to the driving sub-circuit 02223 (i.e., Figure 8The fourth node P4 shown is coupled.

[0124] The gates of both the first initialization transistor T6 and the second initialization transistor T7 can be coupled to the second scan line Scan2. The first terminals of both the first and second initialization transistors T6 and T7 can be coupled to the initialization signal line Vinit. The second terminal of the first initialization transistor T6 can be coupled to the light-emitting driving circuit 0222 (i.e., Figure 8 The third node P3 shown is coupled to the second initialization transistor T7. The second terminal of the second initialization transistor T7 can be coupled to the first terminal of the light-emitting element L1 (i.e., Figure 8 The fifth node P5 shown is coupled.

[0125] The first terminal of the storage capacitor C1 can be connected to the data writing circuit 021 (i.e., Figure 8 The first node P1 shown is coupled to the second terminal of the storage capacitor C1, which can be connected to the light-emitting control sub-circuit 02222 (i.e., Figure 8 The second node P2 shown is coupled.

[0126] The gate of the driving transistor T8 can be connected to the light-emitting control sub-circuit 02222 and the initialization circuit 0221, respectively (i.e., Figure 8 The third node P3 shown is coupled to the first terminal of the driving transistor T8, which can be connected to the light-emitting control sub-circuit 02222 (i.e., Figure 8 The fourth node P4 shown is coupled to the second terminal of the driving transistor T8, which can be connected to the first terminal of the light-emitting element L1 (i.e., Figure 8 The fifth node P5 shown is coupled.

[0127] It should be noted that, under the premise of satisfying the above functions, the pixel circuit 02 described in this embodiment can, in addition to being able to, provide... Figure 8 Besides the 8T1C structure shown (i.e., including 8 transistors and 1 capacitor), other structures are also possible. For example, a 6T1C structure can be used. This 6T1C structure includes at least: Figure 8 The data shown is written to transistor T1 and switching transistor T2.

[0128] It should also be noted that in the pixel circuit 02 described in this embodiment, each transistor can be a P-type transistor. Correspondingly, as described in the above embodiment, the first potential can be a lower potential relative to the second potential. Of course, in some other embodiments, each transistor can also be an N-type transistor, and correspondingly, the first potential can be a higher potential relative to the second potential. Alternatively, each pixel circuit can include both N-type and P-type transistors. Furthermore, the material of the N-type transistor can be an oxide material, and the material of the P-type transistor is low-temperature polycrystalline silicon (LTPS). A display panel including both N-type and P-type transistors can be called a low-temperature polycrystalline oxide (LTPO) display panel. Here, the material of the transistor generally refers to the material of the active layer in the transistor.

[0129] by Figure 3 and Figure 8 Taking the structure shown as an example, Figure 9 This illustrates the structure of yet another display substrate. Figure 9 The diagram shows a data writing transistor T1 and a switching transistor T2, with "rectangular blocks" representing other structures in each pixel circuit 02 besides the data writing transistor T1 and the switching transistor T2. The switching transistor T2 can be considered as the MUX circuit portion integrated into the pixel circuit 02.

[0130] by Figure 3 and Figure 8 Taking the structure shown, and all transistors in the pixel circuit being P-type transistors, with the first potential being lower than the second potential as an example, the driving principle of the pixel circuit in this embodiment is described as follows. Figure 10 This is a timing diagram of each signal terminal in a pixel circuit provided in an embodiment of this disclosure. For example... Figure 10 As shown, the entire process can include: initialization phase t1, data writing phase t2, and light emission phase t3.

[0131] During initialization phase t1, the potentials of the first scan signal provided by the first scan line Scan1, the switch control signal provided by the switch control line MUX1, and the second light emission control signal provided by the second light emission control line EM2 are all at the second potential (i.e., high potential). The potentials of the second scan signal provided by the second scan line Scan2 and the first light emission control signal provided by the first light emission control line EM1 are both at the first potential (i.e., low potential). Consequently, the data writing transistor T1, the switch transistor T2, and the third light emission control transistor T5 are all turned off, while the first initialization transistor T6, the second initialization transistor T7, the first light emission control transistor T3, and the second light emission control transistor T4 are all turned on. Correspondingly, the initialization signal provided by the initialization signal line Vinit can be transmitted to the third node P3 via the first initialization transistor T6, and to the first electrode of the light-emitting element L1 via the second initialization transistor T7, thereby initializing (i.e., resetting) the third node P3 and the first electrode of the light-emitting element L1. Since the third node P3 is coupled to the gate of the driving transistor T8, this also resets the gate of the driving transistor T8, turning it on. Reset can also be called voltage reset. The first power signal provided by the first power line ELVDD can be transmitted to the second node P2 via the first light-emitting control transistor T3. And the initialization signal transmitted to the third node P3 can be transmitted to the first node P1 via the second light-emitting control transistor T4.

[0132] In this context, the initialization signal can have a low potential, and the first power supply signal can have a high potential. Assume the initialization signal potential is Vinit0, and the first power supply signal potential is Elvdd. Then, referring to Table 1 below, during the initialization phase t1, the potentials Vp1 of the first node P1, Vp3 of the third node P3, and Vp5 of the fifth node P5 are all Vinit0. The potential Vp2 of the second node P2 is Elvdd.

[0133] Table 1

[0134] t1 stage Vinit0 Elvdd Vinit0 Vinit0

[0135] Taking the pixel circuit 02 coupled to MUX11 as an example, during the data writing stage t2, the potentials of the first scan signal provided by the first scan line Scan1, the second scan signal provided by the second scan line Scan2, the second light emission control signal provided by the second light emission control line EM2, and the switch control signal provided by the switch control line MUX11 are all the first potential. Only the potential of the first light emission control signal provided by the first light emission control line EM1 is the second potential. Therefore, the data writing transistor T1, the switch transistor T2, the third light emission control transistor T5, the first initialization transistor T6, and the second initialization transistor T7 are all turned on, while the first light emission control transistor T3 and the second light emission control transistor T4 are both turned off. Correspondingly, the data signal provided by the data signal line Data can be transmitted to the first node P1 via the data writing transistor T1 and the switch transistor T2. The initialization signal provided by the initialization signal line Vinit can be transmitted to the third node P3 via the first initialization transistor T6, and can be transmitted to the first electrode of the light-emitting element L1 via the second initialization transistor T7. The potential of the second node P2 can be transmitted to the fourth node P4 via the third light-emitting control transistor T5, meaning that the potential of the fourth node P4 is the same as the potential of the second node P2 at this time.

[0136] In the data writing phase t2, the potential Vp2 of the second node P2 initially remains at the potential of the initialization phase t1 (i.e., Elvdd). Since the voltage difference between the first and second terminals of the storage capacitor C1 cannot change abruptly, when the first node P1 changes from an initialization signal to a data signal, the potential Vp2 of the second node P2 first changes to Elvdd - Vinit0 + Vdata, where Vdata can refer to the potential of the data signal. Correspondingly, it can be determined that the potential Vp4 of the fourth node P4 is also Elvdd - Vinit0 + Vdata. Because the third node P3 is coupled to the gate (g) of the driving transistor T8, and the fourth node P4 is coupled to the source (s) of the driving transistor T8, it can be determined that in the data writing phase t2, the gate-source voltage difference Vgs of the driving transistor T8 can satisfy:

[0137] Vgs=Vg-Vs=Vp3-Vp4=Vinit0-(Elvdd-Vinit0+Vdata) formula (1);

[0138] Since Vinit0 is a low potential, Elvdd and Vdata are generally high potentials. Therefore, based on the above formula (1), the gate-source voltage difference Vgs of the driving transistor T8 should be a low potential, and generally less than the threshold voltage Vth of the driving transistor T8. Since Vth is generally a low potential less than 0 for P-type transistors, it can be determined that during the data writing stage t2, the driving transistor T8 can remain on until the potential Vp2 of the second node P2 is continuously discharged to Vinit0-Vth, at which point the driving transistor T8 is turned off.

[0139] For example, in conjunction with the above embodiments, Table 2 shows the potentials Vp1 of the first node P1, Vp2 of the second node P2, Vp3 of the third node P3, and Vp5 of the first electrode of the light-emitting element L1 during the data writing stage t2. Referring to Table 2 below, it can be seen that during the data writing stage t2, the potential Vp1 of the first node P1 is Vdata, the potential Vp2 of the second node P2 is Vinit0-Vth, and the potentials Vp3 of the third node P3 and Vp5 of the fifth node P5 are both Vinit0.

[0140] Table 2

[0141] t2 stage Vdata Vinit0-Vth Vinit0 Vinit0

[0142] It should be noted that, Figure 10 The data writing stage t2 of pixel circuit 02 coupled to switch control line MUX11 is designated as t2-1, the data writing stage t2 of pixel circuit 02 coupled to switch control line MUX12 is designated as t2-2, and the data writing stage t2 of pixel circuit 02 coupled to switch control line MUX13 is designated as t2-3. (Reference) Figure 10It can be further observed that in stage t2-1, switch control line MUX11 provides a switch control signal at the first potential, while switch control lines MUX12 and MUX13 both provide switch control signals at the second potential. In stage t2-2, switch control line MUX12 provides a switch control signal at the first potential, while switch control lines MUX11 and MUX13 both provide switch control signals at the second potential. In stage t2-3, switch control line MUX13 provides a switch control signal at the first potential, while switch control lines MUX11 and MUX12 both provide switch control signals at the second potential. That is, from stage t2-1 to stage t2-3, switch control lines MUX11, MUX12, and MUX13 provide switch control signals at effective potentials sequentially in a time-division manner. In this way, the data signal provided by one data line S1 can be transmitted in a time-division manner to the driving circuit 022 included in each pixel circuit 02 via the data signal line Data coupled to the three pixel circuits 02, ensuring that the three light-emitting elements L1 coupled to the three pixel circuits 02 emit light sequentially, rather than simultaneously.

[0143] During the light-emitting stage (also known as the display stage) t3, the potentials of the first scan signal provided by the first scan line Scan1, the second scan signal provided by the second scan line Scan2, and the switch control signal provided by the switch control line MUX1 are all the second potential. The potentials of the first light-emitting control signal provided by the first light-emitting control line EM1 and the second light-emitting control signal provided by the second light-emitting control line EM2 are all the first potential. Consequently, the data writing transistor T1, the switch transistor T2, the first initialization transistor T6, and the second initialization transistor T7 are all turned off, while the first light-emitting control transistor T3, the second light-emitting control transistor T4, and the third light-emitting control transistor T5 are all turned on. Correspondingly, the first power supply signal can be transmitted to the second node P2 via the first light-emitting control transistor T3, meaning the potential Vp2 of the second node P2 is Elvdd. Because the voltage difference between the first and second terminals of the storage capacitor C1 cannot change abruptly, the potential Vp1 of the first node P1 at this time is Vdata - Vinit0 + Vth + Elvdd. The potential Vp1 of the first node P1 is transmitted to the third node P3 via the second light-emitting control transistor T4. The potential Vp3 of the third node P3 is the same as the potential Vp1 of the first node P1, which is Vdata - Vinit0 + Vth + Elvdd. Similarly, the potential Vp2 of the second node P2 is transmitted to the fourth node P4 via the third light-emitting control transistor T5. The potential Vp4 of the fourth node P4 is the same as the potential Vp2 of the second node P2, which is also Elvdd.

[0144] Since the third node P3 is coupled to the gate (g) of the driving transistor T8, and the fourth node P4 is coupled to the source (s) of the driving transistor T8, it can be determined that during the light-emitting stage t3, the gate-source voltage difference Vgs of the driving transistor T8 can satisfy:

[0145] Vgs = Vg - Vs = Vp3 - Vp4

[0146] =Vdata-Vinit0+Vth+Elvdd-Elvdd=Vdata-Vinit0+Vth formula (2)

[0147] As can be seen from formula (2), at this time, the gate-source voltage difference Vgs of the driving transistor T8 is greater than the threshold voltage Vth of the driving transistor T8. Accordingly, the driving transistor T8 is turned on, and the driving transistor T8 can transmit driving current to the first electrode of the light-emitting element L1 based on the potential Vp3 of the third node P3 and the potential Vp4 of the fourth node P4, so as to drive the light-emitting element L1 to emit light.

[0148] For example, in conjunction with the above embodiments, Table 3 shows the potentials Vp1 of the first node P1, Vp2 of the second node P2, and Vp3 of the third node P3 during the light emission stage t3. Referring to Table 3 below, it can be seen that during the light emission stage t3, the potentials Vp1 of the first node P1 and Vp3 of the third node P3 are both: Vdata - Vinit0 + Vth + Elvdd, and the potential Vp2 of the second node P2 is: Elvdd.

[0149] Table 3

[0150] t3 stage Vdata-Vinit0+Vth+Elvdd Elvdd Vdata-Vinit0+Vth+Elvdd

[0151] Based on the driving current formula: I0=k*(Vgs-Vth) 2 It can be seen that, in this embodiment of the present disclosure, the drive current I0 generated by the drive transistor T8 can satisfy:

[0152] I0=k*[(Vdata-Vinit0+Vth)-Vth] 2 = k*(Vdata-Vinit0) 2 Formula (3);

[0153] Where k = 1 / 2 * Cox * μW / L, Cox refers to the channel capacitance per unit area of ​​the driving transistor T8, W / L refers to the aspect ratio of the driving transistor T8, and μ refers to the channel mobility of the driving transistor T8. Therefore, k is determined by the characteristics of the driving transistor T8 itself. Consequently, it can be determined that the magnitude of the driving current I0 generated by the driving transistor T8 is only related to the data signal provided by the data signal line Data and the initialization signal provided by the initialization signal line Vinit, and is independent of the threshold voltage Vth of the driving transistor T8. Correspondingly, the driving current transmitted to the light-emitting element L1 will not be affected by the drift of the threshold voltage Vth of the driving transistor T8. Furthermore, since the initialization signal line Vinit only initializes the reference power supply and does not need to generate the light-emitting current driving the light-emitting element L1, the current through the signal line coupled to the initialization signal line Vinit (i.e., the Vinit line) is essentially zero, and the voltage drop (IR) on the Vinit line is small, having almost no effect on the driving current. Therefore, the pixel circuit provided in this embodiment compensates for both the threshold voltage Vth and the IR voltage drop, effectively improving the display unevenness caused by threshold voltage Vth drift or IR voltage drop. The data writing stage t2 can also be called the data writing compensation stage.

[0154] Furthermore, taking a 1:3 MUX circuit architecture as an example, Figure 11 A schematic diagram of a display substrate in the related art is shown. (Reference) Figure 11 As can be seen, in the display area AA, each pixel circuit 02 only includes a data writing transistor T1 coupled to the data signal line Data and the first scan line Scan1. Switching transistors T2 are then set in the non-display area BB. Each switching transistor T2 is coupled to a switching control line MUX1, a data line S1, and a data signal line Data, and in response to the switching control signal, transmits the data signal from the data line S1 to the data signal line Data. Multiple switching transistors T2 (e.g., three switching transistors T2) share the same data line S1. However, from... Figure 11 It can be seen that parasitic capacitance C0 is unavoidable on each data signal line Data. This parasitic capacitance C0 will cause the potential of the data signal transmitted to each data signal line Data that shares the same data line S1 when each data line S1 works in conjunction with the switching transistor T2.

[0155] For example, with Figure 11 The three data signal lines Data1, Data2, and Data3 shown are coupled to one data line S1 via three switching transistors T2, and the three switching transistors T2 are respectively coupled to three switching control lines MUX11, MUX12, and MUX13. Taking this example, combined with... Figure 10As shown in the timing diagram, after the transition from stage t2-1 to stage t2-2, i.e., within stage t2-2, due to the presence of parasitic capacitance C0, even if the switch control line MUX11 provides an invalid switch control signal, the data signal stored on parasitic capacitance C0 will still be transmitted to the pixel circuit 02 coupled to it via data signal line Data1. That is, while writing a data signal to the pixel circuit 02 coupled to data signal line Data2, a data signal is also mistakenly written to the pixel circuit 02 coupled to data signal line Data1. Furthermore, after the transition from stage t2-2 to stage t2-3, i.e., within stage t2-3, due to the presence of parasitic capacitance C0, even if both switch control lines MUX11 and MUX12 provide invalid switch control signals, the data signal stored on parasitic capacitance C0 will still be transmitted to the pixel circuit 02 coupled to it via data signal line Data1, and also to the pixel circuit 02 coupled to it via data signal line Data2. That is, while writing data signals to the pixel circuit 02 coupled to data signal line Data3, data signals are also mistakenly written to the pixel circuit 02 coupled to data signal line Data1 and the pixel circuit 02 coupled to data signal line Data2. Furthermore, it can be seen that the transmission time of data signals via one data line S1 to the three data signal lines Data1, Data2, and Data3 sharing the same data line S1 is different, meaning the charging time of the pixel circuits 02 coupled to the three data signal lines Data1, Data2, and Data3 is different. Correspondingly, the light-emitting elements L1 coupled to each pixel circuit 02 have different brightness, resulting in poor display uniformity on the display substrate.

[0156] Combined Figure 10 It is understood that when using the display substrate provided in this embodiment, since the switching transistor T2 is integrated into each pixel circuit 02, the influence of the parasitic capacitance C0 on the data signal line Data on the charging time of each pixel circuit 02 is avoided. That is, the charging time of each pixel circuit 02 sharing a data line S1 can be the same. For example, taking stage t2-2 as an example, combined with... Figure 8 and Figure 9 It can be seen that although the parasitic capacitance C0 still exists on the data signal line Data, because the switch control signal provided by the switch control line MUX11 jumps to an invalid potential, the switching transistor T2 included in the data writing circuit 021 coupled to the switch control line MUX11 in the pixel circuit 02 is reliably in the off state, and the data signal stored in the parasitic capacitance C0 cannot be transmitted to the first node P1. The same applies to stages t2-3, which will not be elaborated here.

[0157] Therefore, this embodiment of the present disclosure, while simultaneously compensating for the threshold voltage Vth and IR voltage drop, also effectively improves the display unevenness problem caused by the MUX circuit in related technologies. The display substrate provided by this embodiment of the present disclosure has better display uniformity and higher display quality.

[0158] In summary, the present disclosure provides a display substrate. In this display substrate, each pixel circuit includes a data writing circuit that is coupled to a first scan line, a switch control line, a data signal line, and a driving circuit, respectively. Based on a first scan signal provided by the first scan line and a switch control signal provided by the switch control line, the data signal provided by the data signal line is transmitted to the driving circuit, causing the driving circuit to drive the coupled light-emitting element to emit light. Within the same pixel circuit group, each pixel circuit subgroup is coupled to different switch control lines, and multiple data signal lines coupled to each pixel circuit subgroup are coupled to the same data line to receive data signals from that data line. Thus, each pixel circuit can receive data signals from the data line to its coupled data signal line under the control of its coupled switch control line. Consequently, the data signal received by each pixel circuit from the shared data line has good uniformity, the brightness of each light-emitting element is relatively uniform, and the display uniformity of the display substrate is good.

[0159] Figure 12 This is a flowchart of a driving method for a display substrate provided in this disclosure embodiment, which can be used to drive such... Figure 1 , Figure 3 , Figure 4 and Figure 9 Any of the display substrates shown. For example... Figure 12 As shown, the method includes:

[0160] Step 1201: Multiple switch control lines provide switch control signals at different time periods, and multiple first scan lines provide first scan signals at different time periods. The data writing circuits in the multiple pixel circuits included in different pixel circuit subgroups respond to the first scan signal and the switch control signal in a time-division manner, controlling the data signal lines to be connected to the drive circuit so that the data signal lines transmit the data signals from the data lines to the drive circuit.

[0161] This disclosure provides a pixel circuit. Optionally, refer to... Figure 2 The pixel circuit 02 may include a data writing circuit 021 and a driving circuit 022.

[0162] The data writing circuit 021 can be coupled to the first scan line Scan1, the switch control line MUX1, the data signal line Data, and the drive circuit 022. The data writing circuit 021 can be configured to control the switching of the data signal line Data and the drive circuit 022 in response to the first scan signal provided by the first scan line Scan1 and the switch control signal provided by the switch control line MUX1.

[0163] The driving circuit 022 can also be coupled to the light-emitting element L1. The driving circuit 022 can be configured to drive the light-emitting element L1 to emit light based on the data signal provided by the data writing circuit 021.

[0164] Optional, see reference Figure 5 The data writing circuit 021 may include: a data writing sub-circuit 0211 and a switching sub-circuit 0212.

[0165] The data writing sub-circuit 0211 can be coupled to the first scan line Scan1, the data signal line Data, and the switch sub-circuit 0212, respectively. The data writing sub-circuit 0211 can be configured to control the on / off state of the data signal line Data and the switch sub-circuit 0212 in response to the first scan signal.

[0166] The switch sub-circuit 0212 can also be coupled to the switch control line MUX1 and the drive circuit 022 respectively. The switch sub-circuit 0212 can also be configured to control the on / off state of the control data writing sub-circuit 0211 and drive circuit 022 in response to the switch control signal.

[0167] Optional, see reference Figure 6 The display substrate may further include: multiple first light-emitting control lines EM1, multiple second light-emitting control lines EM2, multiple second scan lines Scan2, multiple initialization signal lines Vinit, and multiple first power supply lines ELVDD, located in the display area AA and the non-display area BB, and coupled to multiple pixel circuit subgroups Z11 in multiple pixel circuit groups Z1. The driving circuit 022 may include: an initialization circuit 0221 and a light-emitting driving circuit 0222.

[0168] The initialization circuit 0221 can be coupled to the second scan line Scan2, the initialization signal line Vinit, the light-emitting driving circuit 0222, and the first electrode of the light-emitting element L1, respectively. The initialization circuit 0221 can be configured to control the switching of the initialization signal line Vinit with the light-emitting driving circuit 0222 and the first electrode of the light-emitting element L1 in response to the second scan signal provided by the second scan line Scan2.

[0169] The light-emitting driving circuit 0222 can also be coupled to the data writing circuit 021, the first power line ELVDD, the first light-emitting control line EM1, the second light-emitting control line EM2, and the first electrode of the light-emitting element L1, respectively. The light-emitting driving circuit 0222 can be configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element L1 in response to the data signal provided by the data writing circuit 021, the first light-emitting control signal provided by the first light-emitting control line EM1, the second light-emitting control signal provided by the second light-emitting control line EM2, and the first power signal provided by the first power line ELVDD.

[0170] The second electrode of the light-emitting element L1 can be configured to be coupled to the second power line ELVSS, and the light-emitting element L1 can be configured to emit light based on the light-emitting driving signal and the second power signal provided by the second power line ELVSS. Based on this, it can also be determined that, in addition to the signal lines mentioned above, the display substrate may also include a second power line ELVSS for the second electrode of the light-emitting element L1 to be connected.

[0171] Optional, see reference Figure 7 The light-emitting driving circuit 0222 may include: a storage sub-circuit 02221, a light-emitting control sub-circuit 02222, and a driving sub-circuit 02223.

[0172] The storage sub-circuit 02221 can be coupled to the data writing circuit 021 and the light-emitting control sub-circuit 02222, respectively. The storage sub-circuit 02221 can be configured to adjust the potential at the coupling point.

[0173] The light-emitting control sub-circuit 02222 can also be coupled to the first light-emitting control line EM1, the second light-emitting control line EM2, the first power line ELVDD, the data writing circuit 021, and the driver sub-circuit 02223, respectively. The light-emitting control sub-circuit 02222 can be configured to control the on / off state of the first power line ELVDD and the driver sub-circuit 02223 in response to the first light-emitting control signal and the second light-emitting control signal.

[0174] The driving sub-circuit 02223 can also be coupled to the first electrode of the light-emitting element L1. The driving sub-circuit 02223 can be configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element L1 in response to a signal provided by the light-emitting control sub-circuit 02222.

[0175] Optional, see reference Figure 8 The data writing sub-circuit 0211 may include a data writing transistor T1. The gate of the data writing transistor T1 may be coupled to the first scan line Scan1, the first terminal of the data writing transistor T1 may be coupled to the data signal line Data, and the second terminal of the data writing transistor T1 may be coupled to the switching sub-circuit 0212.

[0176] The switching sub-circuit 0212 may include a switching transistor T2. The gate of the switching transistor T2 may be coupled to the switching control line MUX1, the first terminal of the switching transistor T2 may be coupled to the data writing sub-circuit 0211, and the second terminal of the switching transistor T2 may be coupled to the driving circuit 022.

[0177] The light-emitting control sub-circuit 02222 may include: a first light-emitting control transistor T3, a second light-emitting control transistor T4, and a third light-emitting control transistor T5.

[0178] The gate of the first light-emitting control transistor T3 can be coupled to the first light-emitting control line EM1, the first terminal of the first light-emitting control transistor T3 can be coupled to the first power supply line ELVDD, and the second terminal of the first light-emitting control transistor T3 can be coupled to the first terminal of the third light-emitting control transistor T5.

[0179] The gate of the second light-emitting control transistor T4 can be coupled to the first light-emitting control line EM1, the first terminal of the second light-emitting control transistor T4 can be coupled to the data writing circuit 021, and the second terminal of the second light-emitting control transistor T4 can be coupled to the driving sub-circuit 02223 and the initialization circuit 0221.

[0180] The gate of the third light-emitting control transistor T5 can be coupled to the second light-emitting control line EM2, and the second terminal of the third light-emitting control transistor T5 can be coupled to the driver sub-circuit 02223.

[0181] The driver sub-circuit 02223 may include: driver transistor T8.

[0182] The gate of the driving transistor T8 can be coupled to the light-emitting control sub-circuit 02222 and the initialization circuit 0221 respectively. The first terminal of the driving transistor T8 can be coupled to the light-emitting control sub-circuit 02222, and the second terminal of the driving transistor T8 can be coupled to the first terminal of the light-emitting element L1.

[0183] The storage sub-circuit 02221 may include: a storage capacitor C1, the first end of which may be coupled to the data writing circuit 021, and the second end of which may be coupled to the light-emitting control sub-circuit 02222.

[0184] The initialization circuit 0221 may include: a first initialization transistor T6 and a second initialization transistor T7.

[0185] The gate of the first initialization transistor T6 and the gate of the second initialization transistor T7 can both be coupled to the second scan line Scan2. The first electrode of the first initialization transistor T6 and the first electrode of the second initialization transistor T7 can both be coupled to the initialization signal line Vinit. The second electrode of the first initialization transistor T6 can be coupled to the light-emitting driving circuit 0222. The second electrode of the second initialization transistor T7 can be coupled to the first electrode of the light-emitting element L1.

[0186] It should be noted that the specific structure and working principle of each circuit and sub-circuit in pixel circuit 02 can be referred to the corresponding content in the above-mentioned display substrate embodiment, and will not be repeated here.

[0187] Figure 13 This is a flowchart of a pixel circuit driving method provided in an embodiment of this disclosure, used to drive such... Figure 2 , Figures 5 to 8 Any pixel circuit shown. (e.g.) Figure 13 As shown, the method includes:

[0188] Step 1301, Initialization Phase: The potential of the second scan signal provided by the second scan line and the potential of the first light emission control signal provided by the first light emission control line are both the first potential. The potential of the first scan signal provided by the first scan line, the potential of the switch control signal provided by the switch control line, and the potential of the second light emission control signal provided by the second light emission control line are all the second potential. The initialization circuit responds to the second scan signal and controls the initialization signal line to be connected to the third node and the first pole of the light emission element, so that the initialization signal line transmits the initialization signal to the third node and the first pole of the light emission element. The light emission control sub-circuit responds to the first light emission control signal and controls the first node to be connected to the third node, and controls the first power line to be connected to the second node, so that the first power line transmits the first power signal to the second node.

[0189] Step 1302, Data Writing Stage: The potentials of the first scan signal, the second scan signal, the switch control signal, and the second light-emitting control signal provided by the second light-emitting control line are all at the first potential, and the potential of the first light-emitting control signal is at the second potential. The initialization circuit responds to the second scan signal and controls the initialization signal line to be connected to the third node and the first pole of the light-emitting element. The data writing circuit responds to the first scan signal and the switch control signal and controls the data signal line to be connected to the first node so that the data signal line transmits the data signal from the data line to the first node. The light-emitting control sub-circuit responds to the second light-emitting control signal and controls the second node to be connected to the fourth node.

[0190] Step 1303, Light Emission Stage: The potentials of the first light emission control signal and the second light emission control signal are both the first potential, while the potentials of the first scan signal, the second scan signal, and the switch control signal are all the second potential. The light emission control sub-circuit responds to the first light emission control signal by controlling the first power line to conduct with the second node and controlling the first node to conduct with the third node. In response to the second light emission control signal, it controls the second node to conduct with the fourth node. The driving sub-circuit transmits a light emission driving signal to the first electrode of the light emission element based on the potentials of the third node and the fourth node, thereby driving the light emission element to emit light.

[0191] It should be noted that the specific implementation methods of steps 1301 to 1303 can be referred to the corresponding content in the above-mentioned display substrate embodiment, and will not be repeated here.

[0192] Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Figure 14 As shown, the display device includes: a first driving circuit 10, a second driving circuit 20, and as shown in the figure. Figure 1 , Figure 3 , Figure 4 and Figure 9 Any of the display substrates shown 00.

[0193] The first driving circuit 10 can be coupled to multiple switch control lines MUX1 in the display substrate 00, and the first driving circuit 10 can be configured to provide switch control signals to the multiple switch control lines MUX1. The second driving circuit 20 can be coupled to multiple data lines Data in the display substrate 00, and the second driving circuit 20 can be configured to provide data signals to the multiple data lines Data.

[0194] Optionally, the first driving circuit and the second driving circuit can be integrated, such as by integrating them into the source driving circuit Driver IC described in the above embodiments. Alternatively, the first driving circuit and the second driving circuit can also be configured independently of each other.

[0195] Optionally, the display device described in the embodiments of this disclosure can be any product or component with display function, such as an OLED display device, an AMOLED device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0196] The terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0197] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0198] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0199] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0200] "Up," "down," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0201] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0202] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the gate drive circuit, shift register unit, various circuits and sub-circuits described above can be referred to the corresponding processes in the method embodiments, and will not be repeated here.

[0203] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display substrate, characterized in that, The display substrate includes: A substrate having a display area and a non-display area at least partially surrounding the display area; Multiple light-emitting elements are located in the display area; Multiple pixel circuit groups are located in the display area, at least one of the pixel circuit groups includes multiple pixel circuit subgroups arranged along a first direction, and each pixel circuit subgroup includes multiple pixel circuits arranged along a second direction, wherein the first direction and the second direction intersect. Multiple first scan lines and multiple data signal lines are located in the display area and the non-display area, and are coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups; Multiple switch control lines and multiple data lines are located in the non-display area and are coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups; At least one of the pixel circuits includes a data writing circuit and a driving circuit. The data writing circuit is coupled to the first scan line, the switch control line, the data signal line, and the driving circuit, respectively. The data writing circuit is configured to control the on / off state of the data signal line and the driving circuit in response to a first scan signal provided by the first scan line and a switch control signal provided by the switch control line. The driving circuit is also coupled to the light-emitting element and is configured to drive the light-emitting element to emit light based on the data signal provided by the data writing circuit. Furthermore, the same pixel circuit subgroup is coupled to the same switch control line and the same data signal line; multiple pixel circuit subgroups in the same pixel circuit group are coupled to different switch control lines, and multiple data signal lines coupled to multiple pixel circuit subgroups in the same pixel circuit group are coupled to the same data line and receive data signals from the data line.

2. The display substrate according to claim 1, characterized in that, In different pixel circuit groups, at least two pixel circuit subgroups share one of the multiple switch control lines.

3. The display substrate according to claim 2, characterized in that, In the plurality of pixel circuit groups, each pixel circuit group includes multiple pixel circuit subgroups that share the plurality of switch control lines.

4. The display substrate according to any one of claims 1 to 3, characterized in that, Each pixel circuit group includes a number of pixel circuit subgroups that are greater than or equal to 2 and less than or equal to 5.

5. The display substrate according to any one of claims 1 to 3, characterized in that, The plurality of switch control lines and the plurality of first scan lines extend along the first direction; The plurality of data signal lines and the plurality of data lines extend along the second direction.

6. The display substrate according to any one of claims 1 to 3, characterized in that, The first direction is perpendicular to the second direction.

7. The display substrate according to any one of claims 1 to 3, characterized in that, The multiple switch control lines are configured to provide switch control signals to the data writing circuits of different pixel circuit subgroups at different times.

8. The display substrate according to any one of claims 1 to 3, characterized in that, The data writing circuit includes: a data writing sub-circuit and a switching sub-circuit; The data writing sub-circuit is coupled to the first scan line, the data signal line and the switch sub-circuit respectively. The data writing sub-circuit is configured to control the on / off state of the data signal line and the switch sub-circuit in response to the first scan signal. The switch sub-circuit is also coupled to the switch control line and the drive circuit respectively. The switch sub-circuit is configured to control the on / off state of the data writing sub-circuit and the drive circuit in response to the switch control signal.

9. The display substrate according to claim 8, characterized in that, The data writing sub-circuit includes: a data writing transistor; The gate of the data writing transistor is coupled to the first scan line, the first electrode of the data writing transistor is coupled to the data signal line, and the second electrode of the data writing transistor is coupled to the switch sub-circuit.

10. The display substrate according to claim 8, characterized in that, The switching sub-circuit includes: a switching transistor; The gate of the switching transistor is coupled to the switching control line, the first terminal of the switching transistor is coupled to the data writing sub-circuit, and the second terminal of the switching transistor is coupled to the driving circuit.

11. The display substrate according to any one of claims 1 to 3, characterized in that, The display substrate further includes: multiple first light-emitting control lines, multiple second light-emitting control lines, multiple second scan lines, multiple initialization signal lines, and multiple first power lines, located in the display area and the non-display area, and coupled to multiple pixel circuit subgroups in the multiple pixel circuit groups; the driving circuit includes: an initialization circuit and a light-emitting driving circuit; The initialization circuit is coupled to the second scan line, the initialization signal line, the light-emitting driving circuit, and the first electrode of the light-emitting element, respectively. The initialization circuit is configured to control the on / off state of the initialization signal line with the light-emitting driving circuit and the first electrode of the light-emitting element in response to the second scan signal provided by the second scan line. The light-emitting driving circuit is also coupled to the data writing circuit, the first power line, the first light-emitting control line, the second light-emitting control line, and the first electrode of the light-emitting element. The light-emitting driving circuit is configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element in response to the data signal provided by the data writing circuit, the first light-emitting control signal provided by the first light-emitting control line, the second light-emitting control signal provided by the second light-emitting control line, and the first power signal provided by the first power line. The second electrode of the light-emitting element is configured to be coupled to the second power line, and the light-emitting element is configured to emit light based on the light-emitting drive signal and the second power signal provided by the second power line.

12. The display substrate according to claim 11, characterized in that, The light-emitting driving circuit includes: a storage sub-circuit, a light-emitting control sub-circuit, and a driving sub-circuit; The storage sub-circuit is coupled to the data writing circuit and the light emission control sub-circuit respectively, and the storage sub-circuit is configured to adjust the potential at the coupling point; The light emission control sub-circuit is also coupled to the first light emission control line, the second light emission control line, the first power supply line, the data writing circuit and the driving sub-circuit respectively. The light emission control sub-circuit is configured to control the on / off state of the first power supply line and the driving sub-circuit in response to the first light emission control signal and the second light emission control signal. The driving sub-circuit is also coupled to the first electrode of the light-emitting element, and the driving sub-circuit is configured to transmit a light-emitting driving signal to the first electrode of the light-emitting element in response to a signal provided by the light-emitting control sub-circuit.

13. The display substrate according to claim 12, characterized in that, The light-emitting control sub-circuit includes: a first light-emitting control transistor, a second light-emitting control transistor, and a third light-emitting control transistor; The gate of the first light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the first light-emitting control transistor is coupled to the first power supply line, and the second electrode of the first light-emitting control transistor is coupled to the first electrode of the third light-emitting control transistor. The gate of the second light-emitting control transistor is coupled to the first light-emitting control line, the first electrode of the second light-emitting control transistor is coupled to the data writing circuit, and the second electrode of the second light-emitting control transistor is coupled to the driving sub-circuit and the initialization circuit. The gate of the third light-emitting control transistor is coupled to the second light-emitting control line, and the second electrode of the third light-emitting control transistor is coupled to the driving sub-circuit.

14. The display substrate according to claim 12, characterized in that, The driving sub-circuit includes: a driving transistor; The gate of the driving transistor is coupled to the light-emitting control sub-circuit and the initialization circuit, respectively. The first electrode of the driving transistor is coupled to the light-emitting control sub-circuit, and the second electrode of the driving transistor is coupled to the first electrode of the light-emitting element.

15. The display substrate according to claim 12, characterized in that, The storage sub-circuit includes: a storage capacitor; The first end of the storage capacitor is coupled to the data writing circuit, and the second end of the storage capacitor is coupled to the light-emitting control sub-circuit.

16. The display substrate according to claim 11, characterized in that, The initialization circuit includes: a first initialization transistor and a second initialization transistor; The gates of the first initialization transistor and the second initialization transistor are both coupled to the second scan line. The first terminals of the first initialization transistor and the second initialization transistor are both coupled to the initialization signal line. The second terminal of the first initialization transistor is coupled to the light-emitting driving circuit, and the second terminal of the second initialization transistor is coupled to the first terminal of the light-emitting element.

17. A driving method for a display substrate, characterized in that, The method, configured to drive a display substrate as described in any one of claims 1 to 16, comprises: Multiple switch control lines provide switch control signals at different times, and multiple first scan lines provide first scan signals at different times. The data writing circuits in the multiple pixel circuits of different pixel circuit subgroups respond in a time-division manner to the first scan signal and the switch control signal, controlling the data signal line to be connected to the driving circuit so that the data signal line transmits the data signal from the data line to the driving circuit.

18. A display device, characterized in that, The display device includes: a first driving circuit, a second driving circuit, and a display substrate as described in any one of claims 1 to 16; The first driving circuit is coupled to multiple switch control lines in the display substrate, and the first driving circuit is configured to provide switch control signals to the multiple switch control lines; The second driving circuit is coupled to multiple data lines in the display substrate, and the second driving circuit is configured to provide data signals to the multiple data lines.

19. The display device according to claim 18, characterized in that, The first driving circuit and the second driving circuit are integrated.

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